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mii: clean up empty lines in .c and .h files

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This commit is contained in:
Mateusz Guzik 2020-09-01 22:07:59 +00:00
parent 5ef3520a33
commit 0077d05cae
11 changed files with 3 additions and 33 deletions
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1
sys/dev/mii/amphyreg.h
View File

@ -41,7 +41,6 @@
* AMD Am79C873 registers.
*/
#define MII_AMPHY_DSCR 0x10 /* Specified configuration register */a
#define DSCR_BP4B5B 0x8000 /* Bypass 4B5B encoding */
#define DSCR_BPSCR 0x4000 /* Bypass scrambler */

14
sys/dev/mii/bmtphyreg.h
View File

@ -49,7 +49,6 @@
#define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
#define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
#define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
#define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
#define AUX_STS_LOCKED 0x0200 /* descrambler locked */
@ -63,22 +62,17 @@
#define AUX_STS_LOCKERROR 0x0002 /* lock error detected */
#define AUX_STS_MLT3ERROR 0x0001 /* MLT3 code error detected */
#define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */
#define RXERROR_CTR_MASK 0x00ff
#define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */
#define FCS_CTR_MASK 0x00ff
#define MII_BMTPHY_DIS_CTR 0x14 /* 100base-X disconnect counter */
#define DIS_CTR_MASK 0x00ff
#define MII_BMTPHY_PTEST 0x17 /* PTEST */
#define MII_BMTPHY_AUX_CSR 0x18 /* auxiliary control/status */
#define AUX_CSR_JABBER_DIS 0x8000 /* jabber disable */
#define AUX_CSR_FLINK 0x4000 /* force 10baseT link pass */
@ -91,7 +85,6 @@
#define AUX_CSR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
#define AUX_CSR_FDX 0x0001 /* full-duplex */
#define MII_BMTPHY_AUX_SS 0x19 /* auxiliary status summary */
#define AUX_SS_ACOMP 0x8000 /* auto-negotiation complete */
#define AUX_SS_ACOMP_ACK 0x4000 /* auto-negotiation compl. ack */
@ -114,7 +107,6 @@
#define AUX_SS_ANEN 0x0002 /* auto-neg. enabled */
#define AUX_SS_JABBER 0x0001 /* jabber detected */
#define MII_BMTPHY_INTR 0x1a /* interrupt register */
#define INTR_FDX_LED 0x8000 /* full-duplex led enable */
#define INTR_INTR_EN 0x4000 /* interrupt enable */
@ -127,7 +119,6 @@
#define INTR_LINK_CHANGE 0x0002 /* link change */
#define INTR_INTR_STATUS 0x0001 /* interrupt status */
#define MII_BMTPHY_AUX2 0x1b /* auliliary mode 2 */
#define AUX2_BLOCK_RXDV 0x0200 /* block RXDV mode enabled */
#define AUX2_ANPDQ 0x0100 /* auto-neg parallel detection Q mode */
@ -138,7 +129,6 @@
#define AUX2_TWOLINK_LED 0x0004 /* two link LEDs */
#define AUX2_SQE_DIS 0x0002 /* disable SQE pulse */
#define MII_BMTPHY_AUXERR 0x1c /* auxiliary error */
#define AUXERR_MANCHESTER 0x0400 /* Manchester code error */
#define AUXERR_EOF 0x0200 /* EOF detection error */
@ -148,13 +138,11 @@
#define AUXERR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
#define AUXERR_FDX 0x0001 /* full-duplex */
#define MII_BMTPHY_AUXMODE 0x1d /* auxiliary mode */
#define AUXMODE_ACT_LED_DIS 0x0010 /* activity LED disable */
#define AUXMODE_LINK_LED_DIS 0x0008 /* link LED disable */
#define AUXMODE_BLOCK_TXEN 0x0002 /* enable block TXEN */
#define MII_BMTPHY_AUXMPHY 0x1e /* auxiliary multiple phy register */
#define AUXMPHY_HCD_TX_FDX 0x8000 /* res. is 100baseTX-FDX */
#define AUXMPHY_HCD_T4 0x4000 /* res. is 100baseT4 */
@ -169,8 +157,6 @@
#define AUXMPHY_SUPER_ISO 0x0008 /* super-isolate mode */
#define AUXMPHY_10T_SERIAL 0x0002 /* 10baseT serial mode */
#define MII_BMTPHY_TEST 0x1d /* Broadcom test register */
#endif /* _DEV_MII_BMTPHYREG_H_ */

3
sys/dev/mii/brgphy.c
View File

@ -381,7 +381,6 @@ brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
if (sc->mii_ticks <= sc->mii_anegticks)
break;
/* Retry autonegotiation */
sc->mii_ticks = 0;
brgphy_mii_phy_auto(sc, ife->ifm_media);
@ -1031,7 +1030,6 @@ brgphy_reset(struct mii_softc *sc)
} else if (bce_sc) {
if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
/* Store autoneg capabilities/results in digital block (Page 0) */
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
@ -1080,7 +1078,6 @@ brgphy_reset(struct mii_softc *sc)
}
} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
/* Select the SerDes Digital block of the AN MMD. */
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);

1
sys/dev/mii/brgphyreg.h
View File

@ -360,7 +360,6 @@
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001

1
sys/dev/mii/icsphyreg.h
View File

@ -94,7 +94,6 @@
#define TTR_NOLINK 0x0002 /* Disable Link check */
#define TTR_NOSQUELCH 0x0001 /* Disable squelch */
/*
* Extended Control Register 2
*

1
sys/dev/mii/mlphy.c
View File

@ -237,7 +237,6 @@ mlphy_service(xsc, mii, cmd)
break;
default:
return (EINVAL);
}
break;

7
sys/dev/mii/nsphyterreg.h
View File

@ -71,14 +71,12 @@
#define PHYSTS_MP_JABBER 0x0020 /* jabber detect */
#define PHYSTS_MP_NWAYCOMP 0x0010 /* NWAY complete */
#define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific
control */
#define MIPSCR_INTEN 0x0002 /* interrupt enable */
#define MIPSCR_TINT 0x0001 /* test interrupt */
#define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic
status */
#define MIPGSR_MINT 0x8000 /* MII interrupt pending */
@ -96,7 +94,6 @@
#define MII_NSPHYTER_RECR 0x15 /* Receive error counter */
#define MII_NSPHYTER_PCSR 0x16 /* PCS configuration and status */
#define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
#define PCSR_FEFI_EN 0x4000 /* far end fault indication mode */
@ -121,7 +118,6 @@
#define PCSR_MP_SD_OPTION 0x0100 /* enhanced signal detection alg. */
#define PCSR_MP_NRZI_BYPASS 0x0004 /* NRZI bypass enabled */
/* The bits below are not on MacPHYTER. */
#define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */
#define LBR_BP_STRETCH 0x4000 /* bypass LED stretching */
@ -133,7 +129,6 @@
#define LBR_TW_LBEN 0x0020 /* TWISTER loopback enable */
#define LBR_10_ENDEC_LB 0x0010 /* 10Mb/s ENDEC loopback */
/* The bits below are not on MacPHYTER. */
#define MII_NSPHYTER_10BTSCR 0x18 /* 10baseT status and control */
#define BTSCR_AUI_TPI 0x2000 /* TREX operating mode */
@ -150,7 +145,6 @@
#define BTSCR_THIN_SEL 0x0008 /* thin ethernet select */
#define BTSCR_TX_FILT_DS 0x0004 /* TPI receive filter disable */
#define MII_NSPHYTER_PHYCTRL 0x19 /* PHY control */
#define PHYCTRL_TW_EQSEL 0x3000 /* TWISTER e.q. select */
#define PHYCTRL_BLW_DS 0x0800 /* TWISTER base line wander disable */
@ -166,7 +160,6 @@
#define PHYCTRL_MP_BP_STRETCH 0x0100 /* bypass LED stretching */
#define PHYCTRL_MP_PAUSE_STS 0x0080 /* pause status */
/* The bits below are MacPHYTER only. */
#define MII_MACPHYTER_TBTCTL 0x1a /* 10baseT Control */
#define TBTCTL_LOOPBACK_10_DIS 0x0100 /* loopback 10Mb/s disable */

2
sys/dev/mii/qsphy.c
View File

@ -32,7 +32,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
*

2
sys/dev/mii/rlswitch.c
View File

@ -136,7 +136,7 @@ rlswitch_attach(device_t dev)
#ifdef RL_DEBUG
rlswitch_phydump(dev);
#endif
#ifdef RL_VLAN
int val;

2
sys/dev/mii/tdkphyreg.h
View File

@ -72,7 +72,6 @@
#define INT_CTRL_RXERR 0x4000
#define INT_CTRL_JABBER 0x8000
#define MII_DIAG 18
#define DIAG_RLOCK 0x0100
#define DIAG_RPASS 0x0200
@ -80,5 +79,4 @@
#define DIAG_DUPLEX 0x0800
#define DIAG_NEGFAIL 0x1000
#endif

2
sys/dev/mii/tlphyreg.h
View File

@ -1,5 +1,5 @@
/* $NetBSD: tlphyreg.h,v 1.1 1998/08/10 23:59:58 thorpej Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*