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- Use naming convention the same as MIPS spec does: eliminate _sel1 sufix

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and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1
- Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes)
This commit is contained in:
Oleksandr Tymoshenko 2009-04-27 18:29:59 +00:00
parent ffb90c259e
commit 00c35cc20b
2 changed files with 35 additions and 21 deletions
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48
sys/mips/include/cpufunc.h
View File

@ -183,6 +183,28 @@ mips_wr_ ## n (uint32_t a0) \
mips_barrier(); \
} struct __hack
#define MIPS_RDRW32_COP0_SEL(n,r,s) \
static __inline uint32_t \
mips_rd_ ## n ## s(void) \
{ \
int v0; \
__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
: [v0] "=&r"(v0)); \
mips_barrier(); \
return (v0); \
} \
static __inline void \
mips_wr_ ## n ## s(uint32_t a0) \
{ \
__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
__XSTRING(COP0_SYNC)";" \
"nop;" \
"nop;" \
: \
: [a0] "r"(a0)); \
mips_barrier(); \
} struct __hack
#ifdef TARGET_OCTEON
static __inline void mips_sync_icache (void)
{
@ -197,6 +219,9 @@ static __inline void mips_sync_icache (void)
MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE);
MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG);
MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 1);
MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 2);
MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 3);
MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT);
MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX);
MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
@ -211,26 +236,15 @@ MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1);
MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2);
MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 3);
MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 1);
MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 2);
MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 3);
#undef MIPS_RDRW32_COP0
#define MIPS_RD_CONFIG_SEL(sel) \
static __inline uint32_t \
mips_rd_config_sel##sel(void) \
{ \
int v0; \
__asm __volatile("mfc0 %[v0], $16, " #sel " ;" \
: [v0] "=&r" (v0)); \
mips_barrier(); \
return (v0); \
}
MIPS_RD_CONFIG_SEL(1);
MIPS_RD_CONFIG_SEL(2);
MIPS_RD_CONFIG_SEL(3);
#undef MIPS_RD_CONFIG_SEL
static __inline register_t
intr_disable(void)
{

8
sys/mips/mips/cpu.c
View File

@ -89,7 +89,7 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo)
return;
/* Learn TLB size and L1 cache geometry. */
cfg1 = mips_rd_config_sel1();
cfg1 = mips_rd_config1();
cpuinfo->tlb_nentries =
((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
@ -226,14 +226,14 @@ cpu_identify(void)
if (!(cfg0 & MIPS3_CONFIG_CM))
return;
cfg1 = mips_rd_config_sel1();
cfg1 = mips_rd_config1();
printf(" Config1=0x%b\n", cfg1,
"\20\7COP2\6MDMX\5PerfCount\4WatchRegs\3MIPS16\2EJTAG\1FPU");
/* If config register selection 2 does not exist, exit. */
if (!(cfg1 & MIPS3_CONFIG_CM))
return;
cfg2 = mips_rd_config_sel2();
cfg2 = mips_rd_config2();
/*
* Config2 contains no useful information other then Config3
* existence flag
@ -242,7 +242,7 @@ cpu_identify(void)
/* If config register selection 3 does not exist, exit. */
if (!(cfg2 & MIPS3_CONFIG_CM))
return;
cfg3 = mips_rd_config_sel3();
cfg3 = mips_rd_config3();
/* Print Config3 if it contains any useful info */
if (cfg3 & ~(0x80000000))