minor cleanup
This commit is contained in:
parent
9a3009b800
commit
00e602a997
@ -55,20 +55,20 @@ HAL_BOOL
|
||||
ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
|
||||
{
|
||||
uint32_t isr, isr0, isr1;
|
||||
uint32_t mask2=0;
|
||||
uint32_t mask2;
|
||||
struct ath_hal_5212 *ahp = AH5212(ah);
|
||||
|
||||
isr = OS_REG_READ(ah, AR_ISR);
|
||||
mask2 = 0;
|
||||
if (isr & AR_ISR_BCNMISC) {
|
||||
uint32_t isr2;
|
||||
isr2 = OS_REG_READ(ah, AR_ISR_S2);
|
||||
uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
|
||||
if (isr2 & AR_ISR_S2_TIM)
|
||||
mask2 |= HAL_INT_TIM;
|
||||
if (isr2 & AR_ISR_S2_DTIM)
|
||||
mask2 |= HAL_INT_DTIM;
|
||||
if (isr2 & AR_ISR_S2_DTIMSYNC)
|
||||
mask2 |= HAL_INT_DTIMSYNC;
|
||||
if (isr2 & (AR_ISR_S2_CABEND ))
|
||||
if (isr2 & AR_ISR_S2_CABEND)
|
||||
mask2 |= HAL_INT_CABEND;
|
||||
}
|
||||
isr = OS_REG_READ(ah, AR_ISR_RAC);
|
||||
@ -137,7 +137,7 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
|
||||
{
|
||||
struct ath_hal_5212 *ahp = AH5212(ah);
|
||||
uint32_t omask = ahp->ah_maskReg;
|
||||
uint32_t mask,mask2;
|
||||
uint32_t mask, mask2;
|
||||
|
||||
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
|
||||
__func__, omask, ints);
|
||||
@ -171,7 +171,7 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
|
||||
if (ints & HAL_INT_DTIMSYNC)
|
||||
mask2 |= AR_IMR_S2_DTIMSYNC;
|
||||
if (ints & HAL_INT_CABEND)
|
||||
mask2 |= (AR_IMR_S2_CABEND );
|
||||
mask2 |= AR_IMR_S2_CABEND;
|
||||
}
|
||||
if (ints & HAL_INT_FATAL) {
|
||||
/*
|
||||
@ -184,15 +184,8 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
|
||||
/* Write the new IMR and store off our SW copy. */
|
||||
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
|
||||
OS_REG_WRITE(ah, AR_IMR, mask);
|
||||
OS_REG_WRITE(ah, AR_IMR_S2,
|
||||
(OS_REG_READ(ah, AR_IMR_S2) &
|
||||
~(AR_IMR_S2_TIM |
|
||||
AR_IMR_S2_DTIM |
|
||||
AR_IMR_S2_DTIMSYNC |
|
||||
AR_IMR_S2_CABEND |
|
||||
AR_IMR_S2_CABTO |
|
||||
AR_IMR_S2_TSFOOR ) )
|
||||
| mask2);
|
||||
OS_REG_WRITE(ah, AR_IMR_S2,
|
||||
(OS_REG_READ(ah, AR_IMR_S2) &~ AR_IMR_SR2_BCNMISC) | mask2);
|
||||
ahp->ah_maskReg = ints;
|
||||
|
||||
/* Re-enable interrupts if they were enabled before. */
|
||||
@ -200,7 +193,5 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
|
||||
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
|
||||
OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
|
||||
}
|
||||
|
||||
|
||||
return omask;
|
||||
}
|
||||
|
@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5212reg.h,v 1.5 2008/11/16 06:45:43 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef _DEV_ATH_AR5212REG_H_
|
||||
#define _DEV_ATH_AR5212REG_H_
|
||||
@ -534,6 +534,11 @@
|
||||
#define AR_IMR_S2_TSFOOR 0x80000000 /* TSF OOR */
|
||||
#define AR_IMR_S2_RESV0 0xE0F8FC00 /* Reserved */
|
||||
|
||||
/* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */
|
||||
#define AR_IMR_SR2_BCNMISC \
|
||||
(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \
|
||||
AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR)
|
||||
|
||||
#define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
|
||||
#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
|
||||
#define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */
|
||||
|
Loading…
Reference in New Issue
Block a user