Add support for microcode update on newer AMD CPUs (10h+)
This includes new code for parsing microcode files as well as the kernel-side change to apply the update on all processors at the same time. Developed with help from Borislav Petkov, formerly bp@amd64.org. Tested using Athlon II X2 processor on a system where BIOS does not have the latest microcode version: /boot/firmware/microcode_amd.bin: updating cpu /dev/cpuctl0 to revision 0x10000c7... done. The microcode file is taken from here: https://web.archive.org/web/20160528230514/http://www.amd64.org/microcode.html (note that the original site seems to be down at the moment) It can also be found here: https://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/amd-ucode Reviewed by: kib, stas MFC after: 2 weeks Relnotes: maybe Differential Revision: https://reviews.freebsd.org/D8384
This commit is contained in:
Andriy Gapon
parent
4ab1cdc5ad
commit
0112b52b61
@ -377,13 +377,24 @@ fail:
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return (ret);
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}
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/*
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* NB: MSR 0xc0010020, MSR_K8_UCODE_UPDATE, is not documented by AMD.
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* Coreboot, illumos and Linux source code was used to understand
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* its workings.
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*/
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static void
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amd_ucode_wrmsr(void *ucode_ptr)
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{
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uint32_t tmp[4];
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wrmsr_safe(MSR_K8_UCODE_UPDATE, (uintptr_t)ucode_ptr);
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do_cpuid(0, tmp);
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}
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static int
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update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td)
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{
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void *ptr = NULL;
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uint32_t tmp[4];
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int is_bound = 0;
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int oldcpu;
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void *ptr;
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int ret;
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if (args->size == 0 || args->data == NULL) {
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@ -394,41 +405,23 @@ update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td)
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DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__);
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return (EINVAL);
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}
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/*
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* XXX Might not require contignous address space - needs check
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* 16 byte alignment required. Rely on the fact that
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* malloc(9) always returns the pointer aligned at least on
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* the size of the allocation.
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*/
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ptr = contigmalloc(args->size, M_CPUCTL, 0, 0, 0xffffffff, 16, 0);
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if (ptr == NULL) {
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DPRINTF("[cpuctl,%d]: cannot allocate %zd bytes of memory",
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__LINE__, args->size);
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return (ENOMEM);
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}
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ptr = malloc(args->size + 16, M_CPUCTL, M_ZERO | M_WAITOK);
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if (copyin(args->data, ptr, args->size) != 0) {
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DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed",
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__LINE__, args->data, ptr, args->size);
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ret = EFAULT;
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goto fail;
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}
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oldcpu = td->td_oncpu;
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is_bound = cpu_sched_is_bound(td);
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set_cpu(cpu, td);
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critical_enter();
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/*
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* Perform update.
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*/
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wrmsr_safe(MSR_K8_UCODE_UPDATE, (uintptr_t)ptr);
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/*
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* Serialize instruction flow.
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*/
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do_cpuid(0, tmp);
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critical_exit();
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restore_cpu(oldcpu, is_bound, td);
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smp_rendezvous(NULL, amd_ucode_wrmsr, NULL, ptr);
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ret = 0;
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fail:
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if (ptr != NULL)
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contigfree(ptr, args->size, M_CPUCTL);
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free(ptr, M_CPUCTL);
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return (ret);
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}
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@ -2,7 +2,7 @@
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PROG= cpucontrol
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MAN= cpucontrol.8
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SRCS= cpucontrol.c intel.c amd.c via.c
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SRCS= cpucontrol.c intel.c amd.c amd10h.c via.c
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NO_WCAST_ALIGN=
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@ -33,6 +33,8 @@
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*/
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ucode_probe_t amd_probe;
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ucode_update_t amd_update;
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ucode_probe_t amd10h_probe;
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ucode_update_t amd10h_update;
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typedef struct amd_fw_header {
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uint32_t date; /* Update creation date. */
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@ -46,4 +48,45 @@ typedef struct amd_fw_header {
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#define AMD_MAGIC 0xaaaaaa
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/*
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* AMD family 10h and later.
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*/
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typedef struct amd_10h_fw_header {
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uint32_t data_code;
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uint32_t patch_id;
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uint16_t mc_patch_data_id;
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uint8_t mc_patch_data_len;
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uint8_t init_flag;
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uint32_t mc_patch_data_checksum;
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uint32_t nb_dev_id;
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uint32_t sb_dev_id;
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uint16_t processor_rev_id;
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uint8_t nb_rev_id;
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uint8_t sb_rev_id;
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uint8_t bios_api_rev;
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uint8_t reserved1[3];
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uint32_t match_reg[8];
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} amd_10h_fw_header_t;
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typedef struct equiv_cpu_entry {
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uint32_t installed_cpu;
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uint32_t fixed_errata_mask;
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uint32_t fixed_errata_compare;
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uint16_t equiv_cpu;
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uint16_t res;
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} equiv_cpu_entry_t;
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typedef struct section_header {
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uint32_t type;
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uint32_t size;
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} section_header_t;
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typedef struct container_header {
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uint32_t magic;
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} container_header_t;
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#define AMD_10H_MAGIC 0x414d44
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#define AMD_10H_EQUIV_TABLE_TYPE 0
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#define AMD_10H_uCODE_TYPE 1
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#endif /* !AMD_H */
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307
usr.sbin/cpucontrol/amd10h.c
Normal file
307
usr.sbin/cpucontrol/amd10h.c
Normal file
@ -0,0 +1,307 @@
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/*-
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* Copyright (c) 2012 Andriy Gapon <avg@FreeBSD.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <sys/mman.h>
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#include <sys/ioctl.h>
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#include <sys/ioccom.h>
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#include <sys/cpuctl.h>
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#include <machine/cpufunc.h>
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#include <machine/specialreg.h>
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#include <assert.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <err.h>
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#include "cpucontrol.h"
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#include "amd.h"
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int
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amd10h_probe(int fd)
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{
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char vendor[13];
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cpuctl_cpuid_args_t idargs;
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uint32_t family;
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uint32_t signature;
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int error;
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idargs.level = 0;
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error = ioctl(fd, CPUCTL_CPUID, &idargs);
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if (error < 0) {
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WARN(0, "ioctl()");
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return (1);
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}
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((uint32_t *)vendor)[0] = idargs.data[1];
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((uint32_t *)vendor)[1] = idargs.data[3];
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((uint32_t *)vendor)[2] = idargs.data[2];
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vendor[12] = '\0';
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if (strncmp(vendor, AMD_VENDOR_ID, sizeof(AMD_VENDOR_ID)) != 0)
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return (1);
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idargs.level = 1;
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error = ioctl(fd, CPUCTL_CPUID, &idargs);
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if (error < 0) {
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WARN(0, "ioctl()");
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return (1);
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}
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signature = idargs.data[0];
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family = ((signature >> 8) & 0x0f) + ((signature >> 20) & 0xff);
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if (family < 0x10)
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return (1);
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return (0);
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}
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/*
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* NB: the format of microcode update files is not documented by AMD.
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* It has been reverse engineered from studying Coreboot, illumos and Linux
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* source code.
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*/
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void
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amd10h_update(const char *dev, const char *path)
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{
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struct stat st;
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cpuctl_cpuid_args_t idargs;
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cpuctl_msr_args_t msrargs;
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cpuctl_update_args_t args;
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const amd_10h_fw_header_t *fw_header;
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const amd_10h_fw_header_t *selected_fw;
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const equiv_cpu_entry_t *equiv_cpu_table;
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const section_header_t *section_header;
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const container_header_t *container_header;
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const uint8_t *fw_data;
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uint8_t *fw_image;
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size_t fw_size;
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size_t selected_size;
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uint32_t revision;
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uint32_t new_rev;
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uint32_t signature;
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uint16_t equiv_id;
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int fd, devfd;
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unsigned int i;
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int error;
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assert(path);
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assert(dev);
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fd = -1;
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fw_image = MAP_FAILED;
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devfd = open(dev, O_RDWR);
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if (devfd < 0) {
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WARN(0, "could not open %s for writing", dev);
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return;
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}
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idargs.level = 1;
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error = ioctl(devfd, CPUCTL_CPUID, &idargs);
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if (error < 0) {
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WARN(0, "ioctl()");
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goto done;
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}
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signature = idargs.data[0];
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msrargs.msr = 0x0000008b;
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error = ioctl(devfd, CPUCTL_RDMSR, &msrargs);
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if (error < 0) {
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WARN(0, "ioctl(%s)", dev);
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goto done;
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}
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revision = (uint32_t)msrargs.data;
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WARNX(1, "found cpu family %#x model %#x "
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"stepping %#x extfamily %#x extmodel %#x.",
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(signature >> 8) & 0x0f, (signature >> 4) & 0x0f,
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(signature >> 0) & 0x0f, (signature >> 20) & 0xff,
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(signature >> 16) & 0x0f);
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WARNX(1, "microcode revision %#x", revision);
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/*
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* Open the firmware file.
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*/
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fd = open(path, O_RDONLY, 0);
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if (fd < 0) {
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WARN(0, "open(%s)", path);
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goto done;
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}
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error = fstat(fd, &st);
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if (error != 0) {
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WARN(0, "fstat(%s)", path);
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goto done;
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}
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if (st.st_size < 0 || (size_t)st.st_size <
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(sizeof(*container_header) + sizeof(*section_header))) {
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WARNX(2, "file too short: %s", path);
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goto done;
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}
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fw_size = st.st_size;
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/*
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* mmap the whole image.
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*/
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fw_image = (uint8_t *)mmap(NULL, st.st_size, PROT_READ,
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MAP_PRIVATE, fd, 0);
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if (fw_image == MAP_FAILED) {
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WARN(0, "mmap(%s)", path);
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goto done;
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}
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fw_data = fw_image;
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container_header = (const container_header_t *)fw_data;
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if (container_header->magic != AMD_10H_MAGIC) {
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WARNX(2, "%s is not a valid amd firmware: bad magic", path);
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goto done;
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}
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fw_data += sizeof(*container_header);
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fw_size -= sizeof(*container_header);
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section_header = (const section_header_t *)fw_data;
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if (section_header->type != AMD_10H_EQUIV_TABLE_TYPE) {
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WARNX(2, "%s is not a valid amd firmware: "
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"first section is not CPU equivalence table", path);
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goto done;
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}
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if (section_header->size == 0) {
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WARNX(2, "%s is not a valid amd firmware: "
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"first section is empty", path);
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goto done;
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}
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fw_data += sizeof(*section_header);
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fw_size -= sizeof(*section_header);
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if (section_header->size > fw_size) {
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WARNX(2, "%s is not a valid amd firmware: "
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"file is truncated", path);
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goto done;
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}
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if (section_header->size < sizeof(*equiv_cpu_table)) {
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WARNX(2, "%s is not a valid amd firmware: "
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"first section is too short", path);
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goto done;
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}
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equiv_cpu_table = (const equiv_cpu_entry_t *)fw_data;
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fw_data += section_header->size;
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fw_size -= section_header->size;
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equiv_id = 0;
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for (i = 0; equiv_cpu_table[i].installed_cpu != 0; i++) {
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if (signature == equiv_cpu_table[i].installed_cpu) {
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equiv_id = equiv_cpu_table[i].equiv_cpu;
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WARNX(3, "equiv_id: %x", equiv_id);
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break;
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}
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}
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if (equiv_id == 0) {
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WARNX(2, "CPU is not found in the equivalence table");
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goto done;
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}
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selected_fw = NULL;
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selected_size = 0;
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while (fw_size >= sizeof(*section_header)) {
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section_header = (const section_header_t *)fw_data;
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fw_data += sizeof(*section_header);
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fw_size -= sizeof(*section_header);
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if (section_header->type != AMD_10H_uCODE_TYPE) {
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WARNX(2, "%s is not a valid amd firmware: "
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"section has incorret type", path);
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goto done;
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}
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if (section_header->size > fw_size) {
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WARNX(2, "%s is not a valid amd firmware: "
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"file is truncated", path);
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goto done;
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}
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if (section_header->size < sizeof(*fw_header)) {
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WARNX(2, "%s is not a valid amd firmware: "
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"section is too short", path);
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goto done;
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}
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fw_header = (const amd_10h_fw_header_t *)fw_data;
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fw_data += section_header->size;
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fw_size -= section_header->size;
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if (fw_header->processor_rev_id != equiv_id)
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continue; /* different cpu */
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if (fw_header->patch_id <= revision)
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continue; /* not newer revision */
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if (fw_header->nb_dev_id != 0 || fw_header->sb_dev_id != 0) {
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WARNX(2, "Chipset-specific microcode is not supported");
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}
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WARNX(3, "selecting revision: %x", fw_header->patch_id);
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revision = fw_header->patch_id;
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selected_fw = fw_header;
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selected_size = section_header->size;
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}
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if (fw_size != 0) {
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WARNX(2, "%s is not a valid amd firmware: "
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"file is truncated", path);
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goto done;
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}
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|
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if (selected_fw != NULL) {
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WARNX(1, "selected ucode size is %zu", selected_size);
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fprintf(stderr, "%s: updating cpu %s to revision %#x... ",
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path, dev, revision);
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args.data = __DECONST(void *, selected_fw);
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args.size = selected_size;
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error = ioctl(devfd, CPUCTL_UPDATE, &args);
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if (error < 0) {
|
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fprintf(stderr, "failed.\n");
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warn("ioctl()");
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goto done;
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}
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fprintf(stderr, "done.\n");
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}
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msrargs.msr = 0x0000008b;
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error = ioctl(devfd, CPUCTL_RDMSR, &msrargs);
|
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if (error < 0) {
|
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WARN(0, "ioctl(%s)", dev);
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goto done;
|
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}
|
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new_rev = (uint32_t)msrargs.data;
|
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if (new_rev != revision)
|
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WARNX(0, "revision after update %#x", new_rev);
|
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|
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done:
|
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if (fd >= 0)
|
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close(fd);
|
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if (devfd >= 0)
|
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close(devfd);
|
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if (fw_image != MAP_FAILED)
|
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if (munmap(fw_image, st.st_size) != 0)
|
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warn("munmap(%s)", path);
|
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return;
|
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}
|
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@ -91,6 +91,7 @@ static struct ucode_handler {
|
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ucode_update_t *update;
|
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} handlers[] = {
|
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{ intel_probe, intel_update },
|
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{ amd10h_probe, amd10h_update },
|
||||
{ amd_probe, amd_update },
|
||||
{ via_probe, via_update },
|
||||
};
|
||||
|
||||
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Reference in New Issue
Block a user