[mips] [rt2880] Add oldest Ralink MIPS SOC RT2880 support code.
* Target module have ic plus etherswitch ip175c. * Also add etherswitch support code on rt driver. Reviewed by: mizhka Differential Revision: https://reviews.freebsd.org/D10336
This commit is contained in:
Adrian Chadd
parent
5c99cda025
commit
01c914420d
@ -152,6 +152,7 @@ RT3050F opt_rt305x.h
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RT305X opt_rt305x.h
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RT305X_UBOOT opt_rt305x.h
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RT305X_USE_UART opt_rt305x.h
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RT_MDIO opt_rt305x.h
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#
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# Options that affect the pmap.
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@ -70,6 +70,12 @@ __FBSDID("$FreeBSD$");
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#ifdef RT_MDIO
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#include <dev/mdio/mdio.h>
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#include <dev/etherswitch/miiproxy.h>
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#include "mdio_if.h"
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#endif
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#if 0
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#include <mips/rt305x/rt305x_sysctlvar.h>
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#include <mips/rt305x/rt305xreg.h>
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@ -91,6 +97,7 @@ __FBSDID("$FreeBSD$");
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#define RT_TX_WATCHDOG_TIMEOUT 5
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#define RT_CHIPID_RT2880 0x2880
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#define RT_CHIPID_RT3050 0x3050
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#define RT_CHIPID_RT5350 0x5350
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#define RT_CHIPID_MT7620 0x7620
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@ -99,6 +106,7 @@ __FBSDID("$FreeBSD$");
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#ifdef FDT
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/* more specific and new models should go first */
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static const struct ofw_compat_data rt_compat_data[] = {
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{ "ralink,rt2880-eth", RT_CHIPID_RT2880 },
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{ "ralink,rt3050-eth", RT_CHIPID_RT3050 },
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{ "ralink,rt3352-eth", RT_CHIPID_RT3050 },
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{ "ralink,rt3883-eth", RT_CHIPID_RT3050 },
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@ -166,6 +174,8 @@ static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs,
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static void rt_sysctl_attach(struct rt_softc *sc);
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#ifdef IF_RT_PHY_SUPPORT
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void rt_miibus_statchg(device_t);
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#endif
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#if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
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static int rt_miibus_readreg(device_t, int, int);
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static int rt_miibus_writereg(device_t, int, int, int);
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#endif
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@ -351,7 +361,7 @@ rt_attach(device_t dev)
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sc->mem_rid = 0;
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sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
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RF_ACTIVE);
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RF_ACTIVE | RF_SHAREABLE);
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if (sc->mem == NULL) {
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device_printf(dev, "could not allocate memory resource\n");
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error = ENXIO;
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@ -467,6 +477,9 @@ rt_attach(device_t dev)
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GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
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));
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if (sc->rt_chipid == RT_CHIPID_RT2880)
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RT_WRITE(sc, MDIO_CFG, MDIO_2880_100T_INIT);
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/* allocate Tx and Rx rings */
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for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
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error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i);
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@ -2733,16 +2746,20 @@ rt_sysctl_attach(struct rt_softc *sc)
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"Tx collision count for GDMA ports");
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}
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#ifdef IF_RT_PHY_SUPPORT
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#if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
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/* This code is only work RT2880 and same chip. */
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/* TODO: make RT3052 and later support code. But nobody need it? */
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static int
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rt_miibus_readreg(device_t dev, int phy, int reg)
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{
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struct rt_softc *sc = device_get_softc(dev);
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int dat;
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/*
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* PSEUDO_PHYAD is a special value for indicate switch attached.
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* No one PHY use PSEUDO_PHYAD (0x1e) address.
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*/
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#ifndef RT_MDIO
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if (phy == 31) {
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/* Fake PHY ID for bfeswitch attach */
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switch (reg) {
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@ -2754,13 +2771,14 @@ rt_miibus_readreg(device_t dev, int phy, int reg)
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return (0x6250); /* bfeswitch */
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}
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}
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#endif
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/* Wait prev command done if any */
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while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
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RT_WRITE(sc, MDIO_ACCESS,
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MDIO_CMD_ONGO ||
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((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) ||
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((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK));
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dat = ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
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((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK);
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RT_WRITE(sc, MDIO_ACCESS, dat);
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RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
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while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
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return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK);
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@ -2770,19 +2788,23 @@ static int
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rt_miibus_writereg(device_t dev, int phy, int reg, int val)
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{
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struct rt_softc *sc = device_get_softc(dev);
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int dat;
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/* Wait prev command done if any */
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while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
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RT_WRITE(sc, MDIO_ACCESS,
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MDIO_CMD_ONGO || MDIO_CMD_WR ||
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((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) ||
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((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) ||
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(val & MDIO_PHY_DATA_MASK));
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dat = MDIO_CMD_WR |
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((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
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((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) |
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(val & MDIO_PHY_DATA_MASK);
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RT_WRITE(sc, MDIO_ACCESS, dat);
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RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
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while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
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return (0);
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}
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#endif
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#ifdef IF_RT_PHY_SUPPORT
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void
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rt_miibus_statchg(device_t dev)
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{
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@ -2842,3 +2864,85 @@ DRIVER_MODULE(rt, simplebus, rt_driver, rt_dev_class, 0, 0);
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MODULE_DEPEND(rt, ether, 1, 1, 1);
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MODULE_DEPEND(rt, miibus, 1, 1, 1);
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#ifdef RT_MDIO
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MODULE_DEPEND(rt, mdio, 1, 1, 1);
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static int rtmdio_probe(device_t);
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static int rtmdio_attach(device_t);
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static int rtmdio_detach(device_t);
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static struct mtx miibus_mtx;
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MTX_SYSINIT(miibus_mtx, &miibus_mtx, "rt mii lock", MTX_DEF);
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/*
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* Declare an additional, separate driver for accessing the MDIO bus.
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*/
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static device_method_t rtmdio_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, rtmdio_probe),
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DEVMETHOD(device_attach, rtmdio_attach),
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DEVMETHOD(device_detach, rtmdio_detach),
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/* bus interface */
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DEVMETHOD(bus_add_child, device_add_child_ordered),
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/* MDIO access */
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DEVMETHOD(mdio_readreg, rt_miibus_readreg),
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DEVMETHOD(mdio_writereg, rt_miibus_writereg),
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};
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DEFINE_CLASS_0(rtmdio, rtmdio_driver, rtmdio_methods,
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sizeof(struct rt_softc));
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static devclass_t rtmdio_devclass;
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DRIVER_MODULE(miiproxy, rt, miiproxy_driver, miiproxy_devclass, 0, 0);
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DRIVER_MODULE(rtmdio, simplebus, rtmdio_driver, rtmdio_devclass, 0, 0);
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DRIVER_MODULE(mdio, rtmdio, mdio_driver, mdio_devclass, 0, 0);
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static int
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rtmdio_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "ralink,rt2880-mdio"))
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return (ENXIO);
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device_set_desc(dev, "FV built-in ethernet interface, MDIO controller");
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return(0);
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}
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static int
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rtmdio_attach(device_t dev)
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{
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struct rt_softc *sc;
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int error;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->mem_rid = 0;
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sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->mem_rid, RF_ACTIVE | RF_SHAREABLE);
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if (sc->mem == NULL) {
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device_printf(dev, "couldn't map memory\n");
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error = ENXIO;
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goto fail;
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}
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sc->bst = rman_get_bustag(sc->mem);
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sc->bsh = rman_get_bushandle(sc->mem);
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bus_generic_probe(dev);
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bus_enumerate_hinted_children(dev);
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error = bus_generic_attach(dev);
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fail:
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return(error);
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}
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static int
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rtmdio_detach(device_t dev)
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{
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return(0);
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}
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#endif
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@ -48,6 +48,10 @@
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#define MDIO_PHY_DATA_MASK 0x0000ffff
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#define MDIO_PHY_DATA_SHIFT 0
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#define MDIO_CFG 0x04
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#define MDIO_2880_100T_INIT 0x1001BC01
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#define MDIO_2880_GIGA_INIT 0x1F01DC01
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#define FE_GLO_CFG 0x08 /*Frame Engine Global Configuration */
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#define EXT_VLAN_TYPE_MASK 0xffff0000
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#define EXT_VLAN_TYPE_SHIFT 16
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94
sys/gnu/dts/mips/MZK-W04N-XX.dts
Normal file
94
sys/gnu/dts/mips/MZK-W04N-XX.dts
Normal file
@ -0,0 +1,94 @@
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/dts-v1/;
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#include "rt2880.dtsi"
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/ {
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compatible = "MZK-WNH", "ralink,rt2880-soc";
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model = "Planex MZK-WNH";
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/*
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x2000000>;
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};
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*/
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cfi@1f000000 {
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compatible = "cfi-flash";
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reg = <0x1f000000 0x800000>;
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bank-width = <2>;
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device-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Bootloader";
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reg = <0x0 0x30000>;
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read-only;
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};
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devdata: partition@30000 {
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label = "Config";
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reg = <0x00030000 0x00010000>;
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read-only;
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};
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factory: partition@40000 {
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label = "Factory";
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reg = <0x00040000 0x00010000>;
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read-only;
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};
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kernel: partition@50000 {
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label = "kernel";
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reg = <0x00050000 0x000f0000>;
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read-only;
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};
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rootfs: partition@160000 {
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label = "rootfs";
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reg = <0x00140000 0x002c0000>;
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read-only;
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};
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upgrade: partition@400000 {
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label = "upgrade";
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reg = <0x00050000 0x003b0000>;
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read-only;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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status {
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label = "status";
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gpios = <&gpio0 12 0>;
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};
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio0 10 1>;
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linux,code = <0x198>;
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};
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};
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ip17x@0 {
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compatible = "icplus,ip17x";
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};
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};
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ðernet {
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mtd-mac-address = <&factory 0x28>;
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};
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&wmac {
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ralink,mtd-eeprom = <&factory 0>;
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};
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@ -5,7 +5,7 @@
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cpus {
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cpu@0 {
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compatible = "mips,mips24KEc";
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compatible = "mips,mips4KEc";
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};
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};
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@ -80,6 +80,9 @@
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ralink,register-map = [ 00 04 08 0c
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20 24 28 2c
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30 34 ];
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interrupt-parent = <&intc>;
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interrupts = <7>;
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};
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gpio1: gpio@638 {
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@ -182,13 +185,13 @@
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compatible = "ralink,rt2880-port", "mediatek,eth-port";
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reg = <0>;
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};
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};
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mdio-bus {
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compatible = "ralink,rt2880-mdio";
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reg = <0x00400000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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wmac: wmac@480000 {
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77
sys/mips/conf/RT2880_FDT
Normal file
77
sys/mips/conf/RT2880_FDT
Normal file
@ -0,0 +1,77 @@
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#
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# RT2880_FDT -- Kernel configuration file for FreeBSD/MIPS RT2880 SoC
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#
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# This includes all the configurable parts of the kernel.
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#
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# $FreeBSD$
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#
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#NO_UNIVERSE
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#
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# FDT_DTS_FILE should be modified to suit the target board type.
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#
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#makeoptions FDT_DTS_FILE=MZK-W04N-XX.dts
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# Start with a base configuration
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include "../mediatek/std.rt2880"
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ident RT2880
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cpu CPU_MIPS4KC
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# Don't build any modules by default
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makeoptions MODULES_OVERRIDE=""
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# Default rootfs device configuration, should be changed to suit target board
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options ROOTDEVNAME=\""ufs:md0.uzip\"
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# Support geom_uzip(4) compressed disk images
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device geom_map
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options GEOM_UZIP
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# Support md(4) and md-based rootfs
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device md
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options MD_ROOT
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# Interrupt controller support
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device mtk_intr_v1
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# UART device support
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nodevice uart_ns8250
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device uart_dev_mtk
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# SPI and SPI flash support
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device mtk_spi_v1
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device spibus
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device mx25l
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# CFI support
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device cfi
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device cfid
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# GPIO and gpioled support
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device mtk_gpio_v1
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device gpio
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device gpioled
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# USB (dwcotg) support
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device usb
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device mtk_usb_phy
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device dwcotg
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# USB umass(4) storage and da(4) support
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device umass
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device da
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# CAM support, required if umass(4) is enabled above
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device pass
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device scbus
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# Ethernet, BPF and bridge support
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device rt
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device bpf
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device if_bridge
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# Extres
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options EXT_RESOURCES
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device clk
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@ -146,7 +146,11 @@ mips_init(void)
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ctob(physmem) / (1024 * 1024));
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}
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if (ctob(physmem) < (448 * 1024 * 1024)) {
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if (mtk_soc_get_socid() == MTK_SOC_RT2880) {
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/* RT2880 memory start is 88000000 */
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dump_avail[1] = phys_avail[1] = ctob(physmem)
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+ 0x08000000;
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} else if (ctob(physmem) < (448 * 1024 * 1024)) {
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/*
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* Anything up to 448MB is assumed to be directly
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* mappable as low memory...
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@ -53,6 +53,7 @@ static uint32_t mtk_soc_cpuclk = MTK_CPU_CLK_880MHZ;
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static uint32_t mtk_soc_timerclk = MTK_CPU_CLK_880MHZ / 2;
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static const struct ofw_compat_data compat_data[] = {
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{ "ralink,rt2880-soc", MTK_SOC_RT2880 },
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{ "ralink,rt3050-soc", MTK_SOC_RT3050 },
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{ "ralink,rt3052-soc", MTK_SOC_RT3052 },
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{ "ralink,rt3350-soc", MTK_SOC_RT3350 },
|
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@ -76,6 +77,30 @@ static const struct ofw_compat_data compat_data[] = {
|
||||
{ NULL, MTK_SOC_UNKNOWN },
|
||||
};
|
||||
|
||||
static uint32_t
|
||||
mtk_detect_cpuclk_rt2880(bus_space_tag_t bst, bus_space_handle_t bsh)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
|
||||
val >>= RT2880_CPU_CLKSEL_OFF;
|
||||
val &= RT2880_CPU_CLKSEL_MSK;
|
||||
|
||||
switch (val) {
|
||||
case 0:
|
||||
return (MTK_CPU_CLK_250MHZ);
|
||||
case 1:
|
||||
return (MTK_CPU_CLK_266MHZ);
|
||||
case 2:
|
||||
return (MTK_CPU_CLK_280MHZ);
|
||||
case 3:
|
||||
return (MTK_CPU_CLK_300MHZ);
|
||||
}
|
||||
|
||||
/* Never reached */
|
||||
return (0);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
mtk_detect_cpuclk_rt305x(bus_space_tag_t bst, bus_space_handle_t bsh)
|
||||
{
|
||||
@ -260,7 +285,9 @@ mtk_soc_try_early_detect(void)
|
||||
}
|
||||
|
||||
bst = fdtbus_bs_tag;
|
||||
if (mtk_soc_socid == MTK_SOC_MT7621)
|
||||
if (mtk_soc_socid == MTK_SOC_RT2880)
|
||||
base = MTK_RT2880_BASE;
|
||||
else if (mtk_soc_socid == MTK_SOC_MT7621)
|
||||
base = MTK_MT7621_BASE;
|
||||
else
|
||||
base = MTK_DEFAULT_BASE;
|
||||
@ -270,6 +297,9 @@ mtk_soc_try_early_detect(void)
|
||||
|
||||
/* First, figure out the CPU clock */
|
||||
switch (mtk_soc_socid) {
|
||||
case MTK_SOC_RT2880:
|
||||
mtk_soc_cpuclk = mtk_detect_cpuclk_rt2880(bst, bsh);
|
||||
break;
|
||||
case MTK_SOC_RT3050: /* fallthrough */
|
||||
case MTK_SOC_RT3052:
|
||||
case MTK_SOC_RT3350:
|
||||
@ -327,6 +357,9 @@ mtk_soc_try_early_detect(void)
|
||||
}
|
||||
|
||||
switch (mtk_soc_socid) {
|
||||
case MTK_SOC_RT2880:
|
||||
mtk_soc_uartclk = mtk_soc_cpuclk / MTK_UARTDIV_2;
|
||||
break;
|
||||
case MTK_SOC_RT3350: /* fallthrough */
|
||||
case MTK_SOC_RT3050: /* fallthrough */
|
||||
case MTK_SOC_RT3052:
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
|
||||
enum mtk_soc_id {
|
||||
MTK_SOC_UNKNOWN,
|
||||
MTK_SOC_RT2880,
|
||||
MTK_SOC_RT3050,
|
||||
MTK_SOC_RT3052,
|
||||
MTK_SOC_RT3350,
|
||||
@ -47,6 +48,8 @@ enum mtk_soc_id {
|
||||
MTK_SOC_MAX
|
||||
};
|
||||
|
||||
#define RT2880_CPU_CLKSEL_OFF 20
|
||||
#define RT2880_CPU_CLKSEL_MSK 0x3
|
||||
#define RT305X_CPU_CLKSEL_OFF 18
|
||||
#define RT305X_CPU_CLKSEL_MSK 0x1
|
||||
#define RT3352_CPU_CLKSEL_OFF 8
|
||||
@ -91,7 +94,10 @@ enum mtk_soc_id {
|
||||
#define MTK_MHZ(x) ((x) * 1000 * 1000)
|
||||
|
||||
#define MTK_CPU_CLK_UNKNOWN 0
|
||||
#define MTK_CPU_CLK_233MHZ 233333333
|
||||
#define MTK_CPU_CLK_250MHZ 250000000
|
||||
#define MTK_CPU_CLK_266MHZ 266666666
|
||||
#define MTK_CPU_CLK_280MHZ 280000000
|
||||
#define MTK_CPU_CLK_300MHZ 300000000
|
||||
#define MTK_CPU_CLK_320MHZ 320000000
|
||||
#define MTK_CPU_CLK_360MHZ 360000000
|
||||
@ -111,6 +117,7 @@ enum mtk_soc_id {
|
||||
#define MTK_UARTDIV_3 3
|
||||
|
||||
#define MTK_DEFAULT_BASE 0x10000000
|
||||
#define MTK_RT2880_BASE 0x00300000
|
||||
#define MTK_MT7621_BASE 0x1e000000
|
||||
#define MTK_DEFAULT_SIZE 0x6000
|
||||
|
||||
|
||||
89
sys/mips/mediatek/std.rt2880
Normal file
89
sys/mips/mediatek/std.rt2880
Normal file
@ -0,0 +1,89 @@
|
||||
#
|
||||
# std.rt2880 -- Base kernel configuration file for FreeBSD/MIPS RT2800 SoC
|
||||
#
|
||||
# This includes all the required drivers for the SoCs.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
# Include the standard file list for Mediatek SoCs.
|
||||
files "../mediatek/files.mediatek"
|
||||
|
||||
# Building a mips/mipsel kernel
|
||||
machine mips mipsel
|
||||
|
||||
# Little-endian machine
|
||||
makeoptions MIPS_LITTLE_ENDIAN=defined
|
||||
|
||||
# Default kernel load address
|
||||
makeoptions KERNLOADADDR=0x88001000
|
||||
|
||||
# Mediatek/Ralink SoC support depends on FDT (with static DTB for the moment)
|
||||
options FDT
|
||||
options FDT_DTB_STATIC
|
||||
|
||||
# We rely on INTRNG code
|
||||
options INTRNG
|
||||
options MIPS_NIRQ=256
|
||||
|
||||
# We rely on NEW_PCIB code
|
||||
options NEW_PCIB
|
||||
|
||||
# Build kernel with gdb(1) debug symbols
|
||||
makeoptions DEBUG=-g
|
||||
|
||||
# Support for DDB and KDB
|
||||
options DDB
|
||||
options KDB
|
||||
|
||||
# Debugging for use in -current
|
||||
options INVARIANTS
|
||||
options INVARIANT_SUPPORT
|
||||
options WITNESS
|
||||
options WITNESS_SKIPSPIN
|
||||
options DEBUG_REDZONE
|
||||
options DEBUG_MEMGUARD
|
||||
|
||||
# For small memory footprints
|
||||
options VM_KMEM_SIZE_SCALE=1
|
||||
|
||||
# General options, including scheduler, etc.
|
||||
options SCHED_ULE # ULE scheduler
|
||||
options INET # InterNETworking
|
||||
#options INET6 # IPv6
|
||||
options PSEUDOFS # Pseude-filesystem framework
|
||||
options FFS # Berkeley Fast Filesystem
|
||||
#options SOFTUPDATES # Enable FFS soft updates support
|
||||
#options UFS_ACL # Support for access control lists
|
||||
#options UFS_DIRHASH # Improve big directory performance
|
||||
#options MSDOSFS # Enable support for MSDOS filesystems
|
||||
options _KPOSIX_PRIORITY_SCHEDULING # Posix P1003_1B real-time ext.
|
||||
|
||||
#
|
||||
# Standard drivers section
|
||||
#
|
||||
# The drivers in the following section are required in order to successfully
|
||||
# compile the kernel.
|
||||
#
|
||||
|
||||
# FDT clock and pinctrl framework
|
||||
device fdt_clock
|
||||
device fdt_pinctrl
|
||||
|
||||
# UART support
|
||||
device uart
|
||||
|
||||
# random support
|
||||
device random
|
||||
|
||||
# loop device support
|
||||
device loop
|
||||
|
||||
# ether device support
|
||||
device ether
|
||||
|
||||
# ether switch support
|
||||
#device etherswitch
|
||||
#device miibus
|
||||
#device ip17x
|
||||
#device mdio
|
||||
Loading…
Reference in New Issue
Block a user