d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Hide extended PerfCtr MSRs on AMD processors by clearing bits 23, 24 and 28 in

Browse Source 
CPUID.80000001H:ECX.

Handle accesses to PerfCtrX and PerfEvtSelX MSRs by ignoring writes and
returning 0 on reads.

This further reduces the number of unimplemented MSRs hit by a Linux guest
during boot.
This commit is contained in:
Neel Natu 2014-10-17 03:04:38 +00:00
parent 913d54b96e
commit 02904c45ab
2 changed files with 45 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
sys/amd64/vmm/x86.c
View File

@ -158,6 +158,14 @@ x86_emulate_cpuid(struct vm *vm, int vcpu_id,
*/
regs[2] &= ~(AMDID2_SVM | AMDID2_TOPOLOGY);
/*
* Don't advertise extended performance counter MSRs
* to the guest.
*/
regs[2] &= ~AMDID2_PCXC;
regs[2] &= ~AMDID2_PNXC;
regs[2] &= ~AMDID2_PTSCEL2I;
/*
* Hide rdtscp/ia32_tsc_aux until we know how
* to deal with them.

37
usr.sbin/bhyve/xmsr.c
View File

@ -68,6 +68,21 @@ emulate_wrmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t val)
* Ignore writes to hardware configuration MSR.
*/
return (0);
case MSR_PERFEVSEL0:
case MSR_PERFEVSEL1:
case MSR_PERFEVSEL2:
case MSR_PERFEVSEL3:
/* Ignore writes to the PerfEvtSel MSRs */
return (0);
case MSR_K7_PERFCTR0:
case MSR_K7_PERFCTR1:
case MSR_K7_PERFCTR2:
case MSR_K7_PERFCTR3:
/* Ignore writes to the PerfCtr MSRs */
return (0);
default:
break;
}
@ -111,6 +126,28 @@ emulate_rdmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t *val)
*val = 0x01000010; /* Reset value */
*val |= 1 << 9; /* MONITOR/MWAIT disable */
break;
case MSR_PERFEVSEL0:
case MSR_PERFEVSEL1:
case MSR_PERFEVSEL2:
case MSR_PERFEVSEL3:
/*
* PerfEvtSel MSRs are not properly virtualized so just
* return zero.
*/
*val = 0;
break;
case MSR_K7_PERFCTR0:
case MSR_K7_PERFCTR1:
case MSR_K7_PERFCTR2:
case MSR_K7_PERFCTR3:
/*
* PerfCtr MSRs are not properly virtualized so just
* return zero.
*/
*val = 0;
break;
default:
break;
}