Initial version of the sec(4) driver for the integrated security engine found
in Freescale system-on-chip devices. The following algorithms and schemes are currently supported: - 3DES, AES, DES - MD5, SHA1, SHA256, SHA384, SHA512 Reviewed by: philip Obtained from: Freescale, Semihalf
This commit is contained in:
Rafal Jaworowski
parent
ef0e1c230f
commit
02b553cafc
@ -39,6 +39,7 @@ dev/ofw/ofw_standard.c optional aim
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dev/powermac_nvram/powermac_nvram.c optional powermac_nvram powermac
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dev/quicc/quicc_bfe_ocp.c optional quicc mpc85xx
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dev/scc/scc_bfe_macio.c optional scc powermac
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dev/sec/sec.c optional sec mpc85xx
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dev/sound/macio/aoa.c optional snd_davbus | snd_ai2s powermac
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dev/sound/macio/davbus.c optional snd_davbus powermac
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dev/sound/macio/i2s.c optional snd_ai2s powermac
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1875
sys/dev/sec/sec.c
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1875
sys/dev/sec/sec.c
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File diff suppressed because it is too large
Load Diff
426
sys/dev/sec/sec.h
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426
sys/dev/sec/sec.h
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@ -0,0 +1,426 @@
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/*-
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* Copyright (C) 2008-2009 Semihalf, Piotr Ziecik
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SEC_H
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#define _SEC_H
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/*
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* Each SEC channel can hold up to 24 descriptors. All 4 channels can be
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* simultaneously active holding 96 descriptors. Each descriptor can use 0 or
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* more link table entries depending of size and granulation of input/output
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* data. One link table entry is needed for each 65535 bytes of data.
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*/
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/* Driver settings */
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#define SEC_TIMEOUT 100000
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#define SEC_MAX_SESSIONS 256
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#define SEC_DESCRIPTORS 256 /* Must be power of 2 */
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#define SEC_LT_ENTRIES 1024 /* Must be power of 2 */
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#define SEC_MAX_IV_LEN 16
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#define SEC_MAX_KEY_LEN 64
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/* SEC information */
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#define SEC_20_ID 0x0000000000000040ULL
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#define SEC_30_ID 0x0030030000000000ULL
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#define SEC_CHANNELS 4
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#define SEC_POINTERS 7
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#define SEC_MAX_DMA_BLOCK_SIZE 0xFFFF
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#define SEC_MAX_FIFO_LEVEL 24
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#define SEC_DMA_ALIGNMENT 8
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#define __packed__ __attribute__ ((__packed__))
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struct sec_softc;
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struct sec_session;
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/* SEC descriptor definition */
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struct sec_hw_desc_ptr {
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u_int shdp_length : 16;
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u_int shdp_j : 1;
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u_int shdp_extent : 7;
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u_int __padding0 : 4;
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uint64_t shdp_ptr : 36;
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} __packed__;
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struct sec_hw_desc {
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union __packed__ {
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struct __packed__ {
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u_int eu_sel0 : 4;
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u_int mode0 : 8;
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u_int eu_sel1 : 4;
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u_int mode1 : 8;
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u_int desc_type : 5;
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u_int __padding0 : 1;
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u_int dir : 1;
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u_int dn : 1;
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u_int __padding1 : 32;
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} request;
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struct __packed__ {
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u_int done : 8;
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u_int __padding0 : 27;
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u_int iccr0 : 2;
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u_int __padding1 : 6;
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u_int iccr1 : 2;
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u_int __padding2 : 19;
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} feedback;
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} shd_control;
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struct sec_hw_desc_ptr shd_pointer[SEC_POINTERS];
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/* Data below is mapped to descriptor pointers */
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uint8_t shd_iv[SEC_MAX_IV_LEN];
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uint8_t shd_key[SEC_MAX_KEY_LEN];
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uint8_t shd_mkey[SEC_MAX_KEY_LEN];
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} __packed__;
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#define shd_eu_sel0 shd_control.request.eu_sel0
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#define shd_mode0 shd_control.request.mode0
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#define shd_eu_sel1 shd_control.request.eu_sel1
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#define shd_mode1 shd_control.request.mode1
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#define shd_desc_type shd_control.request.desc_type
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#define shd_dir shd_control.request.dir
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#define shd_dn shd_control.request.dn
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#define shd_done shd_control.feedback.done
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#define shd_iccr0 shd_control.feedback.iccr0
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#define shd_iccr1 shd_control.feedback.iccr1
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/* SEC link table entries definition */
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struct sec_hw_lt {
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u_int shl_length : 16;
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u_int __padding0 : 6;
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u_int shl_r : 1;
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u_int shl_n : 1;
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u_int __padding1 : 4;
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uint64_t shl_ptr : 36;
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} __packed__;
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struct sec_dma_mem {
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void *dma_vaddr;
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bus_addr_t dma_paddr;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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u_int dma_is_map;
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};
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struct sec_desc {
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struct sec_hw_desc *sd_desc;
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bus_addr_t sd_desc_paddr;
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struct sec_dma_mem sd_ptr_dmem[SEC_POINTERS];
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struct cryptop *sd_crp;
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u_int sd_lt_used;
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u_int sd_error;
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};
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struct sec_lt {
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struct sec_hw_lt *sl_lt;
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bus_addr_t sl_lt_paddr;
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};
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struct sec_eu_methods {
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int (*sem_newsession)(struct sec_softc *sc,
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struct sec_session *ses, struct cryptoini *enc,
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struct cryptoini *mac);
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int (*sem_make_desc)(struct sec_softc *sc,
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struct sec_session *ses, struct sec_desc *desc,
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struct cryptop *crp, int buftype);
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};
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struct sec_session {
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u_int ss_used;
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struct sec_eu_methods *ss_eu;
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uint8_t ss_key[SEC_MAX_KEY_LEN];
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uint8_t ss_mkey[SEC_MAX_KEY_LEN];
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u_int ss_klen;
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u_int ss_mklen;
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u_int ss_ivlen;
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};
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struct sec_desc_map_info {
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struct sec_softc *sdmi_sc;
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bus_size_t sdmi_size;
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bus_size_t sdmi_offset;
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struct sec_lt *sdmi_lt_first;
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struct sec_lt *sdmi_lt_last;
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u_int sdmi_lt_used;
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};
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struct sec_softc {
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device_t sc_dev;
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int32_t sc_cid;
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int sc_blocked;
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int sc_shutdown;
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u_int sc_version;
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uint64_t sc_int_error_mask;
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uint64_t sc_channel_idle_mask;
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struct sec_session sc_sessions[SEC_MAX_SESSIONS];
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struct mtx sc_controller_lock;
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struct mtx sc_descriptors_lock;
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struct mtx sc_sessions_lock;
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struct sec_desc sc_desc[SEC_DESCRIPTORS];
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u_int sc_free_desc_get_cnt;
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u_int sc_free_desc_put_cnt;
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u_int sc_ready_desc_get_cnt;
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u_int sc_ready_desc_put_cnt;
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u_int sc_queued_desc_get_cnt;
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u_int sc_queued_desc_put_cnt;
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struct sec_lt sc_lt[SEC_LT_ENTRIES + 1];
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u_int sc_lt_alloc_cnt;
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u_int sc_lt_free_cnt;
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struct sec_dma_mem sc_desc_dmem; /* descriptors DMA memory */
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struct sec_dma_mem sc_lt_dmem; /* link tables DMA memory */
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struct resource *sc_rres; /* register resource */
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int sc_rrid; /* register rid */
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struct {
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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} sc_bas;
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struct resource *sc_pri_ires; /* primary irq resource */
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void *sc_pri_ihand; /* primary irq handler */
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int sc_pri_irid; /* primary irq resource id */
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struct resource *sc_sec_ires; /* secondary irq resource */
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void *sc_sec_ihand; /* secondary irq handler */
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int sc_sec_irid; /* secondary irq resource id */
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};
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/* Locking macros */
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#define SEC_LOCK(sc, what) \
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mtx_lock(&(sc)->sc_ ## what ## _lock)
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#define SEC_UNLOCK(sc, what) \
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mtx_unlock(&(sc)->sc_ ## what ## _lock)
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#define SEC_LOCK_ASSERT(sc, what) \
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mtx_assert(&(sc)->sc_ ## what ## _lock, MA_OWNED)
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/* Read/Write definitions */
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#define SEC_READ(sc, reg) \
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bus_space_read_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg))
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#define SEC_WRITE(sc, reg, val) \
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bus_space_write_8((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val))
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/* Base allocation macros (warning: wrap must be 2^n) */
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#define SEC_CNT_INIT(sc, cnt, wrap) \
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(((sc)->cnt) = ((wrap) - 1))
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#define SEC_ADD(sc, cnt, wrap, val) \
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((sc)->cnt = (((sc)->cnt) + (val)) & ((wrap) - 1))
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#define SEC_INC(sc, cnt, wrap) \
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SEC_ADD(sc, cnt, wrap, 1)
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#define SEC_DEC(sc, cnt, wrap) \
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SEC_ADD(sc, cnt, wrap, -1)
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#define SEC_GET_GENERIC(sc, tab, cnt, wrap) \
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((sc)->tab[SEC_INC(sc, cnt, wrap)])
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#define SEC_PUT_GENERIC(sc, tab, cnt, wrap, val) \
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((sc)->tab[SEC_INC(sc, cnt, wrap)] = val)
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/* Interface for descriptors */
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#define SEC_GET_FREE_DESC(sc) \
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&SEC_GET_GENERIC(sc, sc_desc, sc_free_desc_get_cnt, SEC_DESCRIPTORS)
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#define SEC_PUT_BACK_FREE_DESC(sc) \
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SEC_DEC(sc, sc_free_desc_get_cnt, SEC_DESCRIPTORS)
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#define SEC_DESC_FREE2READY(sc) \
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SEC_INC(sc, sc_ready_desc_put_cnt, SEC_DESCRIPTORS)
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#define SEC_GET_READY_DESC(sc) \
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&SEC_GET_GENERIC(sc, sc_desc, sc_ready_desc_get_cnt, SEC_DESCRIPTORS)
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#define SEC_PUT_BACK_READY_DESC(sc) \
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SEC_DEC(sc, sc_ready_desc_get_cnt, SEC_DESCRIPTORS)
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#define SEC_DESC_READY2QUEUED(sc) \
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SEC_INC(sc, sc_queued_desc_put_cnt, SEC_DESCRIPTORS)
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#define SEC_GET_QUEUED_DESC(sc) \
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&SEC_GET_GENERIC(sc, sc_desc, sc_queued_desc_get_cnt, SEC_DESCRIPTORS)
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#define SEC_PUT_BACK_QUEUED_DESC(sc) \
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SEC_DEC(sc, sc_queued_desc_get_cnt, SEC_DESCRIPTORS)
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#define SEC_DESC_QUEUED2FREE(sc) \
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SEC_INC(sc, sc_free_desc_put_cnt, SEC_DESCRIPTORS)
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#define SEC_FREE_DESC_CNT(sc) \
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(((sc)->sc_free_desc_put_cnt - (sc)->sc_free_desc_get_cnt - 1) \
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& (SEC_DESCRIPTORS - 1))
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#define SEC_READY_DESC_CNT(sc) \
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(((sc)->sc_ready_desc_put_cnt - (sc)->sc_ready_desc_get_cnt) & \
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(SEC_DESCRIPTORS - 1))
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#define SEC_QUEUED_DESC_CNT(sc) \
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(((sc)->sc_queued_desc_put_cnt - (sc)->sc_queued_desc_get_cnt) \
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& (SEC_DESCRIPTORS - 1))
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#define SEC_DESC_SYNC(sc, mode) do { \
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sec_sync_dma_mem(&((sc)->sc_desc_dmem), (mode)); \
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sec_sync_dma_mem(&((sc)->sc_lt_dmem), (mode)); \
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} while (0)
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#define SEC_DESC_SYNC_POINTERS(desc, mode) do { \
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u_int i; \
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for (i = 0; i < SEC_POINTERS; i++) \
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sec_sync_dma_mem(&((desc)->sd_ptr_dmem[i]), (mode)); \
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} while (0)
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#define SEC_DESC_FREE_POINTERS(desc) do { \
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u_int i; \
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for (i = 0; i < SEC_POINTERS; i++) \
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sec_free_dma_mem(&(desc)->sd_ptr_dmem[i]); \
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} while (0);
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#define SEC_DESC_PUT_BACK_LT(sc, desc) \
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SEC_PUT_BACK_LT(sc, (desc)->sd_lt_used)
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#define SEC_DESC_FREE_LT(sc, desc) \
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SEC_FREE_LT(sc, (desc)->sd_lt_used)
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/* Interface for link tables */
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#define SEC_ALLOC_LT_ENTRY(sc) \
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&SEC_GET_GENERIC(sc, sc_lt, sc_lt_alloc_cnt, SEC_LT_ENTRIES)
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#define SEC_PUT_BACK_LT(sc, num) \
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SEC_ADD(sc, sc_lt_alloc_cnt, SEC_LT_ENTRIES, -(num))
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#define SEC_FREE_LT(sc, num) \
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SEC_ADD(sc, sc_lt_free_cnt, SEC_LT_ENTRIES, num)
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#define SEC_FREE_LT_CNT(sc) \
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(((sc)->sc_lt_free_cnt - (sc)->sc_lt_alloc_cnt - 1) \
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& (SEC_LT_ENTRIES - 1))
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/* DMA Maping defines */
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#define SEC_MEMORY 0
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#define SEC_UIO 1
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#define SEC_MBUF 2
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/* Size of SEC registers area */
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#define SEC_IO_SIZE 0x10000
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/* SEC Controller registers */
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#define SEC_IER 0x1008
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#define SEC_INT_CH_DN(n) (1ULL << (((n) * 2) + 32))
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#define SEC_INT_CH_ERR(n) (1ULL << (((n) * 2) + 33))
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#define SEC_INT_ITO (1ULL << 55)
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#define SEC_ISR 0x1010
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#define SEC_ICR 0x1018
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#define SEC_ID 0x1020
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#define SEC_EUASR 0x1028
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#define SEC_EUASR_RNGU(r) (((r) >> 0) & 0xF)
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#define SEC_EUASR_PKEU(r) (((r) >> 8) & 0xF)
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#define SEC_EUASR_KEU(r) (((r) >> 16) & 0xF)
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#define SEC_EUASR_CRCU(r) (((r) >> 20) & 0xF)
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#define SEC_EUASR_DEU(r) (((r) >> 32) & 0xF)
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#define SEC_EUASR_AESU(r) (((r) >> 40) & 0xF)
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#define SEC_EUASR_MDEU(r) (((r) >> 48) & 0xF)
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#define SEC_EUASR_AFEU(r) (((r) >> 56) & 0xF)
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#define SEC_MCR 0x1030
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#define SEC_MCR_SWR (1ULL << 32)
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/* SEC Channel registers */
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#define SEC_CHAN_CCR(n) (((n) * 0x100) + 0x1108)
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#define SEC_CHAN_CCR_CDIE (1ULL << 1)
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#define SEC_CHAN_CCR_NT (1ULL << 2)
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#define SEC_CHAN_CCR_AWSE (1ULL << 3)
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#define SEC_CHAN_CCR_CDWE (1ULL << 4)
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#define SEC_CHAN_CCR_BS (1ULL << 8)
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#define SEC_CHAN_CCR_WGN (1ULL << 13)
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#define SEC_CHAN_CCR_R (1ULL << 32)
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#define SEC_CHAN_CCR_CON (1ULL << 33)
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#define SEC_CHAN_CSR(n) (((n) * 0x100) + 0x1110)
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#define SEC_CHAN_CSR2_FFLVL_M 0x1FULL
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#define SEC_CHAN_CSR2_FFLVL_S 56
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#define SEC_CHAN_CSR2_GSTATE_M 0x0FULL
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#define SEC_CHAN_CSR2_GSTATE_S 48
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#define SEC_CHAN_CSR2_PSTATE_M 0x0FULL
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#define SEC_CHAN_CSR2_PSTATE_S 40
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#define SEC_CHAN_CSR2_MSTATE_M 0x3FULL
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#define SEC_CHAN_CSR2_MSTATE_S 32
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#define SEC_CHAN_CSR3_FFLVL_M 0x1FULL
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#define SEC_CHAN_CSR3_FFLVL_S 24
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#define SEC_CHAN_CSR3_MSTATE_M 0x1FFULL
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#define SEC_CHAN_CSR3_MSTATE_S 32
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#define SEC_CHAN_CSR3_PSTATE_M 0x7FULL
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#define SEC_CHAN_CSR3_PSTATE_S 48
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#define SEC_CHAN_CSR3_GSTATE_M 0x7FULL
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#define SEC_CHAN_CSR3_GSTATE_S 56
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#define SEC_CHAN_CDPR(n) (((n) * 0x100) + 0x1140)
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#define SEC_CHAN_FF(n) (((n) * 0x100) + 0x1148)
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/* SEC Execution Units numbers */
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#define SEC_EU_NONE 0x0
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#define SEC_EU_AFEU 0x1
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#define SEC_EU_DEU 0x2
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#define SEC_EU_MDEU_A 0x3
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#define SEC_EU_MDEU_B 0xB
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#define SEC_EU_RNGU 0x4
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#define SEC_EU_PKEU 0x5
|
||||
#define SEC_EU_AESU 0x6
|
||||
#define SEC_EU_KEU 0x7
|
||||
#define SEC_EU_CRCU 0x8
|
||||
|
||||
/* SEC descriptor types */
|
||||
#define SEC_DT_COMMON_NONSNOOP 0x02
|
||||
#define SEC_DT_HMAC_SNOOP 0x04
|
||||
|
||||
/* SEC AESU declarations and definitions */
|
||||
#define SEC_AESU_MODE_ED (1ULL << 0)
|
||||
#define SEC_AESU_MODE_CBC (1ULL << 1)
|
||||
|
||||
/* SEC DEU declarations and definitions */
|
||||
#define SEC_DEU_MODE_ED (1ULL << 0)
|
||||
#define SEC_DEU_MODE_TS (1ULL << 1)
|
||||
#define SEC_DEU_MODE_CBC (1ULL << 2)
|
||||
|
||||
/* SEC MDEU declarations and definitions */
|
||||
#define SEC_HMAC_HASH_LEN 12
|
||||
#define SEC_MDEU_MODE_SHA1 0x00 /* MDEU A */
|
||||
#define SEC_MDEU_MODE_SHA384 0x00 /* MDEU B */
|
||||
#define SEC_MDEU_MODE_SHA256 0x01
|
||||
#define SEC_MDEU_MODE_MD5 0x02 /* MDEU A */
|
||||
#define SEC_MDEU_MODE_SHA512 0x02 /* MDEU B */
|
||||
#define SEC_MDEU_MODE_SHA224 0x03
|
||||
#define SEC_MDEU_MODE_PD (1ULL << 2)
|
||||
#define SEC_MDEU_MODE_HMAC (1ULL << 3)
|
||||
#define SEC_MDEU_MODE_INIT (1ULL << 4)
|
||||
#define SEC_MDEU_MODE_SMAC (1ULL << 5)
|
||||
#define SEC_MDEU_MODE_CICV (1ULL << 6)
|
||||
#define SEC_MDEU_MODE_CONT (1ULL << 7)
|
||||
|
||||
#endif
|
||||
@ -53,6 +53,8 @@ device ata
|
||||
device atadisk
|
||||
device bpf
|
||||
device cfi
|
||||
device crypto
|
||||
device cryptodev
|
||||
device da
|
||||
device em
|
||||
device ether
|
||||
@ -68,6 +70,7 @@ device random
|
||||
#device rl
|
||||
device scbus
|
||||
device scc
|
||||
device sec
|
||||
device tsec
|
||||
device tun
|
||||
device uart
|
||||
|
||||
@ -42,5 +42,6 @@
|
||||
#define OCPBUS_DEVTYPE_PCIB 5
|
||||
#define OCPBUS_DEVTYPE_LBC 6
|
||||
#define OCPBUS_DEVTYPE_I2C 7
|
||||
#define OCPBUS_DEVTYPE_SEC 8
|
||||
|
||||
#endif /* _MACHINE_OCPBUS_H_ */
|
||||
|
||||
@ -216,6 +216,7 @@ ocpbus_attach(device_t dev)
|
||||
ocpbus_mk_child(dev, OCPBUS_DEVTYPE_TSEC, 3);
|
||||
ocpbus_mk_child(dev, OCPBUS_DEVTYPE_PIC, 0);
|
||||
ocpbus_mk_child(dev, OCPBUS_DEVTYPE_QUICC, 0);
|
||||
ocpbus_mk_child(dev, OCPBUS_DEVTYPE_SEC, 0);
|
||||
|
||||
/* Set up IRQ rman */
|
||||
start = 0;
|
||||
@ -348,6 +349,11 @@ const struct ocp_resource mpc8555_resources[] = {
|
||||
OCP85XX_I2C_SIZE},
|
||||
{OCPBUS_DEVTYPE_I2C, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(27), 1},
|
||||
|
||||
{OCPBUS_DEVTYPE_SEC, 0, SYS_RES_MEMORY, 0, OCP85XX_SEC_OFF,
|
||||
OCP85XX_SEC_SIZE},
|
||||
{OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(29), 1},
|
||||
{OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 1, PIC_IRQ_INT(42), 1},
|
||||
|
||||
{0}
|
||||
};
|
||||
|
||||
|
||||
@ -96,6 +96,8 @@
|
||||
#define OCP85XX_OPENPIC_SIZE 0x200B4
|
||||
#define OCP85XX_QUICC_OFF 0x80000
|
||||
#define OCP85XX_QUICC_SIZE 0x20000
|
||||
#define OCP85XX_SEC_OFF 0x30000
|
||||
#define OCP85XX_SEC_SIZE 0x10000
|
||||
|
||||
/*
|
||||
* PIC definitions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user