- Fix the length of efuse content.
- Replace the magic numbers with something more readable.
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8241ee3b2c
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0339d2cfcc
@ -1236,9 +1236,11 @@ urtwn_efuse_read(struct urtwn_softc *sc)
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static void
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urtwn_efuse_switch_power(struct urtwn_softc *sc)
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{
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uint8_t vol;
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uint32_t reg;
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if (sc->chip & URTWN_CHIP_88E)
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urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON);
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reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
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if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
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urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
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@ -1256,11 +1258,15 @@ urtwn_efuse_switch_power(struct urtwn_softc *sc)
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reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
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}
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/* Enable LDO 2.5V. */
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vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3);
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vol &= 0x0f;
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vol |= 0x30;
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urtwn_write_1(sc, R92C_EFUSE_TEST + 3, (vol | 0x80));
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if (!(sc->chip & URTWN_CHIP_88E)) {
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uint8_t vol;
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/* Enable LDO 2.5V. */
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vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3);
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vol &= 0x0f;
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vol |= 0x30;
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urtwn_write_1(sc, R92C_EFUSE_TEST + 3, (vol | 0x80));
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}
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}
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static int
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@ -1328,7 +1334,7 @@ urtwn_r88e_read_rom(struct urtwn_softc *sc)
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/* Read full ROM image. */
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memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom));
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while (addr < 1024) {
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while (addr < 512) {
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reg = urtwn_efuse_read_1(sc, addr);
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if (reg == 0xff)
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break;
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@ -1354,6 +1360,8 @@ urtwn_r88e_read_rom(struct urtwn_softc *sc)
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}
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}
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urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF);
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addr = 0x10;
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for (i = 0; i < 6; i++)
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sc->cck_tx_pwr[i] = sc->r88e_rom[addr++];
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@ -2193,14 +2201,12 @@ urtwn_r92c_power_on(struct urtwn_softc *sc)
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static int
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urtwn_r88e_power_on(struct urtwn_softc *sc)
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{
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uint8_t val;
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uint32_t reg;
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int ntries;
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/* Wait for power ready bit. */
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for (ntries = 0; ntries < 5000; ntries++) {
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val = urtwn_read_1(sc, 0x6) & 0x2;
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if (val == 0x2)
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if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
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break;
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urtwn_ms_delay(sc);
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}
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@ -2215,17 +2221,23 @@ urtwn_r88e_power_on(struct urtwn_softc *sc)
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urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
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R92C_SYS_FUNC_EN_BB_GLB_RST));
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urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80);
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urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
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urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
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/* Disable HWPDN. */
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urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80);
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urtwn_write_2(sc, R92C_APS_FSMCO,
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urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN);
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/* Disable WL suspend. */
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urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18);
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urtwn_write_2(sc, R92C_APS_FSMCO,
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urtwn_read_2(sc, R92C_APS_FSMCO) &
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~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE));
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urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1);
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urtwn_write_2(sc, R92C_APS_FSMCO,
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urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
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for (ntries = 0; ntries < 5000; ntries++) {
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if (!(urtwn_read_1(sc, 0x5) & 0x1))
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if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_ONMAC))
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break;
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urtwn_ms_delay(sc);
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}
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@ -2233,7 +2245,8 @@ urtwn_r88e_power_on(struct urtwn_softc *sc)
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return (ETIMEDOUT);
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/* Enable LDO normal mode. */
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urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10);
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urtwn_write_1(sc, R92C_LPLDO_CTRL,
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urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10);
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/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
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urtwn_write_2(sc, R92C_CR, 0);
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