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cxgbe(4): Check the RO bit properly before disabling relaxed ordering.

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Reported by:	Coverity (CID 1384286)
MFC after:	1 week
Sponsored by:	Chelsio Communications
This commit is contained in:
Navdeep Parhar 2018-08-21 21:32:51 +00:00
parent b14b007818
commit 036ff794dd
1 changed files with 1 additions and 1 deletions
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2
sys/dev/cxgbe/t4_main.c
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@ -861,7 +861,7 @@ t4_attach(device_t dev)
v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
if (pcie_relaxed_ordering == 0 &&
(v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
(v & PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) {
v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE;
pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
} else if (pcie_relaxed_ordering == 1 &&