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Update firmware interface structures and definitions adding support

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for new features and commands.

MFC after:		1 week
Sponsored by:		Mellanox Technologies
This commit is contained in:
Hans Petter Selasky 2017-01-20 10:47:32 +00:00
parent acdd2b1ca3
commit 0402eb6bcc
1 changed files with 168 additions and 35 deletions
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181
sys/dev/mlx5/mlx5_ifc.h
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@ -1,5 +1,5 @@
/*-
* Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
* Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -23,13 +23,8 @@
* SUCH DAMAGE.
*
* $FreeBSD$
*/
Autogenerated file.
Date: 2015-04-13 14:59
Source Document Name: Mellanox <Doc Name>
Source Document Version: 0.28
Generated by adb_to_c.py (EAT.ME Version: 1.0.70)
*/
#ifndef MLX5_IFC_H
#define MLX5_IFC_H
@ -56,6 +51,8 @@ enum {
MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT = 0x17,
MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e,
MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25,
MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22,
MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
@ -89,6 +86,8 @@ enum {
MLX5_CMD_OP_QUERY_ISSI = 0x10a,
MLX5_CMD_OP_SET_ISSI = 0x10b,
MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e,
MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f,
MLX5_CMD_OP_CREATE_MKEY = 0x200,
MLX5_CMD_OP_QUERY_MKEY = 0x201,
MLX5_CMD_OP_DESTROY_MKEY = 0x202,
@ -190,6 +189,12 @@ enum {
MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
MLX5_CMD_OP_SET_WOL_ROL = 0x830,
MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
MLX5_CMD_OP_CREATE_LAG = 0x840,
MLX5_CMD_OP_MODIFY_LAG = 0x841,
MLX5_CMD_OP_QUERY_LAG = 0x842,
MLX5_CMD_OP_DESTROY_LAG = 0x843,
MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
MLX5_CMD_OP_CREATE_TIR = 0x900,
MLX5_CMD_OP_MODIFY_TIR = 0x901,
MLX5_CMD_OP_DESTROY_TIR = 0x902,
@ -206,6 +211,8 @@ enum {
MLX5_CMD_OP_MODIFY_RMP = 0x90d,
MLX5_CMD_OP_DESTROY_RMP = 0x90e,
MLX5_CMD_OP_QUERY_RMP = 0x90f,
MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911,
MLX5_CMD_OP_CREATE_TIS = 0x912,
MLX5_CMD_OP_MODIFY_TIS = 0x913,
MLX5_CMD_OP_DESTROY_TIS = 0x914,
@ -226,7 +233,10 @@ enum {
MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b
MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
};
enum {
@ -271,7 +281,11 @@ struct mlx5_ifc_flow_table_fields_supported_bits {
u8 outer_gre_protocol[0x1];
u8 outer_gre_key[0x1];
u8 outer_vxlan_vni[0x1];
u8 reserved_2[0x5];
u8 outer_geneve_vni[0x1];
u8 outer_geneve_oam[0x1];
u8 outer_geneve_protocol_type[0x1];
u8 outer_geneve_opt_len[0x1];
u8 reserved_2[0x1];
u8 source_eswitch_port[0x1];
u8 inner_dmac[0x1];
@ -299,10 +313,12 @@ struct mlx5_ifc_flow_table_fields_supported_bits {
u8 inner_tcp_flags[0x1];
u8 reserved_5[0x9];
u8 reserved_6[0x1f];
u8 reserved_6[0x1a];
u8 bth_dst_qp[0x1];
u8 reserved_7[0x4];
u8 source_sqn[0x1];
u8 reserved_7[0x20];
u8 reserved_8[0x20];
};
struct mlx5_ifc_eth_discard_cntrs_grp_bits {
@ -356,7 +372,11 @@ struct mlx5_ifc_eth_discard_cntrs_grp_bits {
u8 egress_stp_filter_low[0x20];
u8 reserved_at_340[0x480];
u8 egress_hoq_stall_high[0x20];
u8 egress_hoq_stall_low[0x20];
u8 reserved_at_340[0x440];
};
struct mlx5_ifc_flow_table_prop_layout_bits {
u8 ft_support[0x1];
@ -411,6 +431,7 @@ enum {
MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0,
MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1,
MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2,
MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3,
};
struct mlx5_ifc_dest_format_struct_bits {
@ -490,9 +511,14 @@ struct mlx5_ifc_fte_match_set_misc_bits {
u8 reserved_6[0xc];
u8 inner_ipv6_flow_label[0x14];
u8 reserved7[0x10];
u8 reserved_7[0xa];
u8 geneve_opt_len[0x6];
u8 geneve_protocol_type[0x10];
u8 reserved8[0xc0];
u8 reserved_8[0x8];
u8 bth_dst_qp[0x18];
u8 reserved_9[0xa0];
};
struct mlx5_ifc_cmd_pas_bits {
@ -698,7 +724,8 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
u8 lro_psh_flag[0x1];
u8 lro_time_stamp[0x1];
u8 lro_max_msg_sz_mode[0x2];
u8 reserved_0[0x2];
u8 wqe_vlan_insert[0x1];
u8 self_lb_en_modifiable[0x1];
u8 self_lb_mc[0x1];
u8 self_lb_uc[0x1];
u8 max_lso_cap[0x5];
@ -715,7 +742,8 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
u8 swp[0x1];
u8 swp_csum[0x1];
u8 swp_lso[0x1];
u8 reserved_2[0x1c];
u8 reserved_2[0x1b];
u8 max_geneve_opt_len[0x1];
u8 tunnel_stateless_geneve_rx[0x1];
u8 reserved_3[0x10];
@ -910,7 +938,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 vport_counters[0x1];
u8 retransmission_q_counters[0x1];
u8 debug[0x1];
u8 reserved_16[0x2];
u8 modify_rq_counters_set_id[0x1];
u8 rq_delay_drop[0x1];
u8 max_qp_cnt[0xa];
u8 pkey_table_size[0x10];
@ -980,7 +1009,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 cq_oi[0x1];
u8 cq_resize[0x1];
u8 cq_moderation[0x1];
u8 reserved_31[0x3];
u8 cq_period_mode_modify[0x1];
u8 cq_invalidate[0x1];
u8 reserved_at_225[0x1];
u8 cq_eq_remap[0x1];
u8 pg[0x1];
u8 block_lb_mc[0x1];
@ -1068,7 +1099,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 log_max_wq_sz[0x5];
u8 nic_vport_change_event[0x1];
u8 reserved_59[0xa];
u8 disable_local_lb[0x1];
u8 reserved_59[0x9];
u8 log_max_vlan_list[0x5];
u8 reserved_60[0x3];
u8 log_max_current_mc_list[0x5];
@ -1312,6 +1344,8 @@ enum {
MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10,
MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20,
};
struct mlx5_ifc_modify_field_select_bits {
@ -2239,9 +2273,15 @@ enum {
MLX5_RQC_STATE_ERR = 0x3,
};
enum {
MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0,
MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1,
};
struct mlx5_ifc_rqc_bits {
u8 rlky[0x1];
u8 reserved_0[0x2];
u8 rlkey[0x1];
u8 delay_drop_en[0x1];
u8 scatter_fcs[0x1];
u8 vlan_strip_disable[0x1];
u8 mem_rq_type[0x4];
u8 state[0x4];
@ -2293,7 +2333,9 @@ enum {
struct mlx5_ifc_nic_vport_context_bits {
u8 reserved_0[0x5];
u8 min_wqe_inline_mode[0x3];
u8 reserved_1[0x17];
u8 reserved_1[0x15];
u8 disable_mc_local_lb[0x1];
u8 disable_uc_local_lb[0x1];
u8 roce_en[0x1];
u8 arm_change_event[0x1];
@ -3075,6 +3117,50 @@ struct mlx5_ifc_teardown_hca_in_bits {
u8 reserved_3[0x20];
};
struct mlx5_ifc_set_delay_drop_params_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_set_delay_drop_params_in_bits {
u8 opcode[0x10];
u8 reserved_at_10[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 reserved_at_40[0x20];
u8 reserved_at_60[0x10];
u8 delay_drop_timeout[0x10];
};
struct mlx5_ifc_query_delay_drop_params_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x20];
u8 reserved_at_60[0x10];
u8 delay_drop_timeout[0x10];
};
struct mlx5_ifc_query_delay_drop_params_in_bits {
u8 opcode[0x10];
u8 reserved_at_10[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_suspend_qp_out_bits {
u8 status[0x8];
u8 reserved_0[0x18];
@ -4100,7 +4186,15 @@ struct mlx5_ifc_query_q_counter_out_bits {
u8 local_ack_timeout_err[0x20];
u8 reserved_13[0x4e0];
u8 reserved_13[0x20];
u8 resp_rnr_nak[0x20];
u8 reserved_14[0x20];
u8 req_rnr_retries_exceeded[0x20];
u8 reserved_15[0x460];
};
struct mlx5_ifc_query_q_counter_in_bits {
@ -5204,7 +5298,9 @@ struct mlx5_ifc_modify_nic_vport_context_out_bits {
};
struct mlx5_ifc_modify_nic_vport_field_select_bits {
u8 reserved_0[0x16];
u8 reserved_0[0x14];
u8 disable_uc_local_lb[0x1];
u8 disable_mc_local_lb[0x1];
u8 node_guid[0x1];
u8 port_guid[0x1];
u8 min_wqe_inline_mode[0x1];
@ -7958,6 +8054,42 @@ struct mlx5_ifc_phys_layer_cntrs_bits {
u8 reserved_0[0x180];
};
struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
u8 time_since_last_clear_high[0x20];
u8 time_since_last_clear_low[0x20];
u8 phy_received_bits_high[0x20];
u8 phy_received_bits_low[0x20];
u8 phy_symbol_errors_high[0x20];
u8 phy_symbol_errors_low[0x20];
u8 phy_corrected_bits_high[0x20];
u8 phy_corrected_bits_low[0x20];
u8 phy_corrected_bits_lane0_high[0x20];
u8 phy_corrected_bits_lane0_low[0x20];
u8 phy_corrected_bits_lane1_high[0x20];
u8 phy_corrected_bits_lane1_low[0x20];
u8 phy_corrected_bits_lane2_high[0x20];
u8 phy_corrected_bits_lane2_low[0x20];
u8 phy_corrected_bits_lane3_high[0x20];
u8 phy_corrected_bits_lane3_low[0x20];
u8 reserved_at_200[0x5c0];
};
struct mlx5_ifc_infiniband_port_cntrs_bits {
u8 symbol_error_counter[0x10];
u8 link_error_recovery_counter[0x8];
@ -9187,6 +9319,7 @@ union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
u8 reserved_0[0x7c0];
};