d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Rename some CPU_MIPSxxx options and add new CPU_MIPSxxx options

Browse Source 
This revision does the following renames:
CPU_MIPS24KC -> CPU_MIPS24K
CPU_MIPS74KC -> CPU_MIPS74K
CPU_MIPS1004KC -> CPU_MIPS1004K

It also adds the following new CPU_MIPSxxx options:
CPU_MIPS24KE, CPU_MIPS34K, CPU_MIPS1074K, CPU_INTERAPTIV, CPU_PROAPTIV

CPU_MIPSxxxxKC is limiting and possibly misleading as it implies the
MIPSxxxxK CPU has no FPU.
It would be better if the CPUs are named after their standard functionalities
only and the presence or absence of FPU can then be controlled via the
CPU_HAVEFPU option.

I will send out another dependent revision that moves MIPS 32 r2 and r3
CPUs to use the EHB instruction for clearing hazards instead of NOP/SSNOP.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	imp
Differential Revision:	https://reviews.freebsd.org/D5077
This commit is contained in:
Adrian Chadd 2016-02-02 07:47:38 +00:00
parent f4c1f0b9eb
commit 04b5e02371
6 changed files with 14 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
sys/conf/options.mips
View File

@ -29,9 +29,13 @@
# $FreeBSD$
CPU_MIPS4KC opt_global.h
CPU_MIPS24KC opt_global.h
CPU_MIPS74KC opt_global.h
CPU_MIPS1004KC opt_global.h
CPU_MIPS24K opt_global.h
CPU_MIPS34K opt_global.h
CPU_MIPS74K opt_global.h
CPU_MIPS1004K opt_global.h
CPU_MIPS1074K opt_global.h
CPU_INTERAPTIV opt_global.h
CPU_PROAPTIV opt_global.h
CPU_MIPS32 opt_global.h
CPU_MIPS64 opt_global.h
CPU_SENTRY5 opt_global.h

2
sys/mips/conf/AR934X_BASE
View File

@ -12,7 +12,7 @@
machine mips mips
ident AR934X_BASE
cpu CPU_MIPS74KC
cpu CPU_MIPS74K
makeoptions KERNLOADADDR=0x80050000
options HZ=1000

2
sys/mips/conf/QCA955X_BASE
View File

@ -13,7 +13,7 @@
machine mips mips
ident QCA955X_BASE
cpu CPU_MIPS74KC
cpu CPU_MIPS74K
makeoptions KERNLOADADDR=0x80050000
options HZ=1000

2
sys/mips/include/asm.h
View File

@ -700,7 +700,7 @@ _C_LABEL(x):
#elif defined(CPU_RMI)
#define HAZARD_DELAY
#define ITLBNOPFIX
#elif defined(CPU_MIPS74KC)
#elif defined(CPU_MIPS74K)
#define HAZARD_DELAY sll $0,$0,3
#define ITLBNOPFIX sll $0,$0,3
#else

2
sys/mips/include/cpufunc.h
View File

@ -248,7 +248,7 @@ MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5);
#if defined(CPU_NLM) || defined(BERI_LARGE_TLB)
MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
#endif
#if defined(CPU_NLM) || defined(CPU_MIPS1004KC)
#if defined(CPU_NLM) || defined(CPU_MIPS1004K)
MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
#endif
MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);

6
sys/mips/include/cpuregs.h
View File

@ -149,12 +149,12 @@
#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
#endif
#if defined(CPU_MIPS74KC)
#if defined(CPU_MIPS74K)
#define MIPS_CCA_UNCACHED 0x02
#define MIPS_CCA_CACHED 0x03
#endif
#if defined(CPU_MIPS1004KC)
#if defined(CPU_MIPS1004K)
#define MIPS_CCA_UNCACHED 0x02
#define MIPS_CCA_CACHED 0x05
#endif
@ -214,7 +214,7 @@
#define COP0_SYNC .word 0xc0 /* ehb */
#elif defined(CPU_SB1)
#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
#elif defined(CPU_MIPS74KC) || defined(CPU_MIPS1004KC)
#elif defined(CPU_MIPS74K) || defined(CPU_MIPS1004K)
#define COP0_SYNC .word 0xc0 /* ehb */
#else
/*