pci: clean up empty lines in .c and .h files
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3cfc80b28a
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04e8183fd1
@ -51,7 +51,6 @@ pci_hostb_probe(device_t dev)
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id = pci_get_devid(dev);
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switch (id) {
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/* VIA VT82C596 Power Management Function */
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case 0x30501106:
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return (ENXIO);
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@ -280,7 +279,6 @@ static device_method_t pci_hostb_methods[] = {
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DEVMETHOD(pci_find_next_extcap, pci_hostb_find_next_extcap),
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DEVMETHOD(pci_find_htcap, pci_hostb_find_htcap),
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DEVMETHOD(pci_find_next_htcap, pci_hostb_find_next_htcap),
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{ 0, 0 }
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};
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@ -145,7 +145,7 @@ isab_pci_probe(device_t dev)
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pci_get_subclass(dev));
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matched = 1;
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break;
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default:
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break;
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}
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@ -317,7 +317,6 @@ static const struct pci_quirk pci_quirks[] = {
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* expected place.
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*/
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{ 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 },
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{ 0 }
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};
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@ -768,7 +767,6 @@ pci_ea_fill_info(device_t pcib, pcicfgregs *cfg)
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ptr += 4;
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for (a = 0; a < num_ent; a++) {
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eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO);
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eae->eae_cfg_offset = cfg->ea.ea_location + ptr;
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@ -2363,7 +2361,6 @@ pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
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* data registers and apply the results.
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*/
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if (cfg->msi.msi_alloc > 0) {
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/* If we don't have any active handlers, nothing to do. */
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if (cfg->msi.msi_handlers == 0)
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return (0);
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@ -2593,7 +2590,6 @@ pci_alloc_msi_method(device_t dev, device_t child, int *count)
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device_printf(child, "using IRQs %d", irqs[0]);
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run = 0;
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for (i = 1; i < actual; i++) {
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/* Still in a run? */
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if (irqs[i] == irqs[i - 1] + 1) {
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run = 1;
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@ -3862,7 +3858,6 @@ pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov)
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return;
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STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
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/*
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* TODO: Ignore EA-BAR if is not enabled.
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* Currently the EA implementation supports
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@ -5261,7 +5256,6 @@ DB_SHOW_COMMAND(pciregs, db_pci_dump)
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dinfo = STAILQ_FIRST(devlist_head);
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(dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
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dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
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/* Populate pd_name and pd_unit */
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name = NULL;
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if (dinfo->cfg.dev)
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@ -31,7 +31,6 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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@ -82,13 +81,10 @@ __FBSDID("$FreeBSD$");
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#define PCI_FUNC_MASK 0x07
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#define PCI_REG_MASK 0xFFF
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#define IATU_CFG_BUS(bus) ((uint64_t)((bus) & 0xff) << 24)
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#define IATU_CFG_SLOT(slot) ((uint64_t)((slot) & 0x1f) << 19)
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#define IATU_CFG_FUNC(func) ((uint64_t)((func) & 0x07) << 16)
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static uint32_t
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pci_dw_dbi_read(device_t dev, u_int reg, int width)
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{
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@ -134,7 +130,6 @@ pci_dw_dbi_write(device_t dev, u_int reg, uint32_t val, int width)
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}
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}
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static void
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pci_dw_dbi_protect(struct pci_dw_softc *sc, bool protect)
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{
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@ -243,7 +238,6 @@ pci_dw_setup_hw(struct pci_dw_softc *sc)
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}
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/* XXX Should we handle also prefetch memory? */
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/* Adjust number of lanes */
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reg = DBI_RD4(sc, DW_PORT_LINK_CTRL);
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reg &= ~PORT_LINK_CAPABLE(~0);
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@ -274,7 +268,6 @@ pci_dw_setup_hw(struct pci_dw_softc *sc)
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}
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DBI_WR4(sc, DW_PORT_LINK_CTRL, reg);
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/* And link width */
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reg = DBI_RD4(sc, DW_GEN2_CTRL);
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reg &= ~GEN2_CTRL_NUM_OF_LANES(~0);
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@ -304,7 +297,6 @@ pci_dw_setup_hw(struct pci_dw_softc *sc)
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reg |= DIRECT_SPEED_CHANGE;
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DBI_WR4(sc, DW_GEN2_CTRL, reg);
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return (0);
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}
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@ -353,8 +345,6 @@ pci_dw_decode_ranges(struct pci_dw_softc *sc, struct ofw_pci_range *ranges,
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return (0);
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}
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/*-----------------------------------------------------------------------------
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*
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* P C I B I N T E R F A C E
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@ -438,7 +428,6 @@ pci_dw_write_config(device_t dev, u_int bus, u_int slot,
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res = sc->cfg_res;
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}
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switch (bytes) {
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case 1:
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bus_write_1(res, reg, val);
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@ -658,7 +647,6 @@ pci_dw_init(device_t dev)
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}
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static device_method_t pci_dw_methods[] = {
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/* Bus interface */
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DEVMETHOD(bus_get_dma_tag, pci_dw_get_dma_tag),
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@ -34,7 +34,6 @@
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#include "pci_dw_if.h"
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/* DesignWare CIe configuration registers */
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#define DW_PORT_LINK_CTRL 0x710
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#define PORT_LINK_CAPABLE(n) (((n) & 0x3F) << 16)
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@ -45,7 +44,6 @@
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#define PORT_LINK_CAPABLE_16 0x1F
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#define PORT_LINK_CAPABLE_32 0x3F
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#define DW_GEN2_CTRL 0x80C
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#define DIRECT_SPEED_CHANGE (1 << 17)
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#define GEN2_CTRL_NUM_OF_LANES(n) (((n) & 0x3F) << 8)
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@ -62,7 +60,6 @@
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#define DW_MSI_INTR0_MASK 0x82C
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#define DW_MSI_INTR0_STATUS 0x830
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#define DW_MISC_CONTROL_1 0x8BC
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#define DBI_RO_WR_EN (1 << 0)
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@ -83,7 +80,6 @@
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#define DW_IATU_LWR_TARGET_ADDR 0x918
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#define DW_IATU_UPPER_TARGET_ADDR 0x91C
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struct pci_dw_softc {
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struct ofw_pci_softc ofw_pci; /* Must be first */
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@ -116,7 +112,6 @@ struct pci_dw_softc {
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DECLARE_CLASS(pci_dw_driver);
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static inline void
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pci_dw_dbi_wr4(device_t dev, u_int reg, uint32_t val)
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{
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@ -31,7 +31,6 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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@ -145,7 +144,6 @@ pci_mv_init(struct pci_mv_softc *sc)
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{
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uint32_t reg;
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/* Set device configuration to RC */
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reg = pci_dw_dbi_rd4(sc->dev, MV_GLOBAL_CONTROL_REG);
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reg &= ~0x000000F0;
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@ -232,7 +230,7 @@ pci_mv_attach(device_t dev)
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node = ofw_bus_get_node(dev);
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sc->dev = dev;
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sc->node = node;
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rid = 0;
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sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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@ -267,7 +265,6 @@ pci_mv_attach(device_t dev)
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goto out;
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}
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rv = clk_enable(sc->clk_core);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot enable 'core' clock\n");
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@ -261,7 +261,6 @@ generic_pcie_read_ivar(device_t dev, device_t child, int index,
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if (index == PCIB_IVAR_BUS) {
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*result = sc->bus_start;
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return (0);
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}
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if (index == PCIB_IVAR_DOMAIN) {
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@ -506,7 +506,6 @@ generic_pcie_ofw_bus_attach(device_t dev)
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get_addr_size_cells(parent, &addr_cells, &size_cells);
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/* Iterate through all bus subordinates */
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for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
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/* Allocate and populate devinfo. */
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di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);
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if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) {
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@ -83,7 +83,6 @@ static u_long pci_iov_max_config = 1024 * 1024;
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SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN,
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&pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration.");
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#define IOV_READ(d, r, w) \
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pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w)
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@ -128,7 +127,7 @@ pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema,
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dinfo = device_get_ivars(dev);
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pcib = device_get_parent(bus);
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schema = NULL;
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error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos);
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if (error != 0)
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@ -171,7 +170,7 @@ pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema,
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error = ENOMEM;
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goto cleanup;
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}
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dinfo->cfg.iov = iov;
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iov->iov_cdev->si_drv1 = dinfo;
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mtx_unlock(&Giant);
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@ -1061,4 +1060,3 @@ pci_vf_release_mem_resource(device_t dev, device_t child, int rid,
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return (rman_release_resource(r));
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}
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@ -43,7 +43,7 @@ struct pcicfg_iov {
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struct pci_iov_bar iov_bar[PCIR_MAX_BAR_0 + 1];
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struct rman rman;
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char rman_name[64];
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int iov_pos;
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int iov_num_vfs;
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uint32_t iov_flags;
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@ -59,4 +59,3 @@ void pci_iov_cfg_restore(device_t dev, struct pci_devinfo *dinfo);
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void pci_iov_cfg_save(device_t dev, struct pci_devinfo *dinfo);
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#endif
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@ -1445,7 +1445,7 @@ pcib_detach_hotplug(struct pcib_softc *sc)
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}
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pcib_pcie_hotplug_update(sc, val, mask, false);
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error = pcib_release_pcie_irq(sc);
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if (error)
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return (error);
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@ -2533,7 +2533,6 @@ pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
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}
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}
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static void
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pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
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{
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@ -963,7 +963,6 @@ pci_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag, struct thread *t
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}
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}
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/* Giant because newbus is Giant locked revisit with newbus locking */
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mtx_lock(&Giant);
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@ -1086,7 +1085,6 @@ pci_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag, struct thread *t
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dinfo = STAILQ_FIRST(devlist_head);
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dinfo != NULL;
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dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
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if (i < cio->offset)
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continue;
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@ -79,4 +79,3 @@ pcib_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot,
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*slot = PCI_RID2SLOT(rid);
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*func = PCI_RID2FUNC(rid);
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}
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@ -160,7 +160,6 @@ vga_pci_reset(device_t dev)
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pci_set_powerstate(dev, ps);
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}
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void *
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vga_pci_map_bios(device_t dev, size_t *size)
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{
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@ -779,7 +778,6 @@ static device_method_t vga_pci_methods[] = {
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DEVMETHOD(pci_release_msi, vga_pci_release_msi),
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DEVMETHOD(pci_msi_count, vga_pci_msi_count),
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DEVMETHOD(pci_msix_count, vga_pci_msix_count),
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{ 0, 0 }
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};
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