cxgbe(4): T4_SET_SCHED_CLASS and T4_SET_SCHED_QUEUE ioctls to program
scheduling classes in the chip and to bind tx queue(s) to a scheduling class respectively. These can be used for various kinds of tx traffic throttling (to force selected tx queues to drain at a fixed Kbps rate, or a % of the port's total bandwidth, or at a fixed pps rate, etc.). Obtained from: Chelsio
This commit is contained in:
Navdeep Parhar
parent
9151c81ccb
commit
05337b80ee
@ -587,4 +587,8 @@ int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type cty
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int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
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int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
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int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
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int t4_sched_config(struct adapter *adapter, int type, int minmaxen);
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int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
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int rateunit, int ratemode, int channel, int cl,
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int minrate, int maxrate, int weight, int pktsize);
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#endif /* __CHELSIO_COMMON_H */
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@ -5664,3 +5664,50 @@ int __devinit t4_port_init(struct port_info *p, int mbox, int pf, int vf)
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return 0;
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}
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int t4_sched_config(struct adapter *adapter, int type, int minmaxen)
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{
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struct fw_sched_cmd cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
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F_FW_CMD_REQUEST |
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F_FW_CMD_WRITE);
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cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
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cmd.u.config.sc = FW_SCHED_SC_CONFIG;
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cmd.u.config.type = type;
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cmd.u.config.minmaxen = minmaxen;
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return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
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NULL, 1);
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}
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int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
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int rateunit, int ratemode, int channel, int cl,
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int minrate, int maxrate, int weight, int pktsize)
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{
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struct fw_sched_cmd cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
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F_FW_CMD_REQUEST |
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F_FW_CMD_WRITE);
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cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
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cmd.u.params.sc = FW_SCHED_SC_PARAMS;
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cmd.u.params.type = type;
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cmd.u.params.level = level;
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cmd.u.params.mode = mode;
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cmd.u.params.ch = channel;
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cmd.u.params.cl = cl;
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cmd.u.params.unit = rateunit;
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cmd.u.params.rate = ratemode;
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cmd.u.params.min = cpu_to_be32(minrate);
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cmd.u.params.max = cpu_to_be32(maxrate);
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cmd.u.params.weight = cpu_to_be16(weight);
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cmd.u.params.pktsize = cpu_to_be16(pktsize);
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return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
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NULL, 1);
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}
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@ -208,6 +208,74 @@ struct t4_filter {
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struct t4_filter_specification fs;
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};
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/*
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* Support for "sched-class" command to allow a TX Scheduling Class to be
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* programmed with various parameters.
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*/
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struct t4_sched_params {
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int8_t subcmd; /* sub-command */
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int8_t type; /* packet or flow */
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union {
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struct { /* sub-command SCHED_CLASS_CONFIG */
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int8_t minmax; /* minmax enable */
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} config;
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struct { /* sub-command SCHED_CLASS_PARAMS */
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int8_t level; /* scheduler hierarchy level */
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int8_t mode; /* per-class or per-flow */
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int8_t rateunit; /* bit or packet rate */
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int8_t ratemode; /* %port relative or kbps
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absolute */
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int8_t channel; /* scheduler channel [0..N] */
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int8_t cl; /* scheduler class [0..N] */
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int32_t minrate; /* minimum rate */
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int32_t maxrate; /* maximum rate */
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int16_t weight; /* percent weight */
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int16_t pktsize; /* average packet size */
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} params;
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uint8_t reserved[6 + 8 * 8];
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} u;
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};
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enum {
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SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */
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SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */
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};
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enum {
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SCHED_CLASS_TYPE_PACKET,
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};
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enum {
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SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */
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SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */
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SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */
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};
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enum {
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SCHED_CLASS_MODE_CLASS, /* per-class scheduling */
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SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */
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};
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enum {
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SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */
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SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */
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};
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enum {
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SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */
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SCHED_CLASS_RATEMODE_ABS, /* Kb/s */
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};
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/*
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* Support for "sched_queue" command to allow one or more NIC TX Queues to be
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* bound to a TX Scheduling Class.
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*/
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struct t4_sched_queue {
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uint8_t port;
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int8_t queue; /* queue index; -1 => all queues */
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int8_t cl; /* class index; -1 => unbind */
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};
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#define T4_SGE_CONTEXT_SIZE 24
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enum {
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SGE_CONTEXT_EGRESS,
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@ -261,6 +329,10 @@ struct t4_tracer {
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#define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range)
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#define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data)
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#define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t)
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#define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \
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struct t4_sched_params)
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#define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \
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struct t4_sched_queue)
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#define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer)
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#define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer)
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#endif
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@ -425,6 +425,8 @@ static int get_sge_context(struct adapter *, struct t4_sge_context *);
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static int load_fw(struct adapter *, struct t4_data *);
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static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
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static int read_i2c(struct adapter *, struct t4_i2c_data *);
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static int set_sched_class(struct adapter *, struct t4_sched_params *);
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static int set_sched_queue(struct adapter *, struct t4_sched_queue *);
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#ifdef TCP_OFFLOAD
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static int toe_capability(struct port_info *, int);
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#endif
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@ -7295,6 +7297,228 @@ read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
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return (rc);
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}
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static int
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in_range(int val, int lo, int hi)
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{
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return (val < 0 || (val <= hi && val >= lo));
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}
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static int
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set_sched_class(struct adapter *sc, struct t4_sched_params *p)
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{
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int fw_subcmd, fw_type, rc;
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rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsc");
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if (rc)
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return (rc);
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if (!(sc->flags & FULL_INIT_DONE)) {
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rc = EAGAIN;
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goto done;
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}
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/*
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* Translate the cxgbetool parameters into T4 firmware parameters. (The
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* sub-command and type are in common locations.)
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*/
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if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
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fw_subcmd = FW_SCHED_SC_CONFIG;
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else if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
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fw_subcmd = FW_SCHED_SC_PARAMS;
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else {
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rc = EINVAL;
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goto done;
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}
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if (p->type == SCHED_CLASS_TYPE_PACKET)
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fw_type = FW_SCHED_TYPE_PKTSCHED;
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else {
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rc = EINVAL;
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goto done;
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}
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if (fw_subcmd == FW_SCHED_SC_CONFIG) {
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/* Vet our parameters ..*/
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if (p->u.config.minmax < 0) {
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rc = EINVAL;
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goto done;
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}
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/* And pass the request to the firmware ...*/
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rc = -t4_sched_config(sc, fw_type, p->u.config.minmax);
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goto done;
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}
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if (fw_subcmd == FW_SCHED_SC_PARAMS) {
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int fw_level;
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int fw_mode;
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int fw_rateunit;
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int fw_ratemode;
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if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL)
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fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
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else if (p->u.params.level == SCHED_CLASS_LEVEL_CL_WRR)
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fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
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else if (p->u.params.level == SCHED_CLASS_LEVEL_CH_RL)
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fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
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else {
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rc = EINVAL;
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goto done;
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}
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if (p->u.params.mode == SCHED_CLASS_MODE_CLASS)
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fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
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else if (p->u.params.mode == SCHED_CLASS_MODE_FLOW)
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fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
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else {
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rc = EINVAL;
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goto done;
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}
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if (p->u.params.rateunit == SCHED_CLASS_RATEUNIT_BITS)
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fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
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else if (p->u.params.rateunit == SCHED_CLASS_RATEUNIT_PKTS)
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fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
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else {
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rc = EINVAL;
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goto done;
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}
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if (p->u.params.ratemode == SCHED_CLASS_RATEMODE_REL)
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fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
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else if (p->u.params.ratemode == SCHED_CLASS_RATEMODE_ABS)
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fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
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else {
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rc = EINVAL;
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goto done;
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}
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/* Vet our parameters ... */
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if (!in_range(p->u.params.channel, 0, 3) ||
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!in_range(p->u.params.cl, 0, is_t4(sc) ? 15 : 16) ||
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!in_range(p->u.params.minrate, 0, 10000000) ||
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!in_range(p->u.params.maxrate, 0, 10000000) ||
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!in_range(p->u.params.weight, 0, 100)) {
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rc = ERANGE;
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goto done;
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}
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/*
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* Translate any unset parameters into the firmware's
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* nomenclature and/or fail the call if the parameters
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* are required ...
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*/
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if (p->u.params.rateunit < 0 || p->u.params.ratemode < 0 ||
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p->u.params.channel < 0 || p->u.params.cl < 0) {
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rc = EINVAL;
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goto done;
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}
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if (p->u.params.minrate < 0)
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p->u.params.minrate = 0;
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if (p->u.params.maxrate < 0) {
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if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL ||
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p->u.params.level == SCHED_CLASS_LEVEL_CH_RL) {
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rc = EINVAL;
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goto done;
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} else
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p->u.params.maxrate = 0;
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}
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if (p->u.params.weight < 0) {
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if (p->u.params.level == SCHED_CLASS_LEVEL_CL_WRR) {
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rc = EINVAL;
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goto done;
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} else
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p->u.params.weight = 0;
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}
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if (p->u.params.pktsize < 0) {
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if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL ||
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p->u.params.level == SCHED_CLASS_LEVEL_CH_RL) {
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rc = EINVAL;
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goto done;
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} else
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p->u.params.pktsize = 0;
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}
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/* See what the firmware thinks of the request ... */
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rc = -t4_sched_params(sc, fw_type, fw_level, fw_mode,
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fw_rateunit, fw_ratemode, p->u.params.channel,
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p->u.params.cl, p->u.params.minrate, p->u.params.maxrate,
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p->u.params.weight, p->u.params.pktsize);
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goto done;
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}
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rc = EINVAL;
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done:
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end_synchronized_op(sc, 0);
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return (rc);
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}
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static int
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set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
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{
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struct port_info *pi = NULL;
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struct sge_txq *txq;
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uint32_t fw_mnem, fw_queue, fw_class;
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int i, rc;
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rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
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if (rc)
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return (rc);
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if (!(sc->flags & FULL_INIT_DONE)) {
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rc = EAGAIN;
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goto done;
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}
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if (p->port >= sc->params.nports) {
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rc = EINVAL;
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goto done;
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}
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pi = sc->port[p->port];
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if (!in_range(p->queue, 0, pi->ntxq - 1) || !in_range(p->cl, 0, 7)) {
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rc = EINVAL;
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goto done;
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}
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/*
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* Create a template for the FW_PARAMS_CMD mnemonic and value (TX
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* Scheduling Class in this case).
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*/
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fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
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V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
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fw_class = p->cl < 0 ? 0xffffffff : p->cl;
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/*
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* If op.queue is non-negative, then we're only changing the scheduling
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* on a single specified TX queue.
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*/
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if (p->queue >= 0) {
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txq = &sc->sge.txq[pi->first_txq + p->queue];
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fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
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rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
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&fw_class);
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goto done;
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}
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/*
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* Change the scheduling on all the TX queues for the
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* interface.
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*/
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for_each_txq(pi, i, txq) {
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fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
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rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
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&fw_class);
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if (rc)
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goto done;
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}
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rc = 0;
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done:
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end_synchronized_op(sc, 0);
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return (rc);
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}
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int
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t4_os_find_pci_capability(struct adapter *sc, int cap)
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{
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@ -7538,6 +7762,12 @@ t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
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}
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break;
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}
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case CHELSIO_T4_SCHED_CLASS:
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rc = set_sched_class(sc, (struct t4_sched_params *)data);
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break;
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case CHELSIO_T4_SCHED_QUEUE:
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rc = set_sched_queue(sc, (struct t4_sched_queue *)data);
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break;
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case CHELSIO_T4_GET_TRACER:
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rc = t4_get_tracer(sc, (struct t4_tracer *)data);
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break;
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