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powerpc: Stop pretending we run on e500v1 cores

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Unconditional writing to MAS7, which doesn't exist on the e500v1 core, in a
TLB miss handler has been in the code for several years now.  Since this has
gone unnoticed for so long, it's easily concluded that e500v1 is not in use
with FreeBSD.  Simplify the code path a bit, by unconditionally zeroing MAS7
instead of calling a subroutine to do it.
This commit is contained in:
Justin Hibbits 2019-04-30 03:45:46 +00:00
parent 7122ab6ed3
commit 0af5d6f7d9
2 changed files with 9 additions and 17 deletions
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23
sys/powerpc/booke/locore.S
View File

@ -250,7 +250,8 @@ __start:
ori %r4, %r4, (MAS3_SX | MAS3_SW | MAS3_SR)@l
mtspr SPR_MAS3, %r4 /* Set RPN and protection */
isync
bl zero_mas7
li %r4, 0
mtspr SPR_MAS7, %r4
bl zero_mas8
isync
tlbwe
@ -505,7 +506,8 @@ bp_kernload:
ori %r3, %r3, (MAS3_SX | MAS3_SW | MAS3_SR)@l
mtspr SPR_MAS3, %r3
isync
bl zero_mas7
li %r4, 0
mtspr SPR_MAS7, %r4
bl zero_mas8
isync
tlbwe
@ -696,7 +698,8 @@ tlb1_temp_mapping_as1:
mtspr SPR_MAS1, %r5
isync
mflr %r3
bl zero_mas7
li %r4, 0
mtspr SPR_MAS7, %r4
bl zero_mas8
mtlr %r3
isync
@ -736,20 +739,8 @@ tlb1_inval_all_but_current:
blr
/*
* MAS7 and MAS8 conditional zeroing.
* MAS8 conditional zeroing.
*/
.globl zero_mas7
zero_mas7:
mfpvr %r20
rlwinm %r20, %r20, 16, 16, 31
cmpli 0, 0, %r20, FSL_E500v1
beq 1f
li %r20, 0
mtspr SPR_MAS7, %r20
1:
blr
.globl zero_mas8
zero_mas8:
mfpvr %r20

3
sys/powerpc/booke/trap_subr.S
View File

@ -765,7 +765,8 @@ search_failed:
mtspr SPR_MAS2, %r27
mtspr SPR_MAS3, %r23
bl zero_mas7
li %r23, 0
mtspr SPR_MAS7, %r23
bl zero_mas8
isync