Change the RX EDMA path to first complete the FIFO, then re-populate it
with fresh descriptors, before handling the frames. Wrap it all in the RX locks. Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be drained and replenished very quickly. Ideally, I'll eventually move this RX FIFO drain/fill into the interrupt handler, only deferring the actual frame completion.
This commit is contained in:
Adrian Chadd
parent
8d467c41b0
commit
0b59717b4b
@ -156,6 +156,7 @@ ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
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{
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struct ath_hal *ah = sc->sc_ah;
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ATH_RX_LOCK(sc);
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ath_hal_stoppcurecv(ah);
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ath_hal_setrxfilter(ah, 0);
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ath_hal_stopdmarecv(ah);
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@ -173,6 +174,7 @@ ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
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m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
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sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
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}
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ATH_RX_UNLOCK(sc);
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}
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/*
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@ -187,6 +189,8 @@ ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
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struct ath_buf *bf;
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int i, j;
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ATH_RX_LOCK_ASSERT(sc);
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i = re->m_fifo_head;
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for (j = 0; j < re->m_fifo_depth; j++) {
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bf = re->m_fifo[i];
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@ -221,6 +225,8 @@ ath_edma_startrecv(struct ath_softc *sc)
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{
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struct ath_hal *ah = sc->sc_ah;
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ATH_RX_LOCK(sc);
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/* Enable RX FIFO */
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ath_hal_rxena(ah);
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@ -266,6 +272,9 @@ ath_edma_startrecv(struct ath_softc *sc)
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ath_mode_init(sc);
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ath_hal_startpcurecv(ah);
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ATH_RX_UNLOCK(sc);
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return (0);
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}
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@ -300,16 +309,21 @@ ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
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struct ath_desc *ds;
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struct ath_buf *bf;
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struct mbuf *m;
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HAL_STATUS status;
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struct ath_hal *ah = sc->sc_ah;
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uint64_t tsf;
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int16_t nf;
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int ngood = 0;
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ath_bufhead rxlist;
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struct ath_buf *next;
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TAILQ_INIT(&rxlist);
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tsf = ath_hal_gettsf64(ah);
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nf = ath_hal_getchannoise(ah, sc->sc_curchan);
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sc->sc_stats.ast_rx_noise = nf;
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ATH_RX_LOCK(sc);
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do {
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bf = re->m_fifo[re->m_fifo_head];
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/* This shouldn't occur! */
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@ -330,12 +344,13 @@ ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
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bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
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BUS_DMASYNC_POSTREAD);
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rs = &bf->bf_status.ds_rxstat;
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status = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr, NULL, rs);
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bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
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NULL, rs);
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#ifdef ATH_DEBUG
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if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
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ath_printrxbuf(sc, bf, 0, status == HAL_OK);
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ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK);
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#endif
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if (status == HAL_EINPROGRESS)
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if (bf->bf_rxstatus == HAL_EINPROGRESS)
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break;
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/*
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@ -349,21 +364,11 @@ ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
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"%s: Q%d: completed!\n", __func__, qtype);
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/*
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* Remove the FIFO entry!
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* Remove the FIFO entry and place it on the completion
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* queue.
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*/
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re->m_fifo[re->m_fifo_head] = NULL;
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/*
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* Skip the RX descriptor status - start at the data offset
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*/
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m_adj(m, sc->sc_rx_statuslen);
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/* Handle the frame */
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if (ath_rx_pkt(sc, rs, status, tsf, nf, qtype, bf))
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ngood++;
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/* Free the buffer/mbuf */
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ath_edma_rxbuf_free(sc, bf);
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TAILQ_INSERT_TAIL(&rxlist, bf, bf_list);
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/* Bump the descriptor FIFO stats */
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INCR(re->m_fifo_head, re->m_fifolen);
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@ -371,6 +376,36 @@ ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
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/* XXX check it doesn't fall below 0 */
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} while (re->m_fifo_depth > 0);
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/* Append some more fresh frames to the FIFO */
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if (dosched)
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ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
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ATH_RX_UNLOCK(sc);
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/* Handle the completed descriptors */
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TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
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/*
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* Skip the RX descriptor status - start at the data offset
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*/
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m_adj(bf->bf_m, sc->sc_rx_statuslen);
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/* Handle the frame */
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/*
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* Note: this may or may not free bf->bf_m and sync/unmap
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* the frame.
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*/
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if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf))
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ngood++;
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}
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/* Free in one set, inside the lock */
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ATH_RX_LOCK(sc);
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TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
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/* Free the buffer/mbuf */
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ath_edma_rxbuf_free(sc, bf);
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}
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ATH_RX_UNLOCK(sc);
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/* Handle resched and kickpcu appropriately */
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ATH_PCU_LOCK(sc);
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if (dosched && sc->sc_kickpcu) {
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@ -386,10 +421,6 @@ ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
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}
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ATH_PCU_UNLOCK(sc);
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/* Append some more fresh frames to the FIFO */
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if (dosched)
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ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
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return (ngood);
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}
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@ -435,6 +466,8 @@ ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
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int error;
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int len;
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ATH_RX_LOCK_ASSERT(sc);
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// device_printf(sc->sc_dev, "%s: called; bf=%p\n", __func__, bf);
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m = m_getm(NULL, sc->sc_edma_bufsize, M_DONTWAIT, MT_DATA);
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@ -498,6 +531,8 @@ ath_edma_rxbuf_alloc(struct ath_softc *sc)
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struct ath_buf *bf;
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int error;
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ATH_RX_LOCK_ASSERT(sc);
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/* Allocate buffer */
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bf = TAILQ_FIRST(&sc->sc_rxbuf);
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/* XXX shouldn't happen upon startup? */
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@ -526,6 +561,9 @@ static void
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ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
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{
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ATH_RX_LOCK_ASSERT(sc);
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/* We're doing this multiple times? */
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bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
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if (bf->bf_m) {
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@ -550,6 +588,8 @@ ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
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struct ath_buf *bf;
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int i;
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ATH_RX_LOCK_ASSERT(sc);
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/*
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* Allocate buffers until the FIFO is full or nbufs is reached.
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*/
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@ -616,6 +656,8 @@ ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
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struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
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int i;
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ATH_RX_LOCK_ASSERT(sc);
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for (i = 0; i < re->m_fifolen; i++) {
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if (re->m_fifo[i] != NULL) {
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#ifdef ATH_DEBUG
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@ -647,6 +689,8 @@ ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
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{
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struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
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ATH_RX_LOCK_ASSERT(sc);
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if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
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device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
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__func__,
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@ -704,8 +748,10 @@ ath_edma_dma_rxsetup(struct ath_softc *sc)
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if (error != 0)
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return error;
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ATH_RX_LOCK(sc);
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(void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
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(void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
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ATH_RX_UNLOCK(sc);
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return (0);
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}
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@ -716,11 +762,13 @@ ath_edma_dma_rxteardown(struct ath_softc *sc)
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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ATH_RX_LOCK(sc);
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ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
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ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
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ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
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ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
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ATH_RX_UNLOCK(sc);
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/* Free RX ath_buf */
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/* Free RX DMA tag */
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@ -189,6 +189,7 @@ struct ath_buf {
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TAILQ_ENTRY(ath_buf) bf_list;
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struct ath_buf * bf_next; /* next buffer in the aggregate */
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int bf_nseg;
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HAL_STATUS bf_rxstatus;
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uint16_t bf_flags; /* status flags (below) */
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struct ath_desc *bf_desc; /* virtual addr of desc */
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struct ath_desc_status bf_status; /* tx/rx status */
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