From 0b9427de889bc68aae100716e5bfc737842c200a Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Tue, 21 Aug 2001 07:53:37 +0000 Subject: [PATCH] The general conesnsus on irc was that pci bios for config registers and such was just a bad idea and one that users should be forced to enable if they want it. This patch introduces a hw.pci.enable_pcibios tunable for those people. This does not impact the pcibios interrupt routing at all. Approved by: peter, msmith --- sys/amd64/include/pc/bios.h | 1 + sys/amd64/pci/pci_cfgreg.c | 27 +++++++++++++++++++++++++-- sys/i386/include/pc/bios.h | 1 + sys/i386/pci/pci_cfgreg.c | 27 +++++++++++++++++++++++++-- sys/i386/pci/pci_pir.c | 27 +++++++++++++++++++++++++-- 5 files changed, 77 insertions(+), 6 deletions(-) diff --git a/sys/amd64/include/pc/bios.h b/sys/amd64/include/pc/bios.h index 755877b830ca..ae13bd418264 100644 --- a/sys/amd64/include/pc/bios.h +++ b/sys/amd64/include/pc/bios.h @@ -207,6 +207,7 @@ struct bios_args { /* * PCI BIOS functions */ +#define PCIBIOS_BIOS_PRESENT 0xb101 #define PCIBIOS_READ_CONFIG_BYTE 0xb108 #define PCIBIOS_READ_CONFIG_WORD 0xb109 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c index 3538969df5ad..1913075fc183 100644 --- a/sys/amd64/pci/pci_cfgreg.c +++ b/sys/amd64/pci/pci_cfgreg.c @@ -55,6 +55,9 @@ static int cfgmech; static int devmax; static int usebios; +static int enable_pcibios = 0; + +TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios); static int pci_cfgintr_unique(struct PIR_entry *pe, int pin); static int pci_cfgintr_linked(struct PIR_entry *pe, int pin); @@ -449,14 +452,34 @@ pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); } +static u_int16_t +pcibios_get_version(void) +{ + struct bios_regs args; + + args.eax = PCIBIOS_BIOS_PRESENT; + if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) + return (0x0000); + if (args.edx != 0x20494350) + return (0x0000); + return (args.ebx & 0xffff); +} + /* * Determine whether there is a PCI BIOS present */ static int pcibios_cfgopen(void) { - /* check for a found entrypoint */ - return(PCIbios.entry != 0); + u_int16_t v = 0; + + if (PCIbios.entry != 0 && enable_pcibios) { + v = pcibios_get_version(); + if (v > 0) + printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8, + v & 0xff); + } + return (v > 0); } /* diff --git a/sys/i386/include/pc/bios.h b/sys/i386/include/pc/bios.h index 755877b830ca..ae13bd418264 100644 --- a/sys/i386/include/pc/bios.h +++ b/sys/i386/include/pc/bios.h @@ -207,6 +207,7 @@ struct bios_args { /* * PCI BIOS functions */ +#define PCIBIOS_BIOS_PRESENT 0xb101 #define PCIBIOS_READ_CONFIG_BYTE 0xb108 #define PCIBIOS_READ_CONFIG_WORD 0xb109 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a diff --git a/sys/i386/pci/pci_cfgreg.c b/sys/i386/pci/pci_cfgreg.c index 3538969df5ad..1913075fc183 100644 --- a/sys/i386/pci/pci_cfgreg.c +++ b/sys/i386/pci/pci_cfgreg.c @@ -55,6 +55,9 @@ static int cfgmech; static int devmax; static int usebios; +static int enable_pcibios = 0; + +TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios); static int pci_cfgintr_unique(struct PIR_entry *pe, int pin); static int pci_cfgintr_linked(struct PIR_entry *pe, int pin); @@ -449,14 +452,34 @@ pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); } +static u_int16_t +pcibios_get_version(void) +{ + struct bios_regs args; + + args.eax = PCIBIOS_BIOS_PRESENT; + if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) + return (0x0000); + if (args.edx != 0x20494350) + return (0x0000); + return (args.ebx & 0xffff); +} + /* * Determine whether there is a PCI BIOS present */ static int pcibios_cfgopen(void) { - /* check for a found entrypoint */ - return(PCIbios.entry != 0); + u_int16_t v = 0; + + if (PCIbios.entry != 0 && enable_pcibios) { + v = pcibios_get_version(); + if (v > 0) + printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8, + v & 0xff); + } + return (v > 0); } /* diff --git a/sys/i386/pci/pci_pir.c b/sys/i386/pci/pci_pir.c index 3538969df5ad..1913075fc183 100644 --- a/sys/i386/pci/pci_pir.c +++ b/sys/i386/pci/pci_pir.c @@ -55,6 +55,9 @@ static int cfgmech; static int devmax; static int usebios; +static int enable_pcibios = 0; + +TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios); static int pci_cfgintr_unique(struct PIR_entry *pe, int pin); static int pci_cfgintr_linked(struct PIR_entry *pe, int pin); @@ -449,14 +452,34 @@ pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); } +static u_int16_t +pcibios_get_version(void) +{ + struct bios_regs args; + + args.eax = PCIBIOS_BIOS_PRESENT; + if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) + return (0x0000); + if (args.edx != 0x20494350) + return (0x0000); + return (args.ebx & 0xffff); +} + /* * Determine whether there is a PCI BIOS present */ static int pcibios_cfgopen(void) { - /* check for a found entrypoint */ - return(PCIbios.entry != 0); + u_int16_t v = 0; + + if (PCIbios.entry != 0 && enable_pcibios) { + v = pcibios_get_version(); + if (v > 0) + printf("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8, + v & 0xff); + } + return (v > 0); } /*