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Use FreeBSD/arm approach for handling bus space access: space tag is a pointer

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to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.
This commit is contained in:
Oleksandr Tymoshenko 2009-04-15 02:28:26 +00:00
parent 20eb34e255
commit 0c6b091e31
14 changed files with 1249 additions and 867 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
sys/conf/files.mips
View File

@ -54,6 +54,7 @@ mips/mips/pm_machdep.c standard
mips/mips/swtch.S standard
mips/mips/tlb.S standard
mips/mips/bus_space_generic.c standard
mips/mips/busdma_machdep.c standard
mips/mips/cache.c standard
mips/mips/cache_mipsNN.c standard

2
sys/mips/adm5120/obio.c
View File

@ -269,7 +269,7 @@ obio_activate_resource(device_t bus, device_t child, int type, int rid,
vaddr = (void *)MIPS_PHYS_TO_KSEG1((intptr_t)rman_get_start(r));
rman_set_virtual(r, vaddr);
rman_set_bustag(r, MIPS_BUS_SPACE_MEM);
rman_set_bustag(r, &mips_bus_space_generic);
rman_set_bushandle(r, (bus_space_handle_t)vaddr);
}

4
sys/mips/adm5120/uart_cpu_adm5120.c
View File

@ -67,7 +67,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->ops = uart_getops(&uart_adm5120_uart_class);
di->bas.chan = 0;
di->bas.bst = 0;
di->bas.bst = &mips_bus_space_generic;
di->bas.regshft = 0;
di->bas.rclk = 0;
di->baudrate = 115200;
@ -76,7 +76,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->parity = UART_PARITY_NONE;
uart_bus_space_io = 0;
uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(ADM5120_BASE_UART0);
uart_bus_space_mem = &mips_bus_space_generic;
di->bas.bsh = MIPS_PHYS_TO_KSEG1(ADM5120_BASE_UART0);
return (0);

2
sys/mips/alchemy/obio.c
View File

@ -269,7 +269,7 @@ obio_activate_resource(device_t bus, device_t child, int type, int rid,
vaddr = (void *)MIPS_PHYS_TO_KSEG1((intptr_t)rman_get_start(r));
rman_set_virtual(r, vaddr);
rman_set_bustag(r, MIPS_BUS_SPACE_MEM);
rman_set_bustag(r, &mips_bus_space_generic);
rman_set_bushandle(r, (bus_space_handle_t)vaddr);
}

4
sys/mips/alchemy/uart_cpu_alchemy.c
View File

@ -63,7 +63,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = 0;
di->bas.bst = &mips_bus_space_generic;
di->bas.regshft = 0;
di->bas.rclk = 0;
di->baudrate = 115200;
@ -72,7 +72,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->parity = UART_PARITY_NONE;
uart_bus_space_io = 0;
uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(UART0_BASE);
uart_bus_space_mem = &mips_bus_space_generic;
di->bas.bsh = MIPS_PHYS_TO_KSEG1(UART0_BASE);
return (0);

4
sys/mips/idt/uart_bus_rc32434.c
View File

@ -88,10 +88,10 @@ uart_rc32434_probe(device_t dev)
sc->sc_class = &uart_ns8250_class;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
sc->sc_sysdev->bas.regshft = 2;
sc->sc_sysdev->bas.bst = 0;
sc->sc_sysdev->bas.bst = &mips_bus_space_generic;
sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0);
sc->sc_bas.regshft = 2;
sc->sc_bas.bst = 0;
sc->sc_bas.bst = &mips_bus_space_generic;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0);
return (uart_bus_probe(dev, 2, 330000000UL/2, 0, 0));

4
sys/mips/idt/uart_cpu_rc32434.c
View File

@ -71,7 +71,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
/* Got it. Fill in the instance and return it. */
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = 0;
di->bas.bst = &mips_bus_space_generic;
di->bas.regshft = 2;
di->bas.rclk = 330000000UL/2; /* IPbus clock */
di->baudrate = 115200;
@ -79,7 +79,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
uart_bus_space_io = 0;
uart_bus_space_mem = 0;
uart_bus_space_mem = &mips_bus_space_generic;
di->bas.bsh = MIPS_PHYS_TO_KSEG1(maddr);
return (0);
}

2
sys/mips/include/_bus.h
View File

@ -43,7 +43,7 @@ typedef uintptr_t bus_size_t;
/*
* Access methods for bus resources and address space.
*/
typedef long bus_space_tag_t;
typedef struct bus_space *bus_space_tag_t;
typedef u_long bus_space_handle_t;
#endif
#endif /* MIPS_INCLUDE__BUS_H */

1442
sys/mips/include/bus.h
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File diff suppressed because it is too large Load Diff

67
sys/mips/malta/gt_pci.c
View File

@ -94,8 +94,6 @@ __FBSDID("$FreeBSD$");
struct gt_pci_softc {
device_t sc_dev;
bus_space_tag_t sc_st;
bus_space_tag_t sc_pciio;
bus_space_tag_t sc_pcimem;
bus_space_handle_t sc_ioh_icu1;
bus_space_handle_t sc_ioh_icu2;
bus_space_handle_t sc_ioh_elcr;
@ -126,14 +124,14 @@ gt_pci_set_icus(struct gt_pci_softc *sc)
else
sc->sc_imask |= (1U << 2);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
sc->sc_imask & 0xff);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, PIC_OCW1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
(sc->sc_imask >> 8) & 0xff);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0,
bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
sc->sc_elcr & 0xff);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
(sc->sc_elcr >> 8) & 0xff);
}
@ -145,9 +143,9 @@ gt_pci_intr(void *v)
int irq;
for (;;) {
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
OCW3_SEL | OCW3_P);
irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3);
irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
if ((irq & OCW3_POLL_PENDING) == 0)
{
return FILTER_HANDLED;
@ -156,9 +154,9 @@ gt_pci_intr(void *v)
irq = OCW3_POLL_IRQ(irq);
if (irq == 2) {
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
PIC_OCW3, OCW3_SEL | OCW3_P);
irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu2,
irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
PIC_OCW3);
if (irq & OCW3_POLL_PENDING)
irq = OCW3_POLL_IRQ(irq) + 8;
@ -177,13 +175,13 @@ gt_pci_intr(void *v)
/* Send a specific EOI to the 8259. */
if (irq > 7) {
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
OCW2_ILS(irq & 7));
irq = 2;
}
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW2,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
}
@ -208,8 +206,7 @@ gt_pci_attach(device_t dev)
busno = 0;
sc->sc_dev = dev;
sc->sc_busno = busno;
sc->sc_pciio = MIPS_BUS_SPACE_IO;
sc->sc_pcimem = MIPS_BUS_SPACE_MEM;
sc->sc_st = &mips_bus_space_generic;
/* Use KSEG1 to access IO ports for it is uncached */
sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE);
@ -239,11 +236,11 @@ gt_pci_attach(device_t dev)
* Map the PIC/ELCR registers.
*/
#if 0
if (bus_space_map(sc->sc_pciio, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
device_printf(dev, "unable to map ELCR registers\n");
if (bus_space_map(sc->sc_pciio, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
device_printf(dev, "unable to map ICU1 registers\n");
if (bus_space_map(sc->sc_pciio, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
device_printf(dev, "unable to map ICU2 registers\n");
#else
sc->sc_ioh_elcr = sc->sc_io + 0x4d0;
@ -262,58 +259,58 @@ gt_pci_attach(device_t dev)
* Initialize the 8259s.
*/
/* reset, program device, 4 bytes */
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
ICW1_RESET | ICW1_IC4);
/*
* XXX: values from NetBSD's <dev/ic/i8259reg.h>
*/
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
0/*XXX*/);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
1 << 2);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
ICW4_8086);
/* mask all interrupts */
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
sc->sc_imask & 0xff);
/* enable special mask mode */
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
OCW3_SEL | OCW3_ESMM | OCW3_SMM);
/* read IRR by default */
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
OCW3_SEL | OCW3_RR);
/* reset, program device, 4 bytes */
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
ICW1_RESET | ICW1_IC4);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
0/*XXX*/);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
1 << 2);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
ICW4_8086);
/* mask all interrupts */
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
sc->sc_imask & 0xff);
/* enable special mask mode */
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
OCW3_SEL | OCW3_ESMM | OCW3_SMM);
/* read IRR by default */
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
OCW3_SEL | OCW3_RR);
/*
* Default all interrupts to edge-triggered.
*/
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0,
bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
sc->sc_elcr & 0xff);
bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1,
bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
(sc->sc_elcr >> 8) & 0xff);
/*
@ -570,12 +567,12 @@ gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
break;
case SYS_RES_MEMORY:
rm = &sc->sc_mem_rman;
bt = sc->sc_pcimem;
bt = sc->sc_st;
bh = sc->sc_mem;
break;
case SYS_RES_IOPORT:
rm = &sc->sc_io_rman;
bt = sc->sc_pciio;
bt = sc->sc_st;
bh = sc->sc_io;
break;
default:

2
sys/mips/malta/obio.c
View File

@ -84,7 +84,7 @@ obio_attach(device_t dev)
{
struct obio_softc *sc = device_get_softc(dev);
sc->oba_st = MIPS_BUS_SPACE_IO;
sc->oba_st = &mips_bus_space_generic;
sc->oba_addr = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
sc->oba_size = MALTA_PCIMEM3_SIZE;
sc->oba_rman.rm_type = RMAN_ARRAY;

4
sys/mips/malta/uart_bus_maltausart.c
View File

@ -88,9 +88,9 @@ uart_malta_probe(device_t dev)
sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
sc->sc_class = &uart_ns8250_class;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
sc->sc_sysdev->bas.bst = 0;
sc->sc_sysdev->bas.bst = &mips_bus_space_generic;
sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
sc->sc_bas.bst = 0;
sc->sc_bas.bst = &mips_bus_space_generic;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
return(uart_bus_probe(dev, 0, 0, 0, 0));
}

8
sys/mips/malta/uart_cpu_maltausart.c
View File

@ -67,7 +67,8 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = 0;
di->bas.bst = &mips_bus_space_generic;
di->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
di->bas.regshft = 0;
di->bas.rclk = 0;
di->baudrate = 115200;
@ -75,8 +76,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
uart_bus_space_io = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
di->bas.bsh = MIPS_PHYS_TO_KSEG1(MALTA_UART0ADR);
uart_bus_space_io = NULL;
uart_bus_space_mem = &mips_bus_space_generic;
return (0);
}

570
sys/mips/mips/bus_space_generic.c Normal file
View File

@ -0,0 +1,570 @@
/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */
/*-
* $Id: bus.h,v 1.6 2007/08/09 11:23:32 katta Exp $
*
* Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* from: src/sys/alpha/include/bus.h,v 1.5 1999/08/28 00:38:40 peter
* $FreeBSD$
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/ktr.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_kern.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <machine/cache.h>
struct bus_space mips_bus_space_generic = {
/* cookie */
(void *) 0,
/* mapping/unmapping */
generic_bs_map,
generic_bs_unmap,
generic_bs_subregion,
/* allocation/deallocation */
NULL,
NULL,
/* barrier */
generic_bs_barrier,
/* read (single) */
generic_bs_r_1,
generic_bs_r_2,
generic_bs_r_4,
NULL,
/* read multiple */
generic_bs_rm_1,
generic_bs_rm_2,
generic_bs_rm_4,
NULL,
/* read region */
generic_bs_rr_1,
generic_bs_rr_2,
generic_bs_rr_4,
NULL,
/* write (single) */
generic_bs_w_1,
generic_bs_w_2,
generic_bs_w_4,
NULL,
/* write multiple */
generic_bs_wm_1,
generic_bs_wm_2,
generic_bs_wm_4,
NULL,
/* write region */
NULL,
generic_bs_wr_2,
generic_bs_wr_4,
NULL,
/* set multiple */
NULL,
NULL,
NULL,
NULL,
/* set region */
NULL,
generic_bs_sr_2,
generic_bs_sr_4,
NULL,
/* copy */
NULL,
generic_bs_c_2,
NULL,
NULL,
/* read (single) stream */
generic_bs_r_1,
generic_bs_r_2,
generic_bs_r_4,
NULL,
/* read multiple stream */
generic_bs_rm_1,
generic_bs_rm_2,
generic_bs_rm_4,
NULL,
/* read region stream */
generic_bs_rr_1,
generic_bs_rr_2,
generic_bs_rr_4,
NULL,
/* write (single) stream */
generic_bs_w_1,
generic_bs_w_2,
generic_bs_w_4,
NULL,
/* write multiple stream */
generic_bs_wm_1,
generic_bs_wm_2,
generic_bs_wm_4,
NULL,
/* write region stream */
NULL,
generic_bs_wr_2,
generic_bs_wr_4,
NULL,
};
int
generic_bs_map(void *t __unused, bus_addr_t addr,
bus_size_t size __unused, int flags __unused,
bus_space_handle_t *bshp)
{
*bshp = addr;
return (0);
}
void
generic_bs_unmap(void *t __unused, bus_space_handle_t bh __unused,
bus_size_t size __unused)
{
/* Do nothing */
}
int
generic_bs_subregion(void *t __unused, bus_space_handle_t handle __unused,
bus_size_t offset __unused, bus_size_t size __unused,
bus_space_handle_t *nhandle __unused)
{
printf("SUBREGION?!?!?!\n");
/* Do nothing */
return (0);
}
u_int8_t
generic_bs_r_1(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return (readb(handle + offset));
}
u_int16_t
generic_bs_r_2(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return (readw(handle + offset));
}
u_int32_t
generic_bs_r_4(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return (readl(handle + offset));
}
void
generic_bs_rm_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t *addr, size_t count)
{
while (count--)
*addr++ = readb(bsh + offset);
}
void
generic_bs_rm_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--)
*addr++ = readw(baddr);
}
void
generic_bs_rm_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--)
*addr++ = readl(baddr);
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle and starting at `offset' and copy into
* buffer provided.
*/
void
generic_bs_rr_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = readb(baddr);
baddr += 1;
}
}
void
generic_bs_rr_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = readw(baddr);
baddr += 2;
}
}
void
generic_bs_rr_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = readl(baddr);
baddr += 4;
}
}
/*
* Write the 1, 2, 4, or 8 byte value `value' to bus space
* described by tag/handle/offset.
*/
void
generic_bs_w_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t value)
{
writeb(bsh + offset, value);
}
void
generic_bs_w_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value)
{
writew(bsh + offset, value);
}
void
generic_bs_w_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value)
{
writel(bsh + offset, value);
}
/*
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer
* provided to bus space described by tag/handle/offset.
*/
void
generic_bs_wm_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, const u_int8_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--)
writeb(baddr, *addr++);
}
void
generic_bs_wm_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, const u_int16_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--)
writew(baddr, *addr++);
}
void
generic_bs_wm_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, const u_int32_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--)
writel(baddr, *addr++);
}
/*
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
* to bus space described by tag/handle starting at `offset'.
*/
void
generic_bs_wr_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, const u_int8_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
writeb(baddr, *addr++);
baddr += 1;
}
}
void
generic_bs_wr_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, const u_int16_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
writew(baddr, *addr++);
baddr += 2;
}
}
void
generic_bs_wr_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, const u_int32_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
writel(baddr, *addr++);
baddr += 4;
}
}
/*
* Write the 1, 2, 4, or 8 byte value `val' to bus space described
* by tag/handle/offset `count' times.
*/
void
generic_bs_sm_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
while (count--)
writeb(addr, value);
}
void
generic_bs_sm_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
while (count--)
writew(addr, value);
}
void
generic_bs_sm_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
while (count--)
writel(addr, value);
}
/*
* Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
* by tag/handle starting at `offset'.
*/
void
generic_bs_sr_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
for (; count != 0; count--, addr++)
writeb(addr, value);
}
void
generic_bs_sr_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
for (; count != 0; count--, addr += 2)
writew(addr, value);
}
void
generic_bs_sr_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
for (; count != 0; count--, addr += 4)
writel(addr, value);
}
/*
* Copy `count' 1, 2, 4, or 8 byte values from bus space starting
* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
*/
void
generic_bs_c_1(void *t, bus_space_handle_t bsh1,
bus_size_t off1, bus_space_handle_t bsh2,
bus_size_t off2, size_t count)
{
bus_addr_t addr1 = bsh1 + off1;
bus_addr_t addr2 = bsh2 + off2;
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; count != 0; count--, addr1++, addr2++)
writeb(addr2, readb(addr1));
} else {
/* dest after src: copy backwards */
for (addr1 += (count - 1), addr2 += (count - 1);
count != 0; count--, addr1--, addr2--)
writeb(addr2, readb(addr1));
}
}
void
generic_bs_c_2(void *t, bus_space_handle_t bsh1,
bus_size_t off1, bus_space_handle_t bsh2,
bus_size_t off2, size_t count)
{
bus_addr_t addr1 = bsh1 + off1;
bus_addr_t addr2 = bsh2 + off2;
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; count != 0; count--, addr1 += 2, addr2 += 2)
writew(addr2, readw(addr1));
} else {
/* dest after src: copy backwards */
for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1);
count != 0; count--, addr1 -= 2, addr2 -= 2)
writew(addr2, readw(addr1));
}
}
void
generic_bs_c_4(void *t, bus_space_handle_t bsh1,
bus_size_t off1, bus_space_handle_t bsh2,
bus_size_t off2, size_t count)
{
bus_addr_t addr1 = bsh1 + off1;
bus_addr_t addr2 = bsh2 + off2;
if (addr1 >= addr2) {
/* src after dest: copy forward */
for (; count != 0; count--, addr1 += 4, addr2 += 4)
writel(addr2, readl(addr1));
} else {
/* dest after src: copy backwards */
for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1);
count != 0; count--, addr1 -= 4, addr2 -= 4)
writel(addr2, readl(addr1));
}
}
void
generic_bs_barrier(void *t __unused,
bus_space_handle_t bsh __unused,
bus_size_t offset __unused, bus_size_t len __unused,
int flags)
{
#if 0
if (flags & BUS_SPACE_BARRIER_WRITE)
mips_dcache_wbinv_all();
#endif
}