d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

At least the ASUS Triton motherboards don't disable the PCI bus configuration

Browse Source 
accesses after the BIOS bus scan. The previous revision made the assumption,
that every PCI motherboard did ...

Change the test on the initial value of the CONF1_ADDR_PORT register in a way
that makes the probe succeed on triton based motherboards, without breaking
the EISA motherboard that has some non-PCI register at the same address.
This commit is contained in:
Stefan Eßer 1995-10-17 15:23:14 +00:00
parent c8cd425122
commit 0e2f699b9e
6 changed files with 30 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
sys/amd64/pci/pci_bus.c
View File

@ -1,6 +1,6 @@
/**************************************************************************
**
** $Id: pcibus.c,v 1.16 1995/10/09 21:56:24 se Exp $
** $Id: pcibus.c,v 1.17 1995/10/15 23:43:08 se Exp $
**
** pci bus subroutines for i386 architecture.
**
@ -146,7 +146,8 @@ DATA_SET (pcibus_set, i386pci);
#define CONF1_ENABLE 0x80000000ul
#define CONF1_ENABLE_CHK 0x80000000ul
#define CONF1_ENABLE_CHK1 0xFF000001ul
#define CONF1_ENABLE_MSK 0x00ff07fful
#define CONF1_ENABLE_CHK1 0xff000001ul
#define CONF1_ENABLE_MSK1 0x80000001ul
#define CONF1_ENABLE_RES1 0x80000000ul
@ -187,7 +188,7 @@ pcibus_setup (void)
oldval1 = inl (CONF1_ADDR_PORT);
if (bootverbose) {
printf ("pcibus_setup(1):\tmode1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
printf ("pcibus_setup(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
}
/*---------------------------------------
@ -195,7 +196,7 @@ pcibus_setup (void)
**---------------------------------------
*/
if ((oldval1 & CONF1_ENABLE) == 0) {
if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
pci_mechanism = 1;
pci_maxdevice = 32;

9
sys/amd64/pci/pci_cfgreg.c
View File

@ -1,6 +1,6 @@
/**************************************************************************
**
** $Id: pcibus.c,v 1.16 1995/10/09 21:56:24 se Exp $
** $Id: pcibus.c,v 1.17 1995/10/15 23:43:08 se Exp $
**
** pci bus subroutines for i386 architecture.
**
@ -146,7 +146,8 @@ DATA_SET (pcibus_set, i386pci);
#define CONF1_ENABLE 0x80000000ul
#define CONF1_ENABLE_CHK 0x80000000ul
#define CONF1_ENABLE_CHK1 0xFF000001ul
#define CONF1_ENABLE_MSK 0x00ff07fful
#define CONF1_ENABLE_CHK1 0xff000001ul
#define CONF1_ENABLE_MSK1 0x80000001ul
#define CONF1_ENABLE_RES1 0x80000000ul
@ -187,7 +188,7 @@ pcibus_setup (void)
oldval1 = inl (CONF1_ADDR_PORT);
if (bootverbose) {
printf ("pcibus_setup(1):\tmode1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
printf ("pcibus_setup(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
}
/*---------------------------------------
@ -195,7 +196,7 @@ pcibus_setup (void)
**---------------------------------------
*/
if ((oldval1 & CONF1_ENABLE) == 0) {
if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
pci_mechanism = 1;
pci_maxdevice = 32;

9
sys/i386/isa/pcibus.c
View File

@ -1,6 +1,6 @@
/**************************************************************************
**
** $Id: pcibus.c,v 1.16 1995/10/09 21:56:24 se Exp $
** $Id: pcibus.c,v 1.17 1995/10/15 23:43:08 se Exp $
**
** pci bus subroutines for i386 architecture.
**
@ -146,7 +146,8 @@ DATA_SET (pcibus_set, i386pci);
#define CONF1_ENABLE 0x80000000ul
#define CONF1_ENABLE_CHK 0x80000000ul
#define CONF1_ENABLE_CHK1 0xFF000001ul
#define CONF1_ENABLE_MSK 0x00ff07fful
#define CONF1_ENABLE_CHK1 0xff000001ul
#define CONF1_ENABLE_MSK1 0x80000001ul
#define CONF1_ENABLE_RES1 0x80000000ul
@ -187,7 +188,7 @@ pcibus_setup (void)
oldval1 = inl (CONF1_ADDR_PORT);
if (bootverbose) {
printf ("pcibus_setup(1):\tmode1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
printf ("pcibus_setup(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
}
/*---------------------------------------
@ -195,7 +196,7 @@ pcibus_setup (void)
**---------------------------------------
*/
if ((oldval1 & CONF1_ENABLE) == 0) {
if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
pci_mechanism = 1;
pci_maxdevice = 32;

9
sys/i386/pci/pci_bus.c
View File

@ -1,6 +1,6 @@
/**************************************************************************
**
** $Id: pcibus.c,v 1.16 1995/10/09 21:56:24 se Exp $
** $Id: pcibus.c,v 1.17 1995/10/15 23:43:08 se Exp $
**
** pci bus subroutines for i386 architecture.
**
@ -146,7 +146,8 @@ DATA_SET (pcibus_set, i386pci);
#define CONF1_ENABLE 0x80000000ul
#define CONF1_ENABLE_CHK 0x80000000ul
#define CONF1_ENABLE_CHK1 0xFF000001ul
#define CONF1_ENABLE_MSK 0x00ff07fful
#define CONF1_ENABLE_CHK1 0xff000001ul
#define CONF1_ENABLE_MSK1 0x80000001ul
#define CONF1_ENABLE_RES1 0x80000000ul
@ -187,7 +188,7 @@ pcibus_setup (void)
oldval1 = inl (CONF1_ADDR_PORT);
if (bootverbose) {
printf ("pcibus_setup(1):\tmode1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
printf ("pcibus_setup(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
}
/*---------------------------------------
@ -195,7 +196,7 @@ pcibus_setup (void)
**---------------------------------------
*/
if ((oldval1 & CONF1_ENABLE) == 0) {
if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
pci_mechanism = 1;
pci_maxdevice = 32;

9
sys/i386/pci/pci_cfgreg.c
View File

@ -1,6 +1,6 @@
/**************************************************************************
**
** $Id: pcibus.c,v 1.16 1995/10/09 21:56:24 se Exp $
** $Id: pcibus.c,v 1.17 1995/10/15 23:43:08 se Exp $
**
** pci bus subroutines for i386 architecture.
**
@ -146,7 +146,8 @@ DATA_SET (pcibus_set, i386pci);
#define CONF1_ENABLE 0x80000000ul
#define CONF1_ENABLE_CHK 0x80000000ul
#define CONF1_ENABLE_CHK1 0xFF000001ul
#define CONF1_ENABLE_MSK 0x00ff07fful
#define CONF1_ENABLE_CHK1 0xff000001ul
#define CONF1_ENABLE_MSK1 0x80000001ul
#define CONF1_ENABLE_RES1 0x80000000ul
@ -187,7 +188,7 @@ pcibus_setup (void)
oldval1 = inl (CONF1_ADDR_PORT);
if (bootverbose) {
printf ("pcibus_setup(1):\tmode1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
printf ("pcibus_setup(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
}
/*---------------------------------------
@ -195,7 +196,7 @@ pcibus_setup (void)
**---------------------------------------
*/
if ((oldval1 & CONF1_ENABLE) == 0) {
if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
pci_mechanism = 1;
pci_maxdevice = 32;

9
sys/i386/pci/pci_pir.c
View File

@ -1,6 +1,6 @@
/**************************************************************************
**
** $Id: pcibus.c,v 1.16 1995/10/09 21:56:24 se Exp $
** $Id: pcibus.c,v 1.17 1995/10/15 23:43:08 se Exp $
**
** pci bus subroutines for i386 architecture.
**
@ -146,7 +146,8 @@ DATA_SET (pcibus_set, i386pci);
#define CONF1_ENABLE 0x80000000ul
#define CONF1_ENABLE_CHK 0x80000000ul
#define CONF1_ENABLE_CHK1 0xFF000001ul
#define CONF1_ENABLE_MSK 0x00ff07fful
#define CONF1_ENABLE_CHK1 0xff000001ul
#define CONF1_ENABLE_MSK1 0x80000001ul
#define CONF1_ENABLE_RES1 0x80000000ul
@ -187,7 +188,7 @@ pcibus_setup (void)
oldval1 = inl (CONF1_ADDR_PORT);
if (bootverbose) {
printf ("pcibus_setup(1):\tmode1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
printf ("pcibus_setup(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n", oldval1);
}
/*---------------------------------------
@ -195,7 +196,7 @@ pcibus_setup (void)
**---------------------------------------
*/
if ((oldval1 & CONF1_ENABLE) == 0) {
if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
pci_mechanism = 1;
pci_maxdevice = 32;