Simplify trapcode setup by placing a copy of the generic trap handler at
every possible trap address by default. This also makes sure the kernel notices (and panics at) traps from newer CPUs that the kernel was not expecting rather than executing gibberish memory.
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@ -256,6 +256,7 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
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vm_offset_t startkernel, endkernel;
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void *generictrap;
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size_t trap_offset, trapsize;
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vm_offset_t trap;
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void *kmdp;
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char *env;
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register_t msr, scratch;
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@ -480,20 +481,6 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
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bcopy(&rfid_patch,&rfi_patch2,4);
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#endif
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/*
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* Copy a code snippet to restore 32-bit bridge mode
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* to the top of every non-generic trap handler
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*/
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trap_offset += (size_t)&restorebridgesize;
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bcopy(&restorebridge, (void *)EXC_RST, trap_offset);
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bcopy(&restorebridge, (void *)EXC_DSI, trap_offset);
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bcopy(&restorebridge, (void *)EXC_ALI, trap_offset);
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bcopy(&restorebridge, (void *)EXC_PGM, trap_offset);
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bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset);
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bcopy(&restorebridge, (void *)EXC_TRC, trap_offset);
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bcopy(&restorebridge, (void *)EXC_BPT, trap_offset);
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/*
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* Set the common trap entry point to the one that
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* knows to restore 32-bit operation on execution.
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@ -507,14 +494,35 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
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#else /* powerpc64 */
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cpu_features |= PPC_FEATURE_64;
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generictrap = &trapcode;
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/* Set TOC base so that the interrupt code can get at it */
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*((void **)TRAP_GENTRAP) = &trapcode2;
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*((register_t *)TRAP_TOCBASE) = toc;
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#endif
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trapsize = (size_t)&trapcodeend - (size_t)&trapcode;
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/*
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* Copy generic handler into every possible trap. Special cases will get
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* different ones in a minute.
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*/
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for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20)
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bcopy(generictrap, (void *)trap, trapsize);
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#ifndef __powerpc64__
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if (cpu_features & PPC_FEATURE_64) {
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/*
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* Copy a code snippet to restore 32-bit bridge mode
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* to the top of every non-generic trap handler
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*/
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trap_offset += (size_t)&restorebridgesize;
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bcopy(&restorebridge, (void *)EXC_RST, trap_offset);
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bcopy(&restorebridge, (void *)EXC_DSI, trap_offset);
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bcopy(&restorebridge, (void *)EXC_ALI, trap_offset);
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bcopy(&restorebridge, (void *)EXC_PGM, trap_offset);
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bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset);
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bcopy(&restorebridge, (void *)EXC_TRC, trap_offset);
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bcopy(&restorebridge, (void *)EXC_BPT, trap_offset);
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}
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#endif
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bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend -
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(size_t)&rstcode);
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@ -527,31 +535,20 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
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(size_t)&dblow);
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bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend -
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(size_t)&dblow);
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#else
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bcopy(generictrap, (void *)EXC_MCHK, trapsize);
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bcopy(generictrap, (void *)EXC_PGM, trapsize);
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bcopy(generictrap, (void *)EXC_TRC, trapsize);
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bcopy(generictrap, (void *)EXC_BPT, trapsize);
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#endif
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bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&aliend -
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(size_t)&alitrap);
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bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsiend -
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(size_t)&dsitrap);
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bcopy(generictrap, (void *)EXC_ISI, trapsize);
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#ifdef __powerpc64__
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/* Set TOC base so that the interrupt code can get at it */
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*((void **)TRAP_GENTRAP) = &trapcode2;
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*((register_t *)TRAP_TOCBASE) = toc;
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bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap);
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bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap);
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#endif
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bcopy(generictrap, (void *)EXC_EXI, trapsize);
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bcopy(generictrap, (void *)EXC_FPU, trapsize);
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bcopy(generictrap, (void *)EXC_DECR, trapsize);
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bcopy(generictrap, (void *)EXC_SC, trapsize);
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bcopy(generictrap, (void *)EXC_FPA, trapsize);
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bcopy(generictrap, (void *)EXC_VEC, trapsize);
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bcopy(generictrap, (void *)EXC_PERF, trapsize);
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bcopy(generictrap, (void *)EXC_VECAST_G4, trapsize);
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bcopy(generictrap, (void *)EXC_VECAST_G5, trapsize);
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#ifndef __powerpc64__
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#else
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/* G2-specific TLB miss helper handlers */
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bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize);
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bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize);
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