Initial device tree source (DTS) files for Marvell ARM systems:
o DB-88F5182 o DB-88F5281 o DB-88F6281 o DB-78100 o SheevaPlug This also includes device tree bindings definitions for some newly introduced nodes (mpp, gpio). Reviewed by: imp Sponsored by: The FreeBSD Foundation
This commit is contained in:
Rafal Jaworowski
parent
103de39de5
commit
13ced1d6a0
101
sys/boot/fdt/dts/bindings-gpio.txt
Normal file
101
sys/boot/fdt/dts/bindings-gpio.txt
Normal file
@ -0,0 +1,101 @@
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$FreeBSD$
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GPIO configuration.
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===================
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1. Properties for GPIO Controllers
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1.1 #gpio-cells
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Property: #gpio-cells
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Value type: <u32>
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Description: The #gpio-cells property defines the number of cells required
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to encode a gpio specifier.
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1.2 gpio-controller
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Property: gpio-controller
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Value type: <empty>
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Description: The presence of a gpio-controller property defines a node as a
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GPIO controller node.
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1.3 pin-count
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Property: pin-count
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Value type: <u32>
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Description: The pin-count property defines the number of GPIO pins.
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1.4 Example
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GPIO: gpio@10100 {
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#gpio-cells = <3>;
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compatible = "mrvl,gpio";
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reg = <0x10100 0x20>;
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gpio-controller;
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interrupts = <6 7 8 9>;
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interrupt-parent = <&PIC>;
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pin-count = <50>
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};
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2. Properties for GPIO consumer nodes.
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2.1 gpios
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Property: gpios
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Value type: <prop-encoded-array> encoded as arbitrary number of GPIO
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specifiers.
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Description: The gpios property of a device node defines the GPIO or GPIOs
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that are used by the device. The value of the gpios property
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consists of an arbitrary number of GPIO specifiers.
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The first cell of the GPIO specifier is phandle of the node's
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parent GPIO controller and remaining cells are defined by the
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binding describing the GPIO parent, typically include
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information like pin number, direction and various flags.
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Example:
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gpios = <&GPIO 0 1 0 /* GPIO[0]: IN, NONE */
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&GPIO 1 2 0>; /* GPIO[1]: OUT, NONE */
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3. "mrvl,gpio" controller GPIO specifier
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<phandle pin dir flags>
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pin: 0-MAX GPIO pin number.
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dir:
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1 IN Input direction.
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2 OUT Output direction.
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flags:
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0x0000---- IN_NONE
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0x0001---- IN_POL_LOW Polarity low (inverted input value.
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0x0002---- IN_IRQ_EDGE Interrupt, edge triggered.
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0x0004---- IN_IRQ_LEVEL Interrupt, level triggered.
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0x----0000 OUT_NONE
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0x----0001 OUT_BLINK Blink on the pin.
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0x----0002 OUT_OPEN_DRAIN Open drain output line.
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0x----0004 OUT_OPEN_SRC Open source output line.
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Example:
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gpios = <&GPIO 0 1 0x00000000 /* GPIO[0]: IN */
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&GPIO 1 2 0x00000000 /* GPIO[1]: OUT */
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&GPIO 2 1 0x00020000 /* GPIO[2]: IN, IRQ (edge) */
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&GPIO 3 1 0x00040000 /* GPIO[3]: IN, IRQ (level) */
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...
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&GPIO 10 2 0x00000001>; /* GPIO[10]: OUT, blink */
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50
sys/boot/fdt/dts/bindings-mpp.txt
Normal file
50
sys/boot/fdt/dts/bindings-mpp.txt
Normal file
@ -0,0 +1,50 @@
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$FreeBSD$
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* Multi purpose pin (MPP) configuration.
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Required properties:
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- pin-map : array of pin configurations. Each pin is defined by 2 cells,
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respectively: <pin> <function>. Pins not specified in the pin-map property
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are assumed to have default value of <function> = 0, which means GPIO.
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- pin : pin number.
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- function : function ID of the pin according to the assignment tables in
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User Manual. Each pin can have many possible functions depending on the
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MPP unit incarnation.
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- pin-count: number of the physical MPP connections on the SOC (depending on
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the model it can be 24-50, or possibly else in future devices).
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Example:
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mpp@10000 {
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#pin-cells = <2>;
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compatible = "mrvl,mpp";
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reg = <0x10000 0x34>;
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pin-count= <50>;
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pin-map = <
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0 1 /* MPP[0]: NF_IO[2] */
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1 1 /* MPP[1]: NF_IO[3] */
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2 1 /* MPP[2]: NF_IO[4] */
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3 1 /* MPP[3]: NF_IO[5] */
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4 1 /* MPP[4]: NF_IO[6] */
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5 1 /* MPP[5]: NF_IO[7] */
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6 1 /* MPP[6]: SYSRST_OUTn */
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7 2 /* MPP[7]: SPI_SCn */
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8 1 /* MPP[8]: TW_SDA */
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9 1 /* MPP[9]: TW_SCK */
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10 3 /* MPP[10]: UA0_TXD */
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11 3 /* MPP[11]: UA0_RXD */
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12 1 /* MPP[12]: SD_CLK */
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13 1 /* MPP[13]: SD_CMD */
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14 1 /* MPP[14]: SD_D[0] */
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15 1 /* MPP[15]: SD_D[1] */
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16 1 /* MPP[16]: SD_D[2] */
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17 1 /* MPP[17]: SD_D[3] */
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18 1 /* MPP[18]: NF_IO[0] */
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19 1 /* MPP[19]: NF_IO[1] */
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20 5 /* MPP[20]: SATA1_AC */
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21 5 >; /* MPP[21]: SATA0_AC */
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};
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315
sys/boot/fdt/dts/db78100.dts
Normal file
315
sys/boot/fdt/dts/db78100.dts
Normal file
@ -0,0 +1,315 @@
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/*
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* Copyright (c) 2010 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under sponsorship from
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* the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Marvell DB-78100 Device Tree Source.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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/ {
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model = "mrvl,DB-78100";
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compatible = "DB-78100-BP", "DB-78100-BP-A";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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serial0 = &serial0;
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serial1 = &serial1;
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mpp = &MPP;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "ARM,88FR571";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x4000>; // L1, 16K
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i-cache-size = <0x4000>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x20000000>; // 512M at 0x0
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};
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localbus@f1000000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "mrvl,lbc";
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win-count = <14>;
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/* This reflects CPU decode windows setup. */
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ranges = <0x0 0x0f 0xf9300000 0x00100000
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0x1 0x1e 0xfa000000 0x00100000
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0x2 0x1d 0xfa100000 0x02000000
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0x3 0x1b 0xfc100000 0x00000400>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x00100000>;
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bank-width = <2>;
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device-width = <1>;
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};
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led@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "led";
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reg = <0x1 0x0 0x00100000>;
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};
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nor@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x2 0x0 0x02000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x3 0x0 0x00100000>;
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bank-width = <2>;
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device-width = <1>;
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};
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};
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soc78100@f1000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0xf1000000 0x00100000>;
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bus-frequency = <0>;
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PIC: pic@20200 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x20200 0x3c>;
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compatible = "mrvl,pic";
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};
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timer@20300 {
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compatible = "mrvl,timer";
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reg = <0x20300 0x30>;
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interrupts = <8>;
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interrupt-parent = <&PIC>;
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mrvl,has-wdt;
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};
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MPP: mpp@10000 {
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#pin-cells = <2>;
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compatible = "mrvl,mpp";
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reg = <0x10000 0x34>;
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pin-count = <50>;
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pin-map = <
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0 2 /* MPP[0]: GE1_TXCLK */
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1 2 /* MPP[1]: GE1_TXCTL */
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2 2 /* MPP[2]: GE1_RXCTL */
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3 2 /* MPP[3]: GE1_RXCLK */
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4 2 /* MPP[4]: GE1_TXD[0] */
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5 2 /* MPP[5]: GE1_TXD[1] */
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6 2 /* MPP[6]: GE1_TXD[2] */
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7 2 /* MPP[7]: GE1_TXD[3] */
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8 2 /* MPP[8]: GE1_RXD[0] */
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9 2 /* MPP[9]: GE1_RXD[1] */
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10 2 /* MPP[10]: GE1_RXD[2] */
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11 2 /* MPP[11]: GE1_RXD[3] */
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13 3 /* MPP[13]: SYSRST_OUTn */
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14 3 /* MPP[14]: SATA1_ACTn */
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15 3 /* MPP[15]: SATA0_ACTn */
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16 4 /* MPP[16]: UA2_TXD */
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17 4 /* MPP[17]: UA2_RXD */
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18 3 /* MPP[18]: <UNKNOWN> */
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19 3 /* MPP[19]: <UNKNOWN> */
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20 3 /* MPP[20]: <UNKNOWN> */
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21 3 /* MPP[21]: <UNKNOWN> */
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22 4 /* MPP[22]: UA3_TXD */
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23 4 >; /* MPP[21]: UA3_RXD */
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};
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GPIO: gpio@10100 {
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#gpio-cells = <3>;
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compatible = "mrvl,gpio";
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reg = <0x10100 0x20>;
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gpio-controller;
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interrupts = <56 57 58 59>;
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interrupt-parent = <&PIC>;
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};
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rtc@10300 {
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compatible = "mrvl,rtc";
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reg = <0x10300 0x08>;
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};
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twsi@11000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,twsi";
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reg = <0x11000 0x20>;
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interrupts = <2>;
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interrupt-parent = <&PIC>;
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};
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twsi@11100 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,twsi";
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reg = <0x11100 0x20>;
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interrupts = <3>;
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interrupt-parent = <&PIC>;
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};
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enet0: ethernet@72000 {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "V2";
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compatible = "mrvl,ge";
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reg = <0x72000 0x2000>;
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ranges = <0x0 0x72000 0x2000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <41 42 43 40 70>;
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interrupt-parent = <&PIC>;
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phy-handle = <&phy0>;
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,mdio";
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phy0: ethernet-phy@0 {
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reg = <0x8>;
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};
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};
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};
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enet1: ethernet@76000 {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "V2";
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compatible = "mrvl,ge";
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reg = <0x76000 0x2000>;
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ranges = <0x0 0x76000 0x2000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <45 46 47 44 70>;
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interrupt-parent = <&PIC>;
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phy-handle = <&phy0>;
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,mdio";
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phy0: ethernet-phy@0 {
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reg = <0x9>;
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};
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};
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};
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serial0: serial@12000 {
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compatible = "ns16550";
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reg = <0x12000 0x20>;
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reg-shift = <2>;
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clock-frequency = <0>;
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interrupts = <12>;
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interrupt-parent = <&PIC>;
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};
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serial1: serial@12100 {
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compatible = "ns16550";
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reg = <0x12100 0x20>;
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reg-shift = <2>;
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clock-frequency = <0>;
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interrupts = <13>;
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interrupt-parent = <&PIC>;
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};
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usb@50000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x50000 0x1000>;
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interrupts = <72 16>;
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interrupt-parent = <&PIC>;
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};
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usb@51000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x51000 0x1000>;
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interrupts = <72 17>;
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interrupt-parent = <&PIC>;
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};
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usb@52000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x52000 0x1000>;
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interrupts = <72 18>;
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interrupt-parent = <&PIC>;
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};
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xor@60000 {
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compatible = "mrvl,xor";
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reg = <0x60000 0x1000>;
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interrupts = <22 23>;
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interrupt-parent = <&PIC>;
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};
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crypto@90000 {
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compatible = "mrvl,cesa";
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reg = <0x90000 0x10000>;
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interrupts = <19>;
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interrupt-parent = <&PIC>;
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};
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sata@a0000 {
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compatible = "mrvl,sata";
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reg = <0xa0000 0x6000>;
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interrupts = <26>;
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interrupt-parent = <&PIC>;
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};
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};
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sram@fd000000 {
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compatible = "mrvl,cesa-sram";
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reg = <0xfd000000 0x00100000>;
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};
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};
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223
sys/boot/fdt/dts/db88f5182.dts
Normal file
223
sys/boot/fdt/dts/db88f5182.dts
Normal file
@ -0,0 +1,223 @@
|
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/*
|
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* Copyright (c) 2010 The FreeBSD Foundation
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software was developed by Semihalf under sponsorship from
|
||||
* the FreeBSD Foundation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Marvell DB-88F5182 Device Tree Source.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "mrvl,DB-88F5182";
|
||||
compatible = "DB-88F5182-BP", "DB-88F5182-BP-A";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
mpp = &MPP;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "ARM,88FR531";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>; // 128M at 0x0
|
||||
};
|
||||
|
||||
localbus@f1000000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mrvl,lbc";
|
||||
|
||||
/* This reflects CPU decode windows setup. */
|
||||
ranges = <0x0 0x0f 0xf9300000 0x00100000
|
||||
0x1 0x1e 0xfa000000 0x00100000
|
||||
0x2 0x1d 0xfa100000 0x02000000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x00100000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
led@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "led";
|
||||
reg = <0x1 0x0 0x00100000>;
|
||||
};
|
||||
|
||||
nor@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x2 0x0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc88f5182@f1000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xf1000000 0x00100000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
PIC: pic@20200 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x20200 0x3c>;
|
||||
compatible = "mrvl,pic";
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "mrvl,timer";
|
||||
reg = <0x20300 0x30>;
|
||||
interrupts = <0>;
|
||||
interrupt-parent = <&PIC>;
|
||||
mrvl,has-wdt;
|
||||
};
|
||||
|
||||
MPP: mpp@10000 {
|
||||
#pin-cells = <2>;
|
||||
compatible = "mrvl,mpp";
|
||||
reg = <0x10000 0x54>;
|
||||
pin-count = <20>;
|
||||
pin-map = <
|
||||
0 3 /* MPP[0]: GPIO[0] */
|
||||
2 2 /* MPP[2]: PCI_REQn[3] */
|
||||
3 2 /* MPP[3]: PCI_GNTn[3] */
|
||||
4 2 /* MPP[4]: PCI_REQn[4] */
|
||||
5 2 /* MPP[5]: PCI_GNTn[4] */
|
||||
6 5 /* MPP[6]: SATA0_ACT */
|
||||
7 5 /* MPP[7]: SATA1_ACT */
|
||||
12 5 /* MPP[12]: SATA0_PRESENT */
|
||||
13 5 /* MPP[13]: SATA1_PRESENT */
|
||||
14 4 /* MPP[14]: NAND Flash REn[2] */
|
||||
15 4 /* MPP[15]: NAND Flash WEn[2] */
|
||||
16 0 /* MPP[16]: UA1_RXD */
|
||||
17 0 /* MPP[17]: UA1_TXD */
|
||||
18 0 /* MPP[18]: UA1_CTS */
|
||||
19 0 >; /* MPP[19]: UA1_RTS */
|
||||
};
|
||||
|
||||
GPIO: gpio@10100 {
|
||||
#gpio-cells = <3>;
|
||||
compatible = "mrvl,gpio";
|
||||
reg = <0x10100 0x20>;
|
||||
gpio-controller;
|
||||
interrupts = <6 7 8 9>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
twsi@11000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mrvl,twsi";
|
||||
reg = <0x11000 0x20>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
enet0: ethernet@72000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "V1";
|
||||
compatible = "mrvl,ge";
|
||||
reg = <0x72000 0x2000>;
|
||||
ranges = <0x0 0x72000 0x2000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <18 19 20 21 22>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
serial0: serial@12000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x12000 0x20>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <3>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
serial1: serial@12100 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x12100 0x20>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "mrvl,usb-ehci", "usb-ehci";
|
||||
reg = <0x50000 0x1000>;
|
||||
interrupts = <17 16>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
idma@60000 {
|
||||
compatible = "mrvl,idma";
|
||||
reg = <0x60000 0x1000>;
|
||||
interrupts = <24 25 26 27 23>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
sata@80000 {
|
||||
compatible = "mrvl,sata";
|
||||
reg = <0x80000 0x6000>;
|
||||
interrupts = <29>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
};
|
||||
227
sys/boot/fdt/dts/db88f5281.dts
Normal file
227
sys/boot/fdt/dts/db88f5281.dts
Normal file
@ -0,0 +1,227 @@
|
||||
/*
|
||||
* Copyright (c) 2010 The FreeBSD Foundation
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software was developed by Semihalf under sponsorship from
|
||||
* the FreeBSD Foundation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Marvell DB-88F5281 Device Tree Source.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "mrvl,DB-88F5281";
|
||||
compatible = "DB-88F5281-BP", "DB-88F5281-BP-A";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
mpp = &MPP;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "ARM,88FR531";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>; // 128M at 0x0
|
||||
};
|
||||
|
||||
localbus@f1000000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mrvl,lbc";
|
||||
|
||||
/* This reflects CPU decode windows setup. */
|
||||
ranges = <0x0 0x0f 0xf9300000 0x00100000
|
||||
0x1 0x1e 0xfa000000 0x00100000
|
||||
0x2 0x1d 0xfa100000 0x02000000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x00100000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
led@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "led";
|
||||
reg = <0x1 0x0 0x00100000>;
|
||||
};
|
||||
|
||||
nor@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x2 0x0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc88f5281@f1000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xf1000000 0x00100000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
PIC: pic@20200 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x20200 0x3c>;
|
||||
compatible = "mrvl,pic";
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "mrvl,timer";
|
||||
reg = <0x20300 0x30>;
|
||||
interrupts = <0>;
|
||||
interrupt-parent = <&PIC>;
|
||||
mrvl,has-wdt;
|
||||
};
|
||||
|
||||
MPP: mpp@10000 {
|
||||
#pin-cells = <2>;
|
||||
compatible = "mrvl,mpp";
|
||||
reg = <0x10000 0x54>;
|
||||
pin-count = <20>;
|
||||
pin-map = <
|
||||
0 3 /* MPP[0]: GPIO[0] */
|
||||
2 2 /* MPP[2]: PCI_REQn[3] */
|
||||
3 2 /* MPP[3]: PCI_GNTn[3] */
|
||||
4 2 /* MPP[4]: PCI_REQn[4] */
|
||||
5 2 /* MPP[5]: PCI_GNTn[4] */
|
||||
6 3 /* MPP[6]: <UNKNOWN> */
|
||||
7 3 /* MPP[7]: <UNKNOWN> */
|
||||
8 3 /* MPP[8]: <UNKNOWN> */
|
||||
9 3 /* MPP[9]: <UNKNOWN> */
|
||||
14 4 /* MPP[14]: NAND Flash REn[2] */
|
||||
15 4 /* MPP[15]: NAND Flash WEn[2] */
|
||||
16 0 /* MPP[16]: UA1_RXD */
|
||||
17 0 /* MPP[17]: UA1_TXD */
|
||||
18 0 /* MPP[18]: UA1_CTS */
|
||||
19 0 >; /* MPP[19]: UA1_RTS */
|
||||
};
|
||||
|
||||
GPIO: gpio@10100 {
|
||||
#gpio-cells = <3>;
|
||||
compatible = "mrvl,gpio";
|
||||
reg = <0x10100 0x20>;
|
||||
gpio-controller;
|
||||
interrupts = <6 7 8 9>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
twsi@11000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mrvl,twsi";
|
||||
reg = <0x11000 0x20>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
enet0: ethernet@72000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "V1";
|
||||
compatible = "mrvl,ge";
|
||||
reg = <0x72000 0x2000>;
|
||||
ranges = <0x0 0x72000 0x2000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <18 19 20 21 22>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mrvl,mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@12000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x12000 0x20>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <3>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
serial1: serial@12100 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x12100 0x20>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "mrvl,usb-ehci", "usb-ehci";
|
||||
reg = <0x50000 0x1000>;
|
||||
interrupts = <17 16>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
idma@60000 {
|
||||
compatible = "mrvl,idma";
|
||||
reg = <0x60000 0x1000>;
|
||||
interrupts = <24 25 26 27 23>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
};
|
||||
306
sys/boot/fdt/dts/db88f6281.dts
Normal file
306
sys/boot/fdt/dts/db88f6281.dts
Normal file
@ -0,0 +1,306 @@
|
||||
/*
|
||||
* Copyright (c) 2009-2010 The FreeBSD Foundation
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software was developed by Semihalf under sponsorship from
|
||||
* the FreeBSD Foundation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Marvell DB-88F6281 Device Tree Source.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "mrvl,DB-88F6281";
|
||||
compatible = "DB-88F6281-BP", "DB-88F6281-BP-A";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
mpp = &MPP;
|
||||
pci0 = &pci0;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
soc = &SOC;
|
||||
sram = &SRAM;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "ARM,88FR131";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x20000000>; // 512M at 0x0
|
||||
};
|
||||
|
||||
localbus@f1000000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mrvl,lbc";
|
||||
|
||||
/* This reflects CPU decode windows setup. */
|
||||
ranges = <0x0 0x0f 0xf9300000 0x00100000
|
||||
0x1 0x1e 0xfa000000 0x00100000
|
||||
0x2 0x1d 0xfa100000 0x02000000
|
||||
0x3 0x1b 0xfc100000 0x00000400>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x00100000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
led@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "led";
|
||||
reg = <0x1 0x0 0x00100000>;
|
||||
};
|
||||
|
||||
nor@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x2 0x0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x3 0x0 0x00100000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
SOC: soc88f6281@f1000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xf1000000 0x00100000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
PIC: pic@20200 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x20200 0x3c>;
|
||||
compatible = "mrvl,pic";
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "mrvl,timer";
|
||||
reg = <0x20300 0x30>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
mrvl,has-wdt;
|
||||
};
|
||||
|
||||
MPP: mpp@10000 {
|
||||
#pin-cells = <2>;
|
||||
compatible = "mrvl,mpp";
|
||||
reg = <0x10000 0x34>;
|
||||
pin-count = <50>;
|
||||
pin-map = <
|
||||
0 1 /* MPP[0]: NF_IO[2] */
|
||||
1 1 /* MPP[1]: NF_IO[3] */
|
||||
2 1 /* MPP[2]: NF_IO[4] */
|
||||
3 1 /* MPP[3]: NF_IO[5] */
|
||||
4 1 /* MPP[4]: NF_IO[6] */
|
||||
5 1 /* MPP[5]: NF_IO[7] */
|
||||
6 1 /* MPP[6]: SYSRST_OUTn */
|
||||
7 2 /* MPP[7]: SPI_SCn */
|
||||
8 1 /* MPP[8]: TW_SDA */
|
||||
9 1 /* MPP[9]: TW_SCK */
|
||||
10 3 /* MPP[10]: UA0_TXD */
|
||||
11 3 /* MPP[11]: UA0_RXD */
|
||||
12 1 /* MPP[12]: SD_CLK */
|
||||
13 1 /* MPP[13]: SD_CMD */
|
||||
14 1 /* MPP[14]: SD_D[0] */
|
||||
15 1 /* MPP[15]: SD_D[1] */
|
||||
16 1 /* MPP[16]: SD_D[2] */
|
||||
17 1 /* MPP[17]: SD_D[3] */
|
||||
18 1 /* MPP[18]: NF_IO[0] */
|
||||
19 1 /* MPP[19]: NF_IO[1] */
|
||||
20 5 /* MPP[20]: SATA1_AC */
|
||||
21 5 >; /* MPP[21]: SATA0_AC */
|
||||
};
|
||||
|
||||
GPIO: gpio@10100 {
|
||||
#gpio-cells = <3>;
|
||||
compatible = "mrvl,gpio";
|
||||
reg = <0x10100 0x20>;
|
||||
gpio-controller;
|
||||
interrupts = <35 36 37 38 39 40 41>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
rtc@10300 {
|
||||
compatible = "mrvl,rtc";
|
||||
reg = <0x10300 0x08>;
|
||||
};
|
||||
|
||||
twsi@11000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mrvl,twsi";
|
||||
reg = <0x11000 0x20>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
enet0: ethernet@72000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "V2";
|
||||
compatible = "mrvl,ge";
|
||||
reg = <0x72000 0x2000>;
|
||||
ranges = <0x0 0x72000 0x2000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <12 13 14 11 46>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mrvl,mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@12000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x12000 0x20>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
serial1: serial@12100 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x12100 0x20>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "mrvl,cesa";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <22>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "mrvl,usb-ehci", "usb-ehci";
|
||||
reg = <0x50000 0x1000>;
|
||||
interrupts = <48 19>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
xor@60000 {
|
||||
compatible = "mrvl,xor";
|
||||
reg = <0x60000 0x1000>;
|
||||
interrupts = <5 6 7 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
sata@80000 {
|
||||
compatible = "mrvl,sata";
|
||||
reg = <0x80000 0x6000>;
|
||||
interrupts = <21>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
SRAM: sram@fd000000 {
|
||||
compatible = "mrvl,cesa-sram";
|
||||
reg = <0xfd000000 0x00100000>;
|
||||
};
|
||||
|
||||
pci0: pcie@f1040000 {
|
||||
compatible = "mrvl,pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xf1040000 0x2000>;
|
||||
bus-range = <0 255>;
|
||||
ranges = <0x02000000 0x0 0xf1300000 0xf1300000 0x0 0x04000000
|
||||
0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupts = <44>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x1 */
|
||||
0x0800 0x0 0x0 0x1 &PIC 0x9
|
||||
0x0800 0x0 0x0 0x2 &PIC 0x9
|
||||
0x0800 0x0 0x0 0x3 &PIC 0x9
|
||||
0x0800 0x0 0x0 0x4 &PIC 0x9
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0xf1300000
|
||||
0x02000000 0x0 0xf1300000
|
||||
0x0 0x04000000
|
||||
|
||||
0x01000000 0x0 0x0
|
||||
0x01000000 0x0 0x0
|
||||
0x0 0x00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
265
sys/boot/fdt/dts/sheevaplug.dts
Normal file
265
sys/boot/fdt/dts/sheevaplug.dts
Normal file
@ -0,0 +1,265 @@
|
||||
/*
|
||||
* Copyright (c) 2010 The FreeBSD Foundation
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software was developed by Semihalf under sponsorship from
|
||||
* the FreeBSD Foundation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Marvell SheevaPlug Device Tree Source.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "mrvl,SheevaPlug";
|
||||
compatible = "SheevaPlug";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
mpp = &MPP;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
soc = &SOC;
|
||||
sram = &SRAM;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "ARM,88FR131";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x20000000>; // 512M at 0x0
|
||||
};
|
||||
|
||||
localbus@f1000000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mrvl,lbc";
|
||||
|
||||
/* This reflects CPU decode windows setup. */
|
||||
ranges = <0x0 0x0f 0xf9300000 0x00100000
|
||||
0x1 0x1e 0xfa000000 0x00100000
|
||||
0x2 0x1d 0xfa100000 0x02000000
|
||||
0x3 0x1b 0xfc100000 0x00000400>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x00100000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
led@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "led";
|
||||
reg = <0x1 0x0 0x00100000>;
|
||||
};
|
||||
|
||||
nor@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x2 0x0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@3,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x3 0x0 0x00100000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
SOC: soc88f6281@f1000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xf1000000 0x00100000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
PIC: pic@20200 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x20200 0x3c>;
|
||||
compatible = "mrvl,pic";
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "mrvl,timer";
|
||||
reg = <0x20300 0x30>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
mrvl,has-wdt;
|
||||
};
|
||||
|
||||
MPP: mpp@10000 {
|
||||
#pin-cells = <2>;
|
||||
compatible = "mrvl,mpp";
|
||||
reg = <0x10000 0x34>;
|
||||
pin-count = <50>;
|
||||
pin-map = <
|
||||
0 1 /* MPP[0]: NF_IO[2] */
|
||||
1 1 /* MPP[1]: NF_IO[3] */
|
||||
2 1 /* MPP[2]: NF_IO[4] */
|
||||
3 1 /* MPP[3]: NF_IO[5] */
|
||||
4 1 /* MPP[4]: NF_IO[6] */
|
||||
5 1 /* MPP[5]: NF_IO[7] */
|
||||
6 1 /* MPP[6]: SYSRST_OUTn */
|
||||
8 2 /* MPP[8]: UA0_RTS */
|
||||
9 2 /* MPP[9]: UA0_CTS */
|
||||
10 3 /* MPP[10]: UA0_TXD */
|
||||
11 3 /* MPP[11]: UA0_RXD */
|
||||
12 1 /* MPP[12]: SD_CLK */
|
||||
13 1 /* MPP[13]: SD_CMD */
|
||||
14 1 /* MPP[14]: SD_D[0] */
|
||||
15 1 /* MPP[15]: SD_D[1] */
|
||||
16 1 /* MPP[16]: SD_D[2] */
|
||||
17 1 /* MPP[17]: SD_D[3] */
|
||||
18 1 /* MPP[18]: NF_IO[0] */
|
||||
19 1 /* MPP[19]: NF_IO[1] */
|
||||
29 1 >; /* MPP[29]: TSMP[9] */
|
||||
};
|
||||
|
||||
GPIO: gpio@10100 {
|
||||
#gpio-cells = <3>;
|
||||
compatible = "mrvl,gpio";
|
||||
reg = <0x10100 0x20>;
|
||||
gpio-controller;
|
||||
interrupts = <35 36 37 38 39 40 41>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
rtc@10300 {
|
||||
compatible = "mrvl,rtc";
|
||||
reg = <0x10300 0x08>;
|
||||
};
|
||||
|
||||
twsi@11000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mrvl,twsi";
|
||||
reg = <0x11000 0x20>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
enet0: ethernet@72000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "V2";
|
||||
compatible = "mrvl,ge";
|
||||
reg = <0x72000 0x2000>;
|
||||
ranges = <0x0 0x72000 0x2000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <12 13 14 11 46>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mrvl,mdio";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@12000 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x12000 0x20>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
serial1: serial@12100 {
|
||||
compatible = "ns16550";
|
||||
reg = <0x12100 0x20>;
|
||||
reg-shift = <2>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "mrvl,cesa";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <22>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "mrvl,usb-ehci", "usb-ehci";
|
||||
reg = <0x50000 0x1000>;
|
||||
interrupts = <48 19>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
xor@60000 {
|
||||
compatible = "mrvl,xor";
|
||||
reg = <0x60000 0x1000>;
|
||||
interrupts = <5 6 7 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
SRAM: sram@fd000000 {
|
||||
compatible = "mrvl,cesa-sram";
|
||||
reg = <0xfd000000 0x00100000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdin = "serial0";
|
||||
stdout = "serial0";
|
||||
};
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user