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Put in offset definitions for FPM and FBM registers, plus just enough

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bits defined so we can reset them.
This commit is contained in:
Matt Jacob 2001-01-15 18:37:14 +00:00
parent df1590c05d
commit 144ff11903
1 changed files with 17 additions and 0 deletions
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17
sys/dev/isp/ispreg.h
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@ -349,6 +349,19 @@
#define MAX_MAILBOX 8
/*
* Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00).
* NB: The RISC processor must be paused and the appropriate register
* bank selected via BIU2100_CSR bits.
*/
#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96)
#define FPM_SOFT_RESET 0x0100
#define FBM_CMD (BIU_BLOCK + 0xB8)
#define FBMCMD_FIFO_RESET_ALL 0xA000
/*
* SXP Block Register Offsets
*/
@ -601,6 +614,10 @@
#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */
#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */
#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */
#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /*
* Disable RISC pause on FPM
* parity error.
*/
#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */
#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */
#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */