Add a couple of small fixes from the AMD folks.
- max tex height is 8192 - increment src/dst by the full transfer amount MFC after: 3 days
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199e206513
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@ -1734,6 +1734,8 @@ r600_blit_copy(struct drm_device *dev,
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if (!src_x && !dst_x) {
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h = (cur_size / max_bytes);
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if (h > 8192)
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h = 8192;
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if (h == 0)
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h = 1;
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else
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@ -1805,8 +1807,8 @@ r600_blit_copy(struct drm_device *dev,
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vb += 12;
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dev_priv->blit_vb->used += 12 * 4;
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src_gpu_addr += cur_size;
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dst_gpu_addr += cur_size;
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src_gpu_addr += cur_size * h;
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dst_gpu_addr += cur_size * h;
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size_bytes -= cur_size * h;
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}
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} else {
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@ -1822,6 +1824,8 @@ r600_blit_copy(struct drm_device *dev,
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if (!src_x && !dst_x) {
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h = (cur_size / max_bytes);
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if (h > 8192)
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h = 8192;
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if (h == 0)
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h = 1;
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else
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@ -1894,8 +1898,8 @@ r600_blit_copy(struct drm_device *dev,
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vb += 12;
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dev_priv->blit_vb->used += 12 * 4;
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src_gpu_addr += cur_size;
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dst_gpu_addr += cur_size;
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src_gpu_addr += cur_size * h;
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dst_gpu_addr += cur_size * h;
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size_bytes -= cur_size * h;
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}
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}
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