nctgpio: improve performance (latency) of operation
This change consists of two parts. First, nctgpio now supports hardware access via an I/O port window if it's configured by firmware. For instance, PC Engines firmware v4.10.0.2 does that. This is faster than going through the Super I/O configuration registers. Second, nctgpio now caches values of bits that it controls. For example, the driver does not need to access the hardware to determine if a pin is an output or an input, or a state of an output. Also, the driver makes use of the fact that the hardware preserves an output state of a pin accross a switch to the input mode and back. With this change I am able to use the 1-Wire bus over nctgpio whereas previously the driver introduced too much latency to be compliant with the relatively strict protocol timings. superio0: <Nuvoton NCT5104D/NCT6102D/NCT6106D (rev. B+)> at port 0x2e-0x2f on isa0 gpio1: <Nuvoton GPIO controller> at GPIO ldn 0x07 on superio0 pcib0: allocated type 4 (0x220-0x226) for rid 0 of gpio1 gpiobus1: <GPIO bus> on gpio1 owc0: <GPIO attached one-wire bus> at pin 4 on gpiobus1 ow0: <1 Wire Bus> on owc0 ow0: romid 28:b2:9e:45:92:10:02:34: no driver ow_temp0: <Advanced One Wire Temperature> romid 28:b2:9e:45:92:10:02:34 on ow0 MFC after: 4 weeks
This commit is contained in:
Andriy Gapon
parent
1de9724e55
commit
155514eacf
@ -69,21 +69,49 @@
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#define NCT_LDF_GPIO0_OUTCFG 0xe0
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#define NCT_LDF_GPIO1_OUTCFG 0xe1
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/* Direct I/O port access. */
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#define NCT_IO_GSR 0
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#define NCT_IO_IOR 1
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#define NCT_IO_DAT 2
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#define NCT_IO_INV 3
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#define NCT_MAX_PIN 15
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#define NCT_IS_VALID_PIN(_p) ((_p) >= 0 && (_p) <= NCT_MAX_PIN)
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#define NCT_PIN_BIT(_p) (1 << ((_p) % 8))
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#define NCT_PIN_BIT(_p) (1 << ((_p) & 7))
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#define NCT_GPIO_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
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GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \
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GPIO_PIN_INVIN | GPIO_PIN_INVOUT)
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/*
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* Note that the values are important.
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* They match actual register offsets.
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*/
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typedef enum {
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REG_IOR = 0,
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REG_DAT = 1,
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REG_INV = 2,
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} reg_t;
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struct nct_softc {
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device_t dev;
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device_t dev_f;
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device_t busdev;
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struct mtx mtx;
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struct resource *iores;
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int iorid;
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int curgrp;
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struct {
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/* direction, 1: pin is input */
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uint8_t ior[2];
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/* output value */
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uint8_t out[2];
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/* whether out is valid */
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uint8_t out_known[2];
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/* inversion, 1: pin is inverted */
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uint8_t inv[2];
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} cache;
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struct gpio_pin pins[NCT_MAX_PIN + 1];
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};
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@ -113,97 +141,142 @@ struct nuvoton_vendor_device_id {
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},
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};
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/*
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* Get the GPIO Input/Output register address
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* for a pin.
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*/
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static uint8_t
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nct_ior_addr(uint32_t pin_num)
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static void
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nct_io_set_group(struct nct_softc *sc, int group)
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{
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uint8_t addr;
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addr = NCT_LD7_GPIO0_IOR;
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if (pin_num > 7)
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addr = NCT_LD7_GPIO1_IOR;
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GPIO_ASSERT_LOCKED(sc);
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if (group != sc->curgrp) {
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bus_write_1(sc->iores, NCT_IO_GSR, group);
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sc->curgrp = group;
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}
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}
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return (addr);
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static uint8_t
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nct_io_read(struct nct_softc *sc, int group, uint8_t reg)
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{
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nct_io_set_group(sc, group);
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return (bus_read_1(sc->iores, reg));
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}
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static void
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nct_io_write(struct nct_softc *sc, int group, uint8_t reg, uint8_t val)
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{
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nct_io_set_group(sc, group);
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return (bus_write_1(sc->iores, reg, val));
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}
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static uint8_t
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nct_get_ioreg(struct nct_softc *sc, reg_t reg, int group)
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{
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uint8_t ioreg;
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if (sc->iores != NULL)
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ioreg = NCT_IO_IOR + reg;
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else if (group == 0)
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ioreg = NCT_LD7_GPIO0_IOR + reg;
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else
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ioreg = NCT_LD7_GPIO1_IOR + reg;
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return (ioreg);
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}
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static uint8_t
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nct_read_reg(struct nct_softc *sc, reg_t reg, int group)
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{
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uint8_t ioreg;
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uint8_t val;
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ioreg = nct_get_ioreg(sc, reg, group);
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if (sc->iores != NULL)
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val = nct_io_read(sc, group, ioreg);
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else
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val = superio_read(sc->dev, ioreg);
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return (val);
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}
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#define GET_BIT(v, b) (((v) >> (b)) & 1)
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static bool
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nct_get_pin_reg(struct nct_softc *sc, reg_t reg, uint32_t pin_num)
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{
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uint8_t bit;
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uint8_t group;
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uint8_t val;
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KASSERT(NCT_IS_VALID_PIN(pin_num), ("%s: invalid pin number %d",
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__func__, pin_num));
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group = pin_num >> 3;
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bit = pin_num & 7;
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val = nct_read_reg(sc, reg, group);
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return (GET_BIT(val, bit));
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}
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static int
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nct_get_pin_cache(struct nct_softc *sc, uint32_t pin_num, uint8_t *cache)
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{
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uint8_t bit;
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uint8_t group;
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uint8_t val;
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KASSERT(NCT_IS_VALID_PIN(pin_num), ("%s: invalid pin number %d",
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__func__, pin_num));
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group = pin_num >> 3;
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bit = pin_num & 7;
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val = cache[group];
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return (GET_BIT(val, bit));
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}
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static void
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nct_write_reg(struct nct_softc *sc, reg_t reg, int group, uint8_t val)
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{
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uint8_t ioreg;
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ioreg = nct_get_ioreg(sc, reg, group);
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if (sc->iores != NULL)
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nct_io_write(sc, group, ioreg, val);
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else
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superio_write(sc->dev, ioreg, val);
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}
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static void
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nct_set_pin_reg(struct nct_softc *sc, reg_t reg, uint32_t pin_num, bool val)
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{
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uint8_t *cache;
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uint8_t bit;
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uint8_t bitval;
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uint8_t group;
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uint8_t mask;
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KASSERT(NCT_IS_VALID_PIN(pin_num),
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("%s: invalid pin number %d", __func__, pin_num));
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KASSERT(reg == REG_IOR || reg == REG_INV,
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("%s: unsupported register %d", __func__, reg));
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group = pin_num >> 3;
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bit = pin_num & 7;
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mask = (uint8_t)1 << bit;
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bitval = (uint8_t)val << bit;
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if (reg == REG_IOR)
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cache = &sc->cache.ior[group];
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else
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cache = &sc->cache.inv[group];
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if ((*cache & mask) == bitval)
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return;
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*cache &= ~mask;
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*cache |= bitval;
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nct_write_reg(sc, reg, group, *cache);
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}
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/*
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* Get the GPIO Data register address for a pin.
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*/
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static uint8_t
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nct_dat_addr(uint32_t pin_num)
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{
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uint8_t addr;
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addr = NCT_LD7_GPIO0_DAT;
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if (pin_num > 7)
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addr = NCT_LD7_GPIO1_DAT;
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return (addr);
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}
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/*
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* Get the GPIO Inversion register address
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* for a pin.
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*/
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static uint8_t
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nct_inv_addr(uint32_t pin_num)
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{
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uint8_t addr;
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addr = NCT_LD7_GPIO0_INV;
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if (pin_num > 7)
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addr = NCT_LD7_GPIO1_INV;
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return (addr);
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}
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/*
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* Get the GPIO Output Configuration/Mode
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* register address for a pin.
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*/
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static uint8_t
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nct_outcfg_addr(uint32_t pin_num)
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{
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uint8_t addr;
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addr = NCT_LDF_GPIO0_OUTCFG;
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if (pin_num > 7)
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addr = NCT_LDF_GPIO1_OUTCFG;
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return (addr);
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}
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/*
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* Set a pin to output mode.
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* Set a pin to input (val is true) or output (val is false) mode.
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*/
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static void
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nct_set_pin_is_output(struct nct_softc *sc, uint32_t pin_num)
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nct_set_pin_input(struct nct_softc *sc, uint32_t pin_num, bool val)
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{
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uint8_t reg;
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uint8_t ior;
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reg = nct_ior_addr(pin_num);
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ior = superio_read(sc->dev, reg);
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ior &= ~(NCT_PIN_BIT(pin_num));
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superio_write(sc->dev, reg, ior);
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}
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/*
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* Set a pin to input mode.
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*/
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static void
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nct_set_pin_is_input(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t ior;
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reg = nct_ior_addr(pin_num);
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ior = superio_read(sc->dev, reg);
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ior |= NCT_PIN_BIT(pin_num);
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superio_write(sc->dev, reg, ior);
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nct_set_pin_reg(sc, REG_IOR, pin_num, val);
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}
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/*
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@ -212,80 +285,98 @@ nct_set_pin_is_input(struct nct_softc *sc, uint32_t pin_num)
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static bool
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nct_pin_is_input(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t ior;
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reg = nct_ior_addr(pin_num);
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ior = superio_read(sc->dev, reg);
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return (ior & NCT_PIN_BIT(pin_num));
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return (nct_get_pin_cache(sc, pin_num, sc->cache.ior));
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}
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/*
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* Write a value to an output pin.
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* Set a pin to inverted (val is true) or normal (val is false) mode.
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*/
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static void
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nct_write_pin(struct nct_softc *sc, uint32_t pin_num, uint8_t data)
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nct_set_pin_inverted(struct nct_softc *sc, uint32_t pin_num, bool val)
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{
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uint8_t reg;
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uint8_t value;
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reg = nct_dat_addr(pin_num);
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value = superio_read(sc->dev, reg);
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if (data)
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value |= NCT_PIN_BIT(pin_num);
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else
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value &= ~(NCT_PIN_BIT(pin_num));
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superio_write(sc->dev, reg, value);
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}
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static bool
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nct_read_pin(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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reg = nct_dat_addr(pin_num);
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return (superio_read(sc->dev, reg) & NCT_PIN_BIT(pin_num));
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}
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static void
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nct_set_pin_is_inverted(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t inv;
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reg = nct_inv_addr(pin_num);
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inv = superio_read(sc->dev, reg);
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inv |= (NCT_PIN_BIT(pin_num));
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superio_write(sc->dev, reg, inv);
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}
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static void
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nct_set_pin_not_inverted(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t inv;
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reg = nct_inv_addr(pin_num);
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inv = superio_read(sc->dev, reg);
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inv &= ~(NCT_PIN_BIT(pin_num));
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superio_write(sc->dev, reg, inv);
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nct_set_pin_reg(sc, REG_INV, pin_num, val);
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}
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static bool
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nct_pin_is_inverted(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t reg;
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uint8_t inv;
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reg = nct_inv_addr(pin_num);
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inv = superio_read(sc->dev, reg);
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return (inv & NCT_PIN_BIT(pin_num));
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return (nct_get_pin_cache(sc, pin_num, sc->cache.inv));
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}
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/*
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* Write a value to an output pin.
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* NB: the hardware remembers last output value across switching from
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* output mode to input mode and back.
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* Writes to a pin in input mode are not allowed here as they cannot
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* have any effect and would corrupt the output value cache.
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*/
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static void
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nct_write_pin(struct nct_softc *sc, uint32_t pin_num, bool val)
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{
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uint8_t bit;
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uint8_t group;
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KASSERT(!nct_pin_is_input(sc, pin_num), ("attempt to write input pin"));
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group = pin_num >> 3;
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bit = pin_num & 7;
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if (GET_BIT(sc->cache.out_known[group], bit) &&
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GET_BIT(sc->cache.out[group], bit) == val) {
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/* The pin is already in requested state. */
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return;
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}
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sc->cache.out_known[group] |= 1 << bit;
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if (val)
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sc->cache.out[group] |= 1 << bit;
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else
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sc->cache.out[group] &= ~(1 << bit);
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nct_write_reg(sc, REG_DAT, group, sc->cache.out[group]);
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}
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/*
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* NB: state of an input pin cannot be cached, of course.
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* For an output we can either take the value from the cache if it's valid
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* or read the state from the hadrware and cache it.
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*/
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static bool
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nct_read_pin(struct nct_softc *sc, uint32_t pin_num)
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{
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uint8_t bit;
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uint8_t group;
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bool val;
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if (nct_pin_is_input(sc, pin_num))
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return (nct_get_pin_reg(sc, REG_DAT, pin_num));
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group = pin_num >> 3;
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bit = pin_num & 7;
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if (GET_BIT(sc->cache.out_known[group], bit))
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return (GET_BIT(sc->cache.out[group], bit));
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val = nct_get_pin_reg(sc, REG_DAT, pin_num);
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sc->cache.out_known[group] |= 1 << bit;
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if (val)
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sc->cache.out[group] |= 1 << bit;
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else
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sc->cache.out[group] &= ~(1 << bit);
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return (val);
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}
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static uint8_t
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nct_outcfg_addr(uint32_t pin_num)
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{
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KASSERT(NCT_IS_VALID_PIN(pin_num), ("%s: invalid pin number %d",
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__func__, pin_num));
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if ((pin_num >> 3) == 0)
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return (NCT_LDF_GPIO0_OUTCFG);
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else
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return (NCT_LDF_GPIO1_OUTCFG);
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}
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/*
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* NB: PP/OD can be configured only via configuration registers.
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* Also, the registers are in a different logical device.
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* So, this is a special case. No caching too.
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*/
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static void
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nct_set_pin_opendrain(struct nct_softc *sc, uint32_t pin_num)
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{
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@ -353,6 +444,9 @@ static int
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nct_attach(device_t dev)
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{
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struct nct_softc *sc;
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device_t dev_8;
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uint16_t iobase;
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int err;
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int i;
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sc = device_get_softc(dev);
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@ -364,12 +458,67 @@ nct_attach(device_t dev)
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return (ENXIO);
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}
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/*
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* As strange as it may seem, I/O port base is configured in the
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* Logical Device 8 which is primarily used for WDT, but also plays
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* a role in GPIO configuration.
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*/
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iobase = 0;
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dev_8 = superio_find_dev(device_get_parent(dev), SUPERIO_DEV_WDT, 8);
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if (dev_8 != NULL)
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iobase = superio_get_iobase(dev_8);
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if (iobase != 0 && iobase != 0xffff) {
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sc->curgrp = -1;
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sc->iorid = 0;
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err = bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid,
|
||||
iobase, 7);
|
||||
if (err == 0) {
|
||||
sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
|
||||
&sc->iorid, RF_ACTIVE);
|
||||
if (sc->iores == NULL) {
|
||||
device_printf(dev, "can't map i/o space, "
|
||||
"iobase=0x%04x\n", iobase);
|
||||
}
|
||||
} else {
|
||||
device_printf(dev,
|
||||
"failed to set io port resource at 0x%x\n", iobase);
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable gpio0 and gpio1. */
|
||||
superio_dev_enable(dev, 0x03);
|
||||
|
||||
GPIO_LOCK_INIT(sc);
|
||||
GPIO_LOCK(sc);
|
||||
|
||||
sc->cache.inv[0] = nct_read_reg(sc, REG_INV, 0);
|
||||
sc->cache.inv[1] = nct_read_reg(sc, REG_INV, 1);
|
||||
sc->cache.ior[0] = nct_read_reg(sc, REG_IOR, 0);
|
||||
sc->cache.ior[1] = nct_read_reg(sc, REG_IOR, 1);
|
||||
|
||||
/*
|
||||
* Caching input values is meaningless as an input can be changed at any
|
||||
* time by an external agent. But outputs are controlled by this
|
||||
* driver, so it can cache their state. Also, the hardware remembers
|
||||
* the output state of a pin when the pin is switched to input mode and
|
||||
* then back to output mode. So, the cache stays valid.
|
||||
* The only problem is with pins that are in input mode at the attach
|
||||
* time. For them the output state is not known until it is set by the
|
||||
* driver for the first time.
|
||||
* 'out' and 'out_known' bits form a tri-state output cache:
|
||||
* |-----+-----------+---------|
|
||||
* | out | out_known | cache |
|
||||
* |-----+-----------+---------|
|
||||
* | X | 0 | invalid |
|
||||
* | 0 | 1 | 0 |
|
||||
* | 1 | 1 | 1 |
|
||||
* |-----+-----------+---------|
|
||||
*/
|
||||
sc->cache.out[0] = nct_read_reg(sc, REG_DAT, 0);
|
||||
sc->cache.out[1] = nct_read_reg(sc, REG_DAT, 1);
|
||||
sc->cache.out_known[0] = ~sc->cache.ior[0];
|
||||
sc->cache.out_known[1] = ~sc->cache.ior[1];
|
||||
|
||||
for (i = 0; i <= NCT_MAX_PIN; i++) {
|
||||
struct gpio_pin *pin;
|
||||
|
||||
@ -398,7 +547,6 @@ nct_attach(device_t dev)
|
||||
|
||||
sc->busdev = gpiobus_attach_bus(dev);
|
||||
if (sc->busdev == NULL) {
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK_DESTROY(sc);
|
||||
return (ENXIO);
|
||||
}
|
||||
@ -414,6 +562,8 @@ nct_detach(device_t dev)
|
||||
sc = device_get_softc(dev);
|
||||
gpiobus_detach_bus(dev);
|
||||
|
||||
if (sc->iores != NULL)
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, sc->iorid, sc->iores);
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK_DESTROY(sc);
|
||||
|
||||
@ -447,8 +597,11 @@ nct_gpio_pin_set(device_t dev, uint32_t pin_num, uint32_t pin_value)
|
||||
return (EINVAL);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
nct_write_pin(sc, pin_num, pin_value);
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
@ -483,6 +636,10 @@ nct_gpio_pin_toggle(device_t dev, uint32_t pin_num)
|
||||
sc = device_get_softc(dev);
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
if (nct_read_pin(sc, pin_num))
|
||||
nct_write_pin(sc, pin_num, 0);
|
||||
else
|
||||
@ -558,53 +715,41 @@ nct_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
|
||||
if ((flags & pin->gp_caps) != flags)
|
||||
return (EINVAL);
|
||||
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
|
||||
if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) ==
|
||||
(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (flags & GPIO_PIN_INPUT)
|
||||
nct_set_pin_is_input(sc, pin_num);
|
||||
else
|
||||
nct_set_pin_is_output(sc, pin_num);
|
||||
if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) ==
|
||||
(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
|
||||
return (EINVAL);
|
||||
}
|
||||
if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) ==
|
||||
(GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) {
|
||||
return (EINVAL);
|
||||
}
|
||||
if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) ==
|
||||
(GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) {
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) {
|
||||
if (flags & GPIO_PIN_INPUT) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) ==
|
||||
(GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
GPIO_ASSERT_UNLOCKED(sc);
|
||||
GPIO_LOCK(sc);
|
||||
if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) != 0) {
|
||||
nct_set_pin_input(sc, pin_num, (flags & GPIO_PIN_INPUT) != 0);
|
||||
pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
|
||||
pin->gp_flags |= flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
|
||||
}
|
||||
if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) != 0) {
|
||||
nct_set_pin_inverted(sc, pin_num,
|
||||
(flags & GPIO_PIN_INVIN) != 0);
|
||||
pin->gp_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
|
||||
pin->gp_flags |= flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
|
||||
}
|
||||
if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) != 0) {
|
||||
if (flags & GPIO_PIN_OPENDRAIN)
|
||||
nct_set_pin_opendrain(sc, pin_num);
|
||||
else
|
||||
nct_set_pin_pushpull(sc, pin_num);
|
||||
pin->gp_flags &= ~(GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL);
|
||||
pin->gp_flags |=
|
||||
flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL);
|
||||
}
|
||||
|
||||
if (flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) {
|
||||
if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) !=
|
||||
(GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) {
|
||||
GPIO_UNLOCK(sc);
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if (flags & GPIO_PIN_INVIN)
|
||||
nct_set_pin_is_inverted(sc, pin_num);
|
||||
else
|
||||
nct_set_pin_not_inverted(sc, pin_num);
|
||||
}
|
||||
|
||||
pin->gp_flags = flags;
|
||||
GPIO_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user