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Correct capitalization of "Hz" in user-visible text (manpages, printf(),

Browse Source 
etc).

MFC after:	3 days
This commit is contained in:
Gavin Atkinson 2012-02-28 13:19:34 +00:00
parent 935921eac7
commit 1748d1e513
9 changed files with 14 additions and 14 deletions
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4
sbin/ifconfig/ifconfig.8
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@ -1036,7 +1036,7 @@ Enable Dynamic Frequency Selection (DFS) as specified in 802.11h.
DFS embodies several facilities including detection of overlapping
radar signals, dynamic transmit power control, and channel selection
according to a least-congested criteria.
DFS support is mandatory for some 5Ghz frequencies in certain
DFS support is mandatory for some 5GHz frequencies in certain
locales (e.g. ETSI).
By default DFS is enabled according to the regulatory definitions
specified in /etc/regdomain.xml and the current country code, regdomain,
@ -1091,7 +1091,7 @@ By default DTIM is 1 (i.e., DTIM occurs at each beacon).
.It Cm quiet
Enable the use of quiet IE. Hostap will use this to silent other
stations to reduce interference for radar detection when
operating on 5Ghz frequency and doth support is enabled.
operating on 5GHz frequency and doth support is enabled.
Use
.Fl quiet
to disable this functionality.

2
sbin/ipfw/ipfw.8
View File

@ -2235,7 +2235,7 @@ specifies the scheduling algorithm to use.
is just a FIFO scheduler (which means that all packets
are stored in the same queue as they arrive to the scheduler).
FIFO has O(1) per-packet time complexity, with very low
constants (estimate 60-80ns on a 2Ghz desktop machine)
constants (estimate 60-80ns on a 2GHz desktop machine)
but gives no service guarantees.
.It Cm wf2qp
implements the WF2Q+ algorithm, which is a Weighted Fair Queueing

4
share/man/man4/ath.4
View File

@ -95,8 +95,8 @@ with transmit speeds appropriate to each.
AR5416-class devices are capable of 802.11n operation
but are supported only in legacy modes (802.11a, 11b, 11g).
Most chips also support an Atheros Turbo Mode (TM) that operates in
the 5Ghz frequency range with 2x the transmit speeds.
Some chips also support Turbo mode in the 2.4Ghz range with 802.11g
the 5GHz frequency range with 2x the transmit speeds.
Some chips also support Turbo mode in the 2.4GHz range with 802.11g
though this support is not presently available due to regulatory requirements.
(Note that Turbo modes are, however,
only interoperable with other Atheros-based devices.)

2
share/man/man4/net80211.4
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@ -280,7 +280,7 @@ Return whether or not Dynamic Frequency Selection (DFS) is enabled in
DFS embodies several facilities including detection of overlapping
radar signals, dynamic transmit power control, and channel selection
according to a least-congested criteria.
DFS support is mandatory for some 5Ghz frequencies in certain
DFS support is mandatory for some 5GHz frequencies in certain
locales (e.g. ETSI).
By default DFS is enabled according to the regulatory definitions
and the current country code, regdomain, and channel.

4
sys/conf/NOTES
View File

@ -2417,11 +2417,11 @@ device cmx
# or
# options BROOKTREE_SYSTEM_DEFAULT=BROOKTREE_NTSC
# Specifies the default video capture mode.
# This is required for Dual Crystal (28&35Mhz) boards where PAL is used
# This is required for Dual Crystal (28&35MHz) boards where PAL is used
# to prevent hangs during initialization, e.g. VideoLogic Captivator PCI.
#
# options BKTR_USE_PLL
# This is required for PAL or SECAM boards with a 28Mhz crystal and no 35Mhz
# This is required for PAL or SECAM boards with a 28MHz crystal and no 35MHz
# crystal, e.g. some new Bt878 cards.
#
# options BKTR_GPIO_ACCESS

2
sys/dev/ath/if_ath_sysctl.c
View File

@ -912,7 +912,7 @@ ath_sysctl_hal_attach(struct ath_softc *sc)
sc->sc_ah->ah_config.ah_ar5416_biasadj = 0;
SYSCTL_ADD_INT(ctx, child, OID_AUTO, "ar5416_biasadj", CTLFLAG_RW,
&sc->sc_ah->ah_config.ah_ar5416_biasadj, 0,
"Enable 2ghz AR5416 direction sensitivity bias adjust");
"Enable 2GHz AR5416 direction sensitivity bias adjust");
sc->sc_ah->ah_config.ah_dma_beacon_response_time = 2;
SYSCTL_ADD_INT(ctx, child, OID_AUTO, "dma_brt", CTLFLAG_RW,

2
sys/dev/siba/siba_core.c
View File

@ -1207,7 +1207,7 @@ siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq)
if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf)
return;
DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u mhz\n",
DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n",
(xtalfreq / 1000), (xtalfreq % 1000));
KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354,

2
sys/ia64/ia64/machdep.c
View File

@ -245,7 +245,7 @@ identifycpu(void)
printf("CPU: %s (", model_name);
if (cpu_freq)
printf("%u Mhz ", cpu_freq);
printf("%u MHz ", cpu_freq);
printf("%s)\n", family_name);
printf(" Origin = \"%s\" Revision = %d\n", vendor, revision);
printf(" Features = 0x%b\n", (u_int32_t) features,

6
sys/mips/rt305x/rt305x_sysctl.c
View File

@ -84,7 +84,7 @@ rt305x_sysctl_dump_config(device_t dev)
if ( val & SYSCTL_SYSCFG_BIG_ENDIAN)
printf("\tBig Endian\n");
if ( val & SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ)
printf("\tClock is 384Mhz\n");
printf("\tClock is 384MHz\n");
printf("\tBoot from %u\n",
((val & SYSCTL_SYSCFG_BOOT_FROM_MASK) >>
SYSCTL_SYSCFG_BOOT_FROM_SHIFT));
@ -109,7 +109,7 @@ rt305x_sysctl_dump_config(device_t dev)
printf("\tI2S clock is enabled\n");
printf("\tI2S clock is %s\n",
(val & SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT)?
"external":"internal 15.625Mhz");
"external":"internal 15.625MHz");
printf("\tI2S clock divider %u\n",
((val & SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK) >>
SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT));
@ -118,7 +118,7 @@ rt305x_sysctl_dump_config(device_t dev)
printf("\tPCM clock is %s\n",
(val & SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT)?
"external":"internal 15.625Mhz");
"external":"internal 15.625MHz");
printf("\tPCM clock divider %u\n",
((val & SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK) >>
SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT));