Finish renaming in if_dwc.
By using DWC TRM terminology, normal descriptor format should be named extended and alternate descriptor format should be named normal. Should not been functional change. MFC after: 4 weeks
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8d43a8685c
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188aee740f
@ -114,7 +114,7 @@ static int
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a20_if_dwc_mac_type(device_t dev)
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{
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return (DWC_GMAC_ALT_DESC);
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return (DWC_GMAC_NORMAL_DESC);
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}
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static int
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@ -66,7 +66,7 @@ static int
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aml8726_if_dwc_mac_type(device_t dev)
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{
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return (DWC_GMAC_ALT_DESC);
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return (DWC_GMAC_NORMAL_DESC);
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}
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static int
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@ -160,7 +160,7 @@ static int
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if_dwc_rk_mac_type(device_t dev)
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{
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return (DWC_GMAC_ALT_DESC);
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return (DWC_GMAC_NORMAL_DESC);
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}
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static int
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@ -74,7 +74,7 @@ static int
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if_dwc_socfpga_mac_type(device_t dev)
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{
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return (DWC_GMAC);
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return (DWC_GMAC_EXT_DESC);
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}
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static int
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@ -249,7 +249,7 @@ dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
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flags = 0;
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--sc->txcount;
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} else {
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if (sc->mactype == DWC_GMAC_ALT_DESC)
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if (sc->mactype != DWC_GMAC_EXT_DESC)
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flags = NTDESC1_TCH | NTDESC1_FS
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| NTDESC1_LS | NTDESC1_IC;
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else
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@ -259,7 +259,7 @@ dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
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}
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sc->txdesc_ring[idx].addr1 = (uint32_t)(paddr);
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if (sc->mactype == DWC_GMAC_ALT_DESC) {
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if (sc->mactype != DWC_GMAC_EXT_DESC) {
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sc->txdesc_ring[idx].desc0 = 0;
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sc->txdesc_ring[idx].desc1 = flags | len;
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} else {
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@ -537,7 +537,7 @@ dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr)
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nidx = next_rxidx(sc, idx);
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sc->rxdesc_ring[idx].addr2 = sc->rxdesc_ring_paddr +
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(nidx * sizeof(struct dwc_hwdesc));
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if (sc->mactype == DWC_GMAC_ALT_DESC)
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if (sc->mactype != DWC_GMAC_EXT_DESC)
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sc->rxdesc_ring[idx].desc1 = NRDESC1_RCH | RX_MAX_PACKET;
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else
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sc->rxdesc_ring[idx].desc1 = ERDESC1_RCH | MCLBYTES;
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@ -661,7 +661,7 @@ dwc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
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crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN);
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/* Take lower 8 bits and reverse it */
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val = bitreverse(~crc & 0xff);
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if (ctx->sc->mactype == DWC_GMAC_ALT_DESC)
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if (ctx->sc->mactype != DWC_GMAC_EXT_DESC)
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val >>= 2; /* Only need lower 6 bits */
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hashreg = (val >> 5);
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hashbit = (val & 31);
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@ -682,7 +682,7 @@ dwc_setup_rxfilter(struct dwc_softc *sc)
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DWC_ASSERT_LOCKED(sc);
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ifp = sc->ifp;
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nhash = sc->mactype == DWC_GMAC_ALT_DESC ? 2 : 8;
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nhash = sc->mactype != DWC_GMAC_EXT_DESC ? 2 : 8;
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/*
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* Set the multicast (group) filter hash.
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@ -715,7 +715,7 @@ dwc_setup_rxfilter(struct dwc_softc *sc)
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WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
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WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
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WRITE4(sc, MAC_FRAME_FILTER, ffval);
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if (sc->mactype == DWC_GMAC_ALT_DESC) {
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if (sc->mactype != DWC_GMAC_EXT_DESC) {
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WRITE4(sc, GMAC_MAC_HTLOW, ctx.hash[0]);
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WRITE4(sc, GMAC_MAC_HTHIGH, ctx.hash[1]);
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} else {
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@ -1260,7 +1260,7 @@ dwc_attach(device_t dev)
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return (ENXIO);
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}
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if (sc->mactype == DWC_GMAC_ALT_DESC) {
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if (sc->mactype != DWC_GMAC_EXT_DESC) {
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reg = BUS_MODE_FIXEDBURST;
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reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT);
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} else
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@ -272,8 +272,9 @@
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#define CURRENT_HOST_RECEIVE_BUF_ADDR 0x1054
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#define HW_FEATURE 0x1058
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#define DWC_GMAC 0x1
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#define DWC_GMAC_ALT_DESC 0x2
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#define DWC_GMAC_NORMAL_DESC 0x1
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#define DWC_GMAC_EXT_DESC 0x2
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#define GMAC_MII_CLK_60_100M_DIV42 0x0
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#define GMAC_MII_CLK_100_150M_DIV62 0x1
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#define GMAC_MII_CLK_25_35M_DIV16 0x2
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@ -41,7 +41,7 @@ CODE {
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static int
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if_dwc_default_mac_type(device_t dev)
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{
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return (DWC_GMAC);
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return (DWC_GMAC_EXT_DESC);
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}
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static int
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