d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add the AR9280 workarounds for PCIe suspend/resume.

Browse Source 
These aren't strictly needed at the moment as we're not doing APSM
and forcing the NIC in and out of network sleep.  But, they don't hurt.

Tested:

* AR9280 (mini-PCIe)

Obtained from:	Qualcomm Atheros, Linux ath9k
This commit is contained in:
Adrian Chadd 2012-05-26 01:36:25 +00:00
parent b815538dec
commit 1a67d0266c
1 changed files with 52 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
View File

@ -420,18 +420,68 @@ ar9280Attach(uint16_t devid, HAL_SOFTC sc,
static void
ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
{
uint32_t val;
if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
OS_DELAY(1000);
}
/*
* Set PCIe workaround bits
*
* NOTE:
*
* In Merlin and Kite, bit 14 in WA register (disable L1) should only
* be set when device enters D3 and be cleared when device comes back
* to D0.
*/
if (power_off) { /* Power-off */
OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
val = OS_REG_READ(ah, AR_WA);
/*
* Disable bit 6 and 7 before entering D3 to prevent
* system hang.
*/
val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
/*
* XXX Not sure, is specified in the reference HAL.
*/
val |= AR_WA_BIT22;
/*
* See above: set AR_WA_D3_L1_DISABLE when entering D3 state.
*
* XXX The reference HAL does it this way - it only sets
* AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT,
* which it (currently) isn't. So the following statement
* is currently a NOP.
*/
if (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
val |= AR_WA_D3_L1_DISABLE;
OS_REG_WRITE(ah, AR_WA, val);
} else { /* Power-on */
val = AR9280_WA_DEFAULT;
/*
* See note above: make sure L1_DISABLE is not set.
*/
val &= (~AR_WA_D3_L1_DISABLE);
OS_REG_WRITE(ah, AR_WA, val);
/* set bit 19 to allow forcing of pcie core into L1 state */
OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
}
}
static void
ar9280DisablePCIE(struct ath_hal *ah)
{
/* XXX TODO */
}
static void