Changes to boot on a subset of threads on an XLR/XLS core.
- Adds re-partitioning TLB per core for enabled threads. - Adds hardware thread id to cpuid mapping - updates rge driver packet distribution and message ring handling threads to be started based on hardware thread id. - remove unused early debugging code to set control registers. - coding style fixes Approved by: rrs (mentor)
This commit is contained in:
Jayachandran C.
parent
96a985c51d
commit
1a9950f319
@ -126,7 +126,7 @@ int mac_debug = 1;
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do {\
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if (mac_debug) {\
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printf("[%s@%d|%s]: cpu_%d: " fmt, \
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__FILE__, __LINE__, __FUNCTION__, PCPU_GET(cpuid), ##args);\
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__FILE__, __LINE__, __FUNCTION__, xlr_cpu_id(), ##args);\
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}\
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} while(0);
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@ -404,7 +404,7 @@ init_p2d_allocation(void)
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uint32_t cpumask;
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int cpu;
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cpumask = PCPU_GET(cpumask) | PCPU_GET(other_cpus);
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cpumask = xlr_hw_thread_mask;
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for (i = 0; i < 32; i++) {
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if (cpumask & (1 << i)) {
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@ -966,7 +966,7 @@ rmi_xlr_config_pde(struct driver_data *priv)
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/* uint32_t desc_pack_ctrl = 0; */
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uint32_t cpumask;
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cpumask = PCPU_GET(cpumask);
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cpumask = 0x1;
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#ifdef SMP
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/*
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* rge may be called before SMP start in a BOOTP/NFSROOT
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@ -974,7 +974,7 @@ rmi_xlr_config_pde(struct driver_data *priv)
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* the SMP is started.
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*/
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if (smp_started)
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cpumask |= PCPU_GET(other_cpus);
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cpumask = xlr_hw_thread_mask;
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#endif
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for (i = 0; i < MAXCPU; i++) {
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@ -1453,7 +1453,7 @@ mac_xmit(struct mbuf *m, struct rge_softc *sc,
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int stid = priv->txbucket;
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uint32_t tx_cycles = 0;
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unsigned long mflags = 0;
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int vcpu = PCPU_GET(cpuid);
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int vcpu = xlr_cpu_id();
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int rv;
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tx_cycles = mips_rd_count();
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@ -78,6 +78,7 @@ struct msgring_ithread {
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u_int i_pending;
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u_int i_flags;
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int i_cpu;
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int i_core;
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};
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struct msgring_ithread *msgring_ithreads[MAXCPU];
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@ -254,13 +255,13 @@ disable_msgring_int(void *arg)
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static int
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msgring_process_fast_intr(void *arg)
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{
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int cpu = PCPU_GET(cpuid);
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int core = xlr_core_id();
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volatile struct msgring_ithread *it;
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struct thread *td;
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/* wakeup an appropriate intr_thread for processing this interrupt */
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it = (volatile struct msgring_ithread *)msgring_ithreads[cpu];
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KASSERT(it != NULL, ("No interrupt thread on cpu %d", cpu));
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it = (volatile struct msgring_ithread *)msgring_ithreads[core];
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KASSERT(it != NULL, ("No interrupt thread on cpu %d", core));
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td = it->i_thread;
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/*
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@ -293,10 +294,11 @@ msgring_process(void *arg)
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/* First bind this thread to the right CPU */
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thread_lock(td);
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sched_bind(td, ithd->i_cpu);
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thread_unlock(td);
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atomic_store_rel_ptr((volatile uintptr_t *)&msgring_ithreads[ithd->i_cpu],
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atomic_store_rel_ptr((volatile uintptr_t *)&msgring_ithreads[ithd->i_core],
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(uintptr_t)arg);
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enable_msgring_int(NULL);
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@ -327,7 +329,7 @@ msgring_process(void *arg)
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}
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static void
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create_msgring_thread(int cpu)
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create_msgring_thread(int core, int cpu)
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{
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struct msgring_ithread *ithd;
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struct thread *td;
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@ -348,12 +350,13 @@ create_msgring_thread(int cpu)
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ithd->i_thread = td;
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ithd->i_pending = 0;
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ithd->i_cpu = cpu;
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ithd->i_core = core;
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thread_lock(td);
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sched_class(td, PRI_ITHD);
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sched_add(td, SRQ_INTR);
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thread_unlock(td);
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CTR2(KTR_INTR, "%s: created %s", __func__, ithd_name[cpu]);
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CTR2(KTR_INTR, "%s: created %s", __func__, ithd_name[core]);
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}
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int
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@ -376,7 +379,7 @@ register_msgring_handler(int major,
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mtx_unlock_spin(&msgrng_lock);
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if (xlr_test_and_set(&msgring_int_enabled)) {
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create_msgring_thread(0);
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create_msgring_thread(0, 0);
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cpu_establish_hardintr("msgring", (driver_filter_t *) msgring_process_fast_intr,
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NULL, NULL, IRQ_MSGRING,
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INTR_TYPE_NET | INTR_FAST, &cookie);
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@ -429,13 +432,15 @@ on_chip_init(void)
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static void
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start_msgring_threads(void *arg)
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{
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uint32_t cpu_mask;
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int cpu;
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int core, cpu;
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cpu_mask = PCPU_GET(cpumask) | PCPU_GET(other_cpus);
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for (cpu = 4; cpu < MAXCPU; cpu += 4)
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if (cpu_mask & (1<<cpu))
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create_msgring_thread(cpu);
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for (core = 1; core < XLR_MAX_CORES; core++) {
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if ((xlr_hw_thread_mask >> (4 * core)) & 0xf) {
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/* start one thread for an enabled core */
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cpu = xlr_hwtid_to_cpuid[4 * core];
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create_msgring_thread(core, cpu);
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}
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}
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}
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SYSINIT(start_msgring_threads, SI_SUB_SMP, SI_ORDER_MIDDLE, start_msgring_threads, NULL);
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@ -75,13 +75,7 @@ __FBSDID("$FreeBSD$");
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#include <mips/rmi/interrupt.h>
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#include <mips/rmi/pic.h>
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#ifdef XLR_PERFMON
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#include <mips/rmi/perfmon.h>
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#endif
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void mpwait(void);
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void enable_msgring_int(void *arg);
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unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE);
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/* 4KB static data aread to keep a copy of the bootload env until
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@ -100,164 +94,140 @@ uint64_t cpu_mask_info;
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uint32_t xlr_online_cpumask;
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uint32_t xlr_core_cpu_mask = 0x1; /* Core 0 thread 0 is always there */
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void
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platform_reset(void)
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{
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/* FIXME : use proper define */
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u_int32_t *mmio = (u_int32_t *) 0xbef18000;
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int xlr_shtlb_enabled;
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int xlr_ncores;
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int xlr_threads_per_core;
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uint32_t xlr_hw_thread_mask;
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int xlr_cpuid_to_hwtid[MAXCPU];
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int xlr_hwtid_to_cpuid[MAXCPU];
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printf("Rebooting the system now\n");
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mmio[8] = 0x1;
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}
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int xlr_asid_pcpu = 256; /* This the default */
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int xlr_shtlb_enabled = 0;
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/* This function sets up the number of tlb entries available
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to the kernel based on the number of threads brought up.
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The ASID range also gets divided similarly.
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THE NUMBER OF THREADS BROUGHT UP IN EACH CORE MUST BE THE SAME
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NOTE: This function will mark all 64TLB entries as available
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to the threads brought up in the core. If kernel is brought with say mask
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0x33333333, no TLBs will be available to the threads in each core.
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*/
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static void
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setup_tlb_resource(void)
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xlr_setup_mmu_split(void)
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{
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int mmu_setup;
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int value = 0;
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uint32_t cpu_map = xlr_boot1_info.cpu_online_map;
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uint32_t thr_mask = cpu_map >> (xlr_core_id() << 2);
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uint8_t core0 = xlr_boot1_info.cpu_online_map & 0xf;
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uint8_t core_thr_mask;
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int i = 0, count = 0;
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int val = 0;
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/* If CPU0 did not enable shared TLB, other cores need to follow */
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if ((xlr_core_id() != 0) && (xlr_shtlb_enabled == 0))
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return;
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/* First check if each core is brought up with the same mask */
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for (i = 1; i < 8; i++) {
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core_thr_mask = cpu_map >> (i << 2);
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core_thr_mask &= 0xf;
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if (core_thr_mask && core_thr_mask != core0) {
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printf
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("Each core must be brought with same cpu mask\n");
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printf("Cannot enabled shared TLB. ");
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printf("Falling back to split TLB mode\n");
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return;
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}
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if (xlr_threads_per_core == 4 && xlr_shtlb_enabled == 0)
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return; /* no change from boot setup */
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switch (xlr_threads_per_core) {
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case 1:
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val = 0; break;
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case 2:
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val = 2; break;
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case 4:
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val = 3; break;
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}
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xlr_shtlb_enabled = 1;
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for (i = 0; i < 4; i++)
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if (thr_mask & (1 << i))
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count++;
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switch (count) {
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case 1:
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xlr_asid_pcpu = 256;
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break;
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case 2:
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xlr_asid_pcpu = 128;
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value = 0x2;
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break;
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default:
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xlr_asid_pcpu = 64;
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value = 0x3;
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break;
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}
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mmu_setup = read_32bit_phnx_ctrl_reg(4, 0);
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mmu_setup = mmu_setup & ~0x06;
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mmu_setup |= (value << 1);
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mmu_setup |= (val << 1);
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/* turn on global mode */
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#ifndef SMP
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mmu_setup |= 0x01;
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#endif
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if (xlr_shtlb_enabled)
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mmu_setup |= 0x01;
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write_32bit_phnx_ctrl_reg(4, 0, mmu_setup);
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}
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/*
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* Platform specific register setup for CPUs
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* XLR has control registers accessible with MFCR/MTCR instructions, this
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* code initialized them from the environment variable xlr.cr of form:
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* xlr.cr=reg:val[,reg:val]*, all values in hex.
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* To enable shared TLB option use xlr.shtlb=1
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*/
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void
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platform_cpu_init()
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static void
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xlr_parse_mmu_options(void)
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{
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char *hw_env;
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char *start, *end;
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uint32_t reg, val;
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int thr_id = xlr_thr_id();
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#ifdef notyet
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char *hw_env, *start, *end;
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#endif
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uint32_t cpu_map;
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uint8_t core0_thr_mask, core_thr_mask;
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int i, j, k;
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/*
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* XXX: SMP now need different wired mappings for threads
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* we cannot share TLBs.
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*/
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if (thr_id == 0) {
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if ((hw_env = getenv("xlr.shtlb")) != NULL) {
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start = hw_env;
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reg = strtoul(start, &end, 16);
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if (start != end && reg != 0)
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setup_tlb_resource();
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} else {
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/* By default TLB entries are shared in a core */
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setup_tlb_resource();
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}
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}
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if ((hw_env = getenv("xlr.cr")) == NULL)
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return;
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start = hw_env;
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while (*start != '\0') {
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reg = strtoul(start, &end, 16);
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if (start == end) {
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printf("Invalid value in xlr.cr %s, cannot read a hex value at %d\n",
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hw_env, start - hw_env);
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goto err_return;
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}
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if (*end != ':') {
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printf("Invalid format in xlr.cr %s, ':' expected at pos %d\n",
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hw_env, end - hw_env);
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goto err_return;
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}
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start = end + 1;/* step over ':' */
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val = strtoul(start, &end, 16);
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if (start == end) {
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printf("Invalid value in xlr.cr %s, cannot read a hex value at pos %d\n",
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hw_env, start - hw_env);
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goto err_return;
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}
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if (*end != ',' && *end != '\0') {
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printf("Invalid format in xlr.cr %s, ',' expected at pos %d\n",
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hw_env, end - hw_env);
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goto err_return;
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}
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xlr_mtcr(reg, val);
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if (*end == ',')
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start = end + 1; /* skip over ',' */
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/* First check for the shared TLB setup */
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xlr_shtlb_enabled = 0;
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#ifdef notyet
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/*
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* We don't support sharing TLB per core - TODO
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*/
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xlr_shtlb_enabled = 0;
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if ((hw_env = getenv("xlr.shtlb")) != NULL) {
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start = hw_env;
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tmp = strtoul(start, &end, 0);
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if (start != end)
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xlr_shtlb_enabled = (tmp != 0);
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else
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start = end;
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printf("Bad value for xlr.shtlb [%s]\n", hw_env);
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freeenv(hw_env);
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}
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freeenv(hw_env);
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#endif
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/*
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* XLR supports splitting the 64 TLB entries across one, two or four
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* threads (split mode). XLR also allows the 64 TLB entries to be shared
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* across all threads in the core using a global flag (shared TLB mode).
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* We will support 1/2/4 threads in split mode or shared mode.
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*
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*/
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xlr_ncores = 1;
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cpu_map = xlr_boot1_info.cpu_online_map;
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core0_thr_mask = cpu_map & 0xf;
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switch (core0_thr_mask) {
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case 1:
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xlr_threads_per_core = 1; break;
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case 3:
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xlr_threads_per_core = 2; break;
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case 0xf:
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xlr_threads_per_core = 4; break;
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default:
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goto unsupp;
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}
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/* Verify other cores CPU masks */
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for (i = 1; i < XLR_MAX_CORES; i++) {
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core_thr_mask = (cpu_map >> (i*4)) & 0xf;
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if (core_thr_mask) {
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if (core_thr_mask != core0_thr_mask)
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goto unsupp;
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xlr_ncores++;
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}
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}
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/* setup hardware processor id to cpu id mapping */
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xlr_hw_thread_mask = xlr_boot1_info.cpu_online_map;
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for (i = 0; i< MAXCPU; i++)
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xlr_cpuid_to_hwtid[i] =
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xlr_hwtid_to_cpuid [i] = -1;
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for (i = 0, k = 0; i < XLR_MAX_CORES; i++) {
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if (((cpu_map >> (i*4)) & 0xf) == 0)
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continue;
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for (j = 0; j < xlr_threads_per_core; j++) {
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xlr_cpuid_to_hwtid[k] = i*4 + j;
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xlr_hwtid_to_cpuid[i*4 + j] = k;
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k++;
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}
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}
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/* setup for the startup core */
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xlr_setup_mmu_split();
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return;
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err_return:
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panic("Invalid xlr.cr setting!");
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unsupp:
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printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n"
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"\tcore0 thread mask [%lx], boot cpu mask [%lx]\n"
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"\tUsing default, 16 TLB entries per CPU, split mode\n",
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(u_long)core0_thr_mask, (u_long)cpu_map);
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panic("Invalid CPU mask - halting.\n");
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return;
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}
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static void
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xlr_set_boot_flags(void)
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{
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char *p;
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for (p = getenv("boot_flags"); p && *p != '\0'; p++) {
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p = getenv("bootflags");
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if (p == NULL)
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p = getenv("boot_flags"); /* old style */
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if (p == NULL)
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return;
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for (; p && *p != '\0'; p++) {
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switch (*p) {
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case 'd':
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case 'D':
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@ -283,9 +253,7 @@ xlr_set_boot_flags(void)
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}
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}
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if (p)
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freeenv(p);
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freeenv(p);
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return;
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}
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extern uint32_t _end;
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@ -307,7 +275,6 @@ mips_init(void)
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}
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#endif
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mips_proc0_init();
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write_c0_register32(MIPS_COP_0_OSSCRATCH, 7, pcpup->pc_curthread);
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mutex_init();
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}
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@ -325,11 +292,6 @@ platform_start(__register_t a0 __unused,
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void (*wakeup) (void *, void *, unsigned int);
|
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|
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#endif
|
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/* XXX no zeroing of BSS? */
|
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/* Initialize pcpu stuff */
|
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mips_pcpu0_init();
|
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|
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/* XXX FIXME the code below is not 64 bit clean */
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/* Save boot loader and other stuff from scratch regs */
|
||||
xlr_boot1_info = *(struct boot1_info *)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0);
|
||||
@ -343,6 +305,9 @@ platform_start(__register_t a0 __unused,
|
||||
/* TODO: Verify the magic number here */
|
||||
/* FIXMELATER: xlr_boot1_info.magic_number */
|
||||
|
||||
/* Initialize pcpu stuff */
|
||||
mips_pcpu0_init();
|
||||
|
||||
/* initialize console so that we have printf */
|
||||
boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
|
||||
|
||||
@ -378,6 +343,7 @@ platform_start(__register_t a0 __unused,
|
||||
}
|
||||
|
||||
xlr_set_boot_flags();
|
||||
xlr_parse_mmu_options();
|
||||
|
||||
/* get physical memory info from boot loader */
|
||||
boot_map = (struct xlr_boot1_mem_map *)
|
||||
@ -437,9 +403,6 @@ platform_start(__register_t a0 __unused,
|
||||
phys_avail[j] = phys_avail[j + 1] = 0;
|
||||
realmem = physmem = btoc(physsz);
|
||||
|
||||
/* Store pcpu in scratch 5 */
|
||||
write_c0_register32(MIPS_COP_0_OSSCRATCH, 5, pcpup);
|
||||
|
||||
/* Set up hz, among others. */
|
||||
mips_init();
|
||||
|
||||
@ -452,7 +415,7 @@ platform_start(__register_t a0 __unused,
|
||||
for (i = 4; i < MAXCPU; i += 4) {
|
||||
if ((tmp & (0xf << i)) && !(tmp & (0x1 << i))) {
|
||||
/*
|
||||
* Oopps.. thread 0 is not available. Disable whole
|
||||
* Oops.. thread 0 is not available. Disable whole
|
||||
* core
|
||||
*/
|
||||
tmp = tmp & ~(0xf << i);
|
||||
@ -463,15 +426,6 @@ platform_start(__register_t a0 __unused,
|
||||
xlr_boot1_info.cpu_online_map = tmp;
|
||||
|
||||
/* Wakeup Other cpus, and put them in bsd park code. */
|
||||
for (i = 1, j = 1; i < 32; i++) {
|
||||
/* Allocate stack for all other cpus from fbsd kseg0 memory. */
|
||||
if ((1U << i) & xlr_boot1_info.cpu_online_map) {
|
||||
if ((i & 0x3) == 0) /* store thread0 of each core */
|
||||
xlr_core_cpu_mask |= (1 << j);
|
||||
j++;
|
||||
}
|
||||
}
|
||||
|
||||
wakeup = ((void (*) (void *, void *, unsigned int))
|
||||
(unsigned long)(xlr_boot1_info.wakeup));
|
||||
printf("Waking up CPUs 0x%llx.\n", xlr_boot1_info.cpu_online_map & ~(0x1U));
|
||||
@ -492,13 +446,16 @@ platform_start(__register_t a0 __unused,
|
||||
printf("Platform specific startup now completes\n");
|
||||
}
|
||||
|
||||
void
|
||||
platform_cpu_init()
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
platform_identify(void)
|
||||
{
|
||||
printf("Board [%d:%d], processor 0x%08x\n", (int)xlr_boot1_info.board_major_version,
|
||||
(int)xlr_boot1_info.board_minor_version, mips_rd_prid());
|
||||
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
@ -510,6 +467,15 @@ platform_trap_enter(void)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
platform_reset(void)
|
||||
{
|
||||
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
|
||||
|
||||
/* write 1 to GPIO software reset register */
|
||||
xlr_write_reg(mmio, 8, 1);
|
||||
}
|
||||
|
||||
void
|
||||
platform_trap_exit(void)
|
||||
{
|
||||
@ -518,20 +484,31 @@ platform_trap_exit(void)
|
||||
#ifdef SMP
|
||||
int xlr_ap_release[MAXCPU];
|
||||
|
||||
int platform_start_ap(int cpuid)
|
||||
int
|
||||
platform_start_ap(int cpuid)
|
||||
{
|
||||
/*
|
||||
* other cpus are enabled by the boot loader and they will be
|
||||
* already looping in mpwait, release them
|
||||
*/
|
||||
atomic_store_rel_int(&xlr_ap_release[cpuid], 1);
|
||||
return 0;
|
||||
int hwid = xlr_cpuid_to_hwtid[cpuid];
|
||||
|
||||
if (xlr_boot1_info.cpu_online_map & (1<<hwid)) {
|
||||
/*
|
||||
* other cpus are enabled by the boot loader and they will be
|
||||
* already looping in mpwait, release them
|
||||
*/
|
||||
atomic_store_rel_int(&xlr_ap_release[hwid], 1);
|
||||
return (0);
|
||||
} else
|
||||
return (-1);
|
||||
}
|
||||
|
||||
void platform_init_ap(int processor_id)
|
||||
void
|
||||
platform_init_ap(int cpuid)
|
||||
{
|
||||
uint32_t stat;
|
||||
|
||||
/* The first thread has to setup the core MMU split */
|
||||
if (xlr_thr_id() == 0)
|
||||
xlr_setup_mmu_split();
|
||||
|
||||
/* Setup interrupts for secondary CPUs here */
|
||||
stat = mips_rd_status();
|
||||
KASSERT((stat & MIPS_SR_INT_IE) == 0,
|
||||
@ -549,34 +526,40 @@ void platform_init_ap(int processor_id)
|
||||
return;
|
||||
}
|
||||
|
||||
int platform_ipi_intrnum(void)
|
||||
int
|
||||
platform_ipi_intrnum(void)
|
||||
{
|
||||
return IRQ_IPI;
|
||||
return (IRQ_IPI);
|
||||
}
|
||||
|
||||
void platform_ipi_send(int cpuid)
|
||||
void
|
||||
platform_ipi_send(int cpuid)
|
||||
{
|
||||
pic_send_ipi(cpuid, platform_ipi_intrnum(), 0);
|
||||
pic_send_ipi(xlr_cpuid_to_hwtid[cpuid],
|
||||
platform_ipi_intrnum(), 0);
|
||||
}
|
||||
|
||||
void platform_ipi_clear(void)
|
||||
void
|
||||
platform_ipi_clear(void)
|
||||
{
|
||||
}
|
||||
|
||||
int platform_processor_id(void)
|
||||
int
|
||||
platform_processor_id(void)
|
||||
{
|
||||
return xlr_cpu_id();
|
||||
return (xlr_hwtid_to_cpuid[xlr_cpu_id()]);
|
||||
}
|
||||
|
||||
int platform_num_processors(void)
|
||||
int
|
||||
platform_num_processors(void)
|
||||
{
|
||||
return fls(xlr_boot1_info.cpu_online_map);
|
||||
return (xlr_ncores * xlr_threads_per_core);
|
||||
}
|
||||
|
||||
struct cpu_group *
|
||||
platform_smp_topo()
|
||||
{
|
||||
return (smp_topo_2level(CG_SHARE_L2, platform_num_processors() / 4,
|
||||
CG_SHARE_L1, 4, CG_FLAG_THREAD));
|
||||
return (smp_topo_2level(CG_SHARE_L2, xlr_ncores, CG_SHARE_L1,
|
||||
xlr_threads_per_core, CG_FLAG_THREAD));
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -352,4 +352,9 @@ xlr_paddr_lw(uint64_t paddr)
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
/* for cpuid to hardware thread id mapping */
|
||||
extern uint32_t xlr_hw_thread_mask;
|
||||
extern int xlr_cpuid_to_hwtid[];
|
||||
extern int xlr_hwtid_to_cpuid[];
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user