Add DEVICE_IDENTIFY method for wbwd(4), required on most of recent
Supermicro motherboards. Tested on X8STi and X8DTH boards. Sponsored by: iXsystems, Inc. MFC after: 2 weeks
This commit is contained in:
Xin LI
parent
e25fe6cdb9
commit
1adb4ebd35
@ -1,5 +1,6 @@
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/*-
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* Copyright (c) 2011 Sandvine Incorporated ULC.
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* Copyright (c) 2012 iXsystems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -93,15 +94,6 @@ __FBSDID("$FreeBSD$");
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#define WB_LDN8_CRF7_CLEAR_MASK \
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(WB_LDN8_CRF7_MOUSE|WB_LDN8_CRF7_KEYB|WB_LDN8_CRF7_TS|WB_LDN8_CRF7_IRQS)
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#define write_efir_1(sc, value) \
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bus_space_write_1((sc)->bst, (sc)->bsh, 0, (value))
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#define read_efir_1(sc) \
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bus_space_read_1((sc)->bst, (sc)->bsh, 0)
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#define write_efdr_1(sc, value) \
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bus_space_write_1((sc)->bst, (sc)->bsh, 1, (value))
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#define read_efdr_1(sc) \
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bus_space_read_1((sc)->bst, (sc)->bsh, 1)
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struct wb_softc {
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device_t dev;
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struct resource *portres;
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@ -109,8 +101,8 @@ struct wb_softc {
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bus_space_handle_t bsh;
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int rid;
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eventhandler_tag ev_tag;
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int (*ext_cfg_enter_f)(struct wb_softc *);
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void (*ext_cfg_exit_f)(struct wb_softc *);
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int (*ext_cfg_enter_f)(struct wb_softc *, u_short);
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void (*ext_cfg_exit_f)(struct wb_softc *, u_short);
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int debug_verbose;
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/*
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@ -131,13 +123,13 @@ struct wb_softc {
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uint8_t reg_2;
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};
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static int ext_cfg_enter_0x87_0x87(struct wb_softc *);
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static void ext_cfg_exit_0xaa(struct wb_softc *);
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static int ext_cfg_enter_0x87_0x87(struct wb_softc *, u_short);
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static void ext_cfg_exit_0xaa(struct wb_softc *, u_short);
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struct winbond_superio_cfg {
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uint8_t efer; /* and efir */
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int (*ext_cfg_enter_f)(struct wb_softc *);
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void (*ext_cfg_exit_f)(struct wb_softc *);
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int (*ext_cfg_enter_f)(struct wb_softc *, u_short);
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void (*ext_cfg_exit_f)(struct wb_softc *, u_short);
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} probe_addrs[] = {
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{
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.efer = 0x2e,
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@ -189,6 +181,50 @@ struct winbond_vendor_device_id {
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},
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};
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static void
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write_efir_1(struct wb_softc *sc, u_short baseport, uint8_t value)
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{
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MPASS(sc != NULL || baseport != 0);
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if (sc != NULL)
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bus_space_write_1((sc)->bst, (sc)->bsh, 0, (value));
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else
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outb(baseport, value);
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}
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static uint8_t __unused
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read_efir_1(struct wb_softc *sc, u_short baseport)
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{
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MPASS(sc != NULL || baseport != 0);
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if (sc != NULL)
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return (bus_space_read_1((sc)->bst, (sc)->bsh, 0));
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else
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return (inb(baseport));
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}
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static void
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write_efdr_1(struct wb_softc *sc, u_short baseport, uint8_t value)
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{
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MPASS(sc != NULL || baseport != 0);
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if (sc != NULL)
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bus_space_write_1((sc)->bst, (sc)->bsh, 1, (value));
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else
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outb(baseport + 1, value);
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}
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static uint8_t
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read_efdr_1(struct wb_softc *sc, u_short baseport)
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{
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MPASS(sc != NULL || baseport != 0);
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if (sc != NULL)
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return (bus_space_read_1((sc)->bst, (sc)->bsh, 1));
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else
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return (inb(baseport + 1));
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}
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/*
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* Return the watchdog related registers as we last read them. This will
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* usually not give the current timeout or state on whether the watchdog
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@ -231,19 +267,19 @@ sysctl_wb_debug_current(SYSCTL_HANDLER_ARGS)
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* Enter extended function mode in case someone else has been
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* poking on the registers. We will not leave it though.
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*/
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if ((*sc->ext_cfg_enter_f)(sc) != 0)
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if ((*sc->ext_cfg_enter_f)(sc, 0) != 0)
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return (ENXIO);
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/* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
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write_efir_1(sc, WB_LDN_REG);
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write_efdr_1(sc, WB_LDN_REG_LDN8);
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write_efir_1(sc, 0, WB_LDN_REG);
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write_efdr_1(sc, 0, WB_LDN_REG_LDN8);
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write_efir_1(sc, WB_LDN8_CRF5);
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sc->reg_1 = read_efdr_1(sc);
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write_efir_1(sc, WB_LDN8_CRF6);
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sc->reg_timeout = read_efdr_1(sc);
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write_efir_1(sc, WB_LDN8_CRF7);
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sc->reg_2 = read_efdr_1(sc);
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write_efir_1(sc, 0, WB_LDN8_CRF5);
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sc->reg_1 = read_efdr_1(sc, 0);
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write_efir_1(sc, 0, WB_LDN8_CRF6);
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sc->reg_timeout = read_efdr_1(sc, 0);
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write_efir_1(sc, 0, WB_LDN8_CRF7);
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sc->reg_2 = read_efdr_1(sc, 0);
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return (sysctl_wb_debug(oidp, arg1, arg2, req));
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}
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@ -288,7 +324,7 @@ sysctl_wb_force_test_nmi(SYSCTL_HANDLER_ARGS)
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* Enter extended function mode in case someone else has been
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* poking on the registers. We will not leave it though.
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*/
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if ((*sc->ext_cfg_enter_f)(sc) != 0)
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if ((*sc->ext_cfg_enter_f)(sc, 0) != 0)
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return (ENXIO);
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#ifdef notyet
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@ -301,16 +337,16 @@ sysctl_wb_force_test_nmi(SYSCTL_HANDLER_ARGS)
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#endif
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/* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
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write_efir_1(sc, WB_LDN_REG);
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write_efdr_1(sc, WB_LDN_REG_LDN8);
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write_efir_1(sc, 0, WB_LDN_REG);
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write_efdr_1(sc, 0, WB_LDN_REG_LDN8);
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/* Force watchdog to fire. */
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write_efir_1(sc, WB_LDN8_CRF7);
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sc->reg_2 = read_efdr_1(sc);
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write_efir_1(sc, 0, WB_LDN8_CRF7);
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sc->reg_2 = read_efdr_1(sc, 0);
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sc->reg_2 |= WB_LDN8_CRF7_FORCE;
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write_efir_1(sc, WB_LDN8_CRF7);
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write_efdr_1(sc, sc->reg_2);
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write_efir_1(sc, 0, WB_LDN8_CRF7);
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write_efdr_1(sc, 0, sc->reg_2);
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return (0);
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}
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@ -344,24 +380,24 @@ wb_print_state(struct wb_softc *sc, const char *msg)
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* between different chips.
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*/
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static int
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ext_cfg_enter_0x87_0x87(struct wb_softc *sc)
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ext_cfg_enter_0x87_0x87(struct wb_softc *sc, u_short baseport)
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{
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/*
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* Enable extended function mode.
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* Winbond does not allow us to validate so always return success.
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*/
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write_efir_1(sc, 0x87);
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write_efir_1(sc, 0x87);
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write_efir_1(sc, baseport, 0x87);
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write_efir_1(sc, baseport, 0x87);
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return (0);
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}
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static void
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ext_cfg_exit_0xaa(struct wb_softc *sc)
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ext_cfg_exit_0xaa(struct wb_softc *sc, u_short baseport)
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{
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write_efir_1(sc, 0xaa);
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write_efir_1(sc, baseport, 0xaa);
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}
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/*
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@ -379,22 +415,22 @@ wb_set_watchdog(struct wb_softc *sc, unsigned int timeout)
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* Enter extended function mode in case someone else has been
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* poking on the registers. We will not leave it though.
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*/
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if ((*sc->ext_cfg_enter_f)(sc) != 0)
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if ((*sc->ext_cfg_enter_f)(sc, 0) != 0)
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return (ENXIO);
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/* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog) */
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write_efir_1(sc, WB_LDN_REG);
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write_efdr_1(sc, WB_LDN_REG_LDN8);
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write_efir_1(sc, 0, WB_LDN_REG);
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write_efdr_1(sc, 0, WB_LDN_REG_LDN8);
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/* Disable and validate or arm/reset watchdog. */
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if (timeout == 0) {
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/* Disable watchdog. */
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write_efir_1(sc, WB_LDN8_CRF6);
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write_efdr_1(sc, 0x00);
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write_efir_1(sc, 0, WB_LDN8_CRF6);
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write_efdr_1(sc, 0, 0x00);
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/* Re-check. */
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write_efir_1(sc, WB_LDN8_CRF6);
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sc->reg_timeout = read_efdr_1(sc);
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write_efir_1(sc, 0, WB_LDN8_CRF6);
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sc->reg_timeout = read_efdr_1(sc, 0);
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if (sc->reg_timeout != 0x00) {
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device_printf(sc->dev, "Failed to disable watchdog: "
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@ -415,8 +451,8 @@ wb_set_watchdog(struct wb_softc *sc, unsigned int timeout)
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return (EINVAL);
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/* Read current scaling factor. */
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write_efir_1(sc, WB_LDN8_CRF5);
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sc->reg_1 = read_efdr_1(sc);
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write_efir_1(sc, 0, WB_LDN8_CRF5);
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sc->reg_1 = read_efdr_1(sc, 0);
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if (timeout > 255) {
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/* Set scaling factor to 60s. */
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@ -431,21 +467,21 @@ wb_set_watchdog(struct wb_softc *sc, unsigned int timeout)
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}
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/* In case we fired before we need to clear to fire again. */
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write_efir_1(sc, WB_LDN8_CRF7);
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sc->reg_2 = read_efdr_1(sc);
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write_efir_1(sc, 0, WB_LDN8_CRF7);
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sc->reg_2 = read_efdr_1(sc, 0);
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if (sc->reg_2 & WB_LDN8_CRF7_TS) {
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sc->reg_2 &= ~WB_LDN8_CRF7_TS;
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write_efir_1(sc, WB_LDN8_CRF7);
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write_efdr_1(sc, sc->reg_2);
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write_efir_1(sc, 0, WB_LDN8_CRF7);
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write_efdr_1(sc, 0, sc->reg_2);
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}
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/* Write back scaling factor. */
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write_efir_1(sc, WB_LDN8_CRF5);
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write_efdr_1(sc, sc->reg_1);
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write_efir_1(sc, 0, WB_LDN8_CRF5);
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write_efdr_1(sc, 0, sc->reg_1);
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/* Set timer and arm/reset the watchdog. */
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write_efir_1(sc, WB_LDN8_CRF6);
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write_efdr_1(sc, sc->reg_timeout);
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write_efir_1(sc, 0, WB_LDN8_CRF6);
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write_efdr_1(sc, 0, sc->reg_timeout);
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}
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if (sc->debug_verbose)
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@ -515,62 +551,71 @@ wb_probe_enable(device_t dev, int probe)
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int error, found, i, j;
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uint8_t dev_id, dev_rev, cr26;
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sc = device_get_softc(dev);
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bzero(sc, sizeof(*sc));
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sc->dev = dev;
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if (dev == NULL)
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sc = NULL;
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else {
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sc = device_get_softc(dev);
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bzero(sc, sizeof(*sc));
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sc->dev = dev;
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}
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error = ENXIO;
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for (i = 0; i < sizeof(probe_addrs) / sizeof(*probe_addrs); i++) {
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/* Allocate bus resources for IO index/data register access. */
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sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
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probe_addrs[i].efer, probe_addrs[i].efer + 1, 2, RF_ACTIVE);
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if (sc->portres == NULL)
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continue;
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sc->bst = rman_get_bustag(sc->portres);
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sc->bsh = rman_get_bushandle(sc->portres);
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if (sc != NULL) {
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/* Allocate bus resources for IO index/data register access. */
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sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
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probe_addrs[i].efer, probe_addrs[i].efer + 1, 2, RF_ACTIVE);
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if (sc->portres == NULL)
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continue;
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sc->bst = rman_get_bustag(sc->portres);
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sc->bsh = rman_get_bushandle(sc->portres);
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}
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found = 0;
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error = (*probe_addrs[i].ext_cfg_enter_f)(sc);
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error = (*probe_addrs[i].ext_cfg_enter_f)(sc, probe_addrs[i].efer);
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if (error != 0)
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goto cleanup;
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/* Identify the SuperIO chip. */
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write_efir_1(sc, WB_DEVICE_ID_REG);
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dev_id = read_efdr_1(sc);
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write_efir_1(sc, WB_DEVICE_REV_REG);
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dev_rev = read_efdr_1(sc);
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write_efir_1(sc, WB_CR26);
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cr26 = read_efdr_1(sc);
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write_efir_1(sc, probe_addrs[i].efer, WB_DEVICE_ID_REG);
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dev_id = read_efdr_1(sc, probe_addrs[i].efer);
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write_efir_1(sc, probe_addrs[i].efer, WB_DEVICE_REV_REG);
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dev_rev = read_efdr_1(sc, probe_addrs[i].efer);
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write_efir_1(sc, probe_addrs[i].efer, WB_CR26);
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cr26 = read_efdr_1(sc, probe_addrs[i].efer);
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/* HEFRAS of 0 means EFER at 0x2e, 1 means EFER at 0x4e. */
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if (((cr26 & 0x40) == 0x00 && probe_addrs[i].efer != 0x2e) ||
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((cr26 & 0x40) == 0x40 && probe_addrs[i].efer != 0x4e)) {
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device_printf(dev, "HEFRAS and EFER do not align: EFER "
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"0x%02x DevID 0x%02x DevRev 0x%02x CR26 0x%02x\n",
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probe_addrs[i].efer, dev_id, dev_rev, cr26);
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if (dev != NULL)
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device_printf(dev, "HEFRAS and EFER do not "
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"align: EFER 0x%02x DevID 0x%02x DevRev "
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"0x%02x CR26 0x%02x\n",
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probe_addrs[i].efer, dev_id, dev_rev, cr26);
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goto cleanup;
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}
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for (j = 0; j < sizeof(wb_devs) / sizeof(*wb_devs); j++) {
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if (wb_devs[j].device_id == dev_id &&
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wb_devs[j].device_rev == dev_rev) {
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if (probe)
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if (probe && dev != NULL)
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device_set_desc(dev, wb_devs[j].descr);
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found++;
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break;
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}
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}
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if (probe && found && bootverbose)
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if (probe && found && bootverbose && dev != NULL)
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device_printf(dev, "%s EFER 0x%02x ID 0x%02x Rev 0x%02x"
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" CR26 0x%02x (probing)\n", device_get_desc(dev),
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probe_addrs[i].efer, dev_id, dev_rev, cr26);
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cleanup:
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if (probe || !found) {
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(*probe_addrs[i].ext_cfg_exit_f)(sc);
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(*probe_addrs[i].ext_cfg_exit_f)(sc, probe_addrs[i].efer);
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(void) bus_release_resource(dev, SYS_RES_IOPORT, sc->rid,
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sc->portres);
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if (sc != NULL)
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(void) bus_release_resource(dev, SYS_RES_IOPORT,
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sc->rid, sc->portres);
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}
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/*
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@ -579,8 +624,10 @@ wb_probe_enable(device_t dev, int probe)
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* for operations.
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*/
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if (found) {
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sc->ext_cfg_enter_f = probe_addrs[i].ext_cfg_enter_f;
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sc->ext_cfg_exit_f = probe_addrs[i].ext_cfg_exit_f;
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if (sc != NULL) {
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sc->ext_cfg_enter_f = probe_addrs[i].ext_cfg_enter_f;
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sc->ext_cfg_exit_f = probe_addrs[i].ext_cfg_exit_f;
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}
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error = BUS_PROBE_DEFAULT;
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break;
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} else
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@ -590,6 +637,21 @@ wb_probe_enable(device_t dev, int probe)
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return (error);
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}
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static void
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wb_identify(driver_t *driver, device_t parent)
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{
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device_t dev;
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if ((dev = device_find_child(parent, driver->name, 0)) == NULL) {
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if (wb_probe_enable(dev, 1) != BUS_PROBE_DEFAULT) {
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if (bootverbose)
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device_printf(dev, "can not find compatible Winbond chip.\n");
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} else
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dev = BUS_ADD_CHILD(parent, 0, driver->name, 0);
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return;
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}
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}
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static int
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wb_probe(device_t dev)
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||||
{
|
||||
@ -619,20 +681,20 @@ wb_attach(device_t dev)
|
||||
("%s: successfull probe result but not setup correctly", __func__));
|
||||
|
||||
/* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
|
||||
write_efir_1(sc, WB_LDN_REG);
|
||||
write_efdr_1(sc, WB_LDN_REG_LDN8);
|
||||
write_efir_1(sc, 0, WB_LDN_REG);
|
||||
write_efdr_1(sc, 0, WB_LDN_REG_LDN8);
|
||||
|
||||
/* Make sure LDN8 is enabled (Do we need to? Also affects GPIO). */
|
||||
write_efir_1(sc, WB_LDN8_CR30);
|
||||
write_efdr_1(sc, WB_LDN8_CR30_ACTIVE);
|
||||
write_efir_1(sc, 0, WB_LDN8_CR30);
|
||||
write_efdr_1(sc, 0, WB_LDN8_CR30_ACTIVE);
|
||||
|
||||
/* Read the current watchdog configuration. */
|
||||
write_efir_1(sc, WB_LDN8_CRF5);
|
||||
sc->reg_1 = read_efdr_1(sc);
|
||||
write_efir_1(sc, WB_LDN8_CRF6);
|
||||
sc->reg_timeout = read_efdr_1(sc);
|
||||
write_efir_1(sc, WB_LDN8_CRF7);
|
||||
sc->reg_2 = read_efdr_1(sc);
|
||||
write_efir_1(sc, 0, WB_LDN8_CRF5);
|
||||
sc->reg_1 = read_efdr_1(sc, 0);
|
||||
write_efir_1(sc, 0, WB_LDN8_CRF6);
|
||||
sc->reg_timeout = read_efdr_1(sc, 0);
|
||||
write_efir_1(sc, 0, WB_LDN8_CRF7);
|
||||
sc->reg_2 = read_efdr_1(sc, 0);
|
||||
|
||||
/* Print current state if bootverbose or watchdog already enabled. */
|
||||
if (bootverbose || (sc->reg_timeout > 0x00))
|
||||
@ -644,12 +706,12 @@ wb_attach(device_t dev)
|
||||
*/
|
||||
sc->reg_1 &= ~(WB_LDN8_CRF5_KEYB_P20);
|
||||
sc->reg_1 |= WB_LDN8_CRF5_KBRST;
|
||||
write_efir_1(sc, WB_LDN8_CRF5);
|
||||
write_efdr_1(sc, sc->reg_1);
|
||||
write_efir_1(sc, 0, WB_LDN8_CRF5);
|
||||
write_efdr_1(sc, 0, sc->reg_1);
|
||||
|
||||
sc->reg_2 &= ~WB_LDN8_CRF7_CLEAR_MASK;
|
||||
write_efir_1(sc, WB_LDN8_CRF7);
|
||||
write_efdr_1(sc, sc->reg_2);
|
||||
write_efir_1(sc, 0, WB_LDN8_CRF7);
|
||||
write_efdr_1(sc, 0, sc->reg_2);
|
||||
|
||||
/* Read global timeout override tunable, Add per device sysctls. */
|
||||
if (TUNABLE_ULONG_FETCH("hw.wbwd.timeout_override", &timeout)) {
|
||||
@ -698,7 +760,7 @@ wb_detach(device_t dev)
|
||||
wb_set_watchdog(sc, 0);
|
||||
|
||||
/* Disable extended function mode. */
|
||||
(*sc->ext_cfg_exit_f)(sc);
|
||||
(*sc->ext_cfg_exit_f)(sc, 0);
|
||||
|
||||
/* Cleanup resources. */
|
||||
(void) bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
|
||||
@ -710,6 +772,7 @@ wb_detach(device_t dev)
|
||||
|
||||
static device_method_t wb_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_identify, wb_identify),
|
||||
DEVMETHOD(device_probe, wb_probe),
|
||||
DEVMETHOD(device_attach, wb_attach),
|
||||
DEVMETHOD(device_detach, wb_detach),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user