diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index 37ab8660df1f..be86c65cb279 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -164,6 +164,15 @@ init_cy486dx(void)
 #ifdef CPU_SUSP_HLT
 	ccr2 |= CCR2_SUSP_HLT;
 #endif
+
+#ifdef PC98
+	/* Enables WB cache interface pin and Lock NW bit in CR0. */
+	ccr2 |= CCR2_WB | CCR2_LOCK_NW;
+	/* Unlock NW bit in CR0. */
+	write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
+	load_cr0((rcr0() & ~CR0_CD) | CR0_NW);	/* CD = 0, NW = 1 */
+#endif
+
 	write_cyrix_reg(CCR2, ccr2);
 	write_eflags(eflags);
 }
@@ -561,6 +570,12 @@ initializecpu(void)
 		case CPU_M1SC:
 			need_pre_dma_flush = 1;
 			break;
+		case CPU_CY486DX:
+			need_pre_dma_flush = 1;
+#ifdef CPU_I486_ON_386
+			need_post_dma_flush = 1;
+#endif
+			break;
 #endif
 		default:
 			break;
diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c
index 37ab8660df1f..be86c65cb279 100644
--- a/sys/i386/i386/initcpu.c
+++ b/sys/i386/i386/initcpu.c
@@ -164,6 +164,15 @@ init_cy486dx(void)
 #ifdef CPU_SUSP_HLT
 	ccr2 |= CCR2_SUSP_HLT;
 #endif
+
+#ifdef PC98
+	/* Enables WB cache interface pin and Lock NW bit in CR0. */
+	ccr2 |= CCR2_WB | CCR2_LOCK_NW;
+	/* Unlock NW bit in CR0. */
+	write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
+	load_cr0((rcr0() & ~CR0_CD) | CR0_NW);	/* CD = 0, NW = 1 */
+#endif
+
 	write_cyrix_reg(CCR2, ccr2);
 	write_eflags(eflags);
 }
@@ -561,6 +570,12 @@ initializecpu(void)
 		case CPU_M1SC:
 			need_pre_dma_flush = 1;
 			break;
+		case CPU_CY486DX:
+			need_pre_dma_flush = 1;
+#ifdef CPU_I486_ON_386
+			need_post_dma_flush = 1;
+#endif
+			break;
 #endif
 		default:
 			break;