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rk_pll: Add support for mode

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RockChip PLL have two modes controlled by a register, a "slow mode" (the
default one) where the frequency is derived from the 24Mhz oscillator on the
board, and a "normal" one when the pll take it's input from the real PLL output.

Default the mode to normal for all the PLLs.
This commit is contained in:
Emmanuel Vadot 2018-06-14 05:43:45 +00:00
parent b1b521b1d5
commit 1e7af4cc7a
3 changed files with 23 additions and 0 deletions
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10
sys/arm64/rockchip/clk/rk3328_cru.c
View File

@ -512,6 +512,8 @@ static struct rk_clk_pll_def apll = {
.base_offset = 0x00,
.gate_offset = 0x200,
.gate_shift = 0,
.mode_reg = 0x80,
.mode_val = 0x1,
.flags = RK_CLK_PLL_HAVE_GATE,
.frac_rates = rk3328_pll_frac_rates,
};
@ -526,6 +528,8 @@ static struct rk_clk_pll_def dpll = {
.base_offset = 0x20,
.gate_offset = 0x200,
.gate_shift = 1,
.mode_reg = 0x80,
.mode_val = 0x8,
.flags = RK_CLK_PLL_HAVE_GATE,
};
@ -537,6 +541,8 @@ static struct rk_clk_pll_def cpll = {
.parent_cnt = nitems(pll_parents),
},
.base_offset = 0x40,
.mode_reg = 0x80,
.mode_val = 0x80,
.rates = rk3328_pll_rates,
};
@ -550,6 +556,8 @@ static struct rk_clk_pll_def gpll = {
.base_offset = 0x60,
.gate_offset = 0x200,
.gate_shift = 2,
.mode_reg = 0x80,
.mode_val = 0x800,
.flags = RK_CLK_PLL_HAVE_GATE,
.frac_rates = rk3328_pll_frac_rates,
};
@ -564,6 +572,8 @@ static struct rk_clk_pll_def npll = {
.base_offset = 0xa0,
.gate_offset = 0x200,
.gate_shift = 12,
.mode_reg = 0x80,
.mode_val = 0x2,
.flags = RK_CLK_PLL_HAVE_GATE,
.rates = rk3328_pll_rates,
};

10
sys/arm64/rockchip/clk/rk_clk_pll.c
View File

@ -47,6 +47,9 @@ struct rk_clk_pll_sc {
uint32_t gate_offset;
uint32_t gate_shift;
uint32_t mode_reg;
uint32_t mode_val;
uint32_t flags;
struct rk_clk_pll_rate *rates;
@ -221,6 +224,11 @@ rk_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
reg |= rates->frac << RK_CLK_PLL_FRAC_SHIFT;
WRITE4(clk, sc->base_offset + 0x8, reg);
/* Setting to normal mode */
READ4(clk, sc->mode_reg, &reg);
reg |= sc->mode_val << 16 | sc->mode_val;
WRITE4(clk, sc->mode_reg, reg);
/* Reading lock */
for (timeout = 1000; timeout; timeout--) {
READ4(clk, sc->base_offset + 0x4, &reg);
@ -263,6 +271,8 @@ rk_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef)
sc->base_offset = clkdef->base_offset;
sc->gate_offset = clkdef->gate_offset;
sc->gate_shift = clkdef->gate_shift;
sc->mode_reg = clkdef->mode_reg;
sc->mode_val = clkdef->mode_val;
sc->flags = clkdef->flags;
sc->rates = clkdef->rates;
sc->frac_rates = clkdef->frac_rates;

3
sys/arm64/rockchip/clk/rk_clk_pll.h
View File

@ -50,6 +50,9 @@ struct rk_clk_pll_def {
uint32_t gate_offset;
uint32_t gate_shift;
uint32_t mode_reg;
uint32_t mode_val;
uint32_t flags;
struct rk_clk_pll_rate *rates;