Add workaround to get IXP435 NPE-A working: reseting NPE-A after NPE-C
causes both to become inoperative; this apparently was done by the original IAL code as a workaround for IMEM parity errors which we've not seen so just disable the reset. Note this problem does not occur on IXP425 boards. The linux driver does fuse-resets on each NPE but in the order NPE-A < NPE-B < NPE-C (when probing for which NPE's are present/operational); we may want to switch to a similar scheme but for now disable the resets until we see an issue.
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@ -804,20 +804,34 @@ static const uint32_t ixNpeDlCtxtRegResetValues[] = {
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IX_NPEDL_CTXT_REG_RESET_CINDEX,
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};
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#define IX_NPEDL_RESET_NPE_PARITY 0x0800
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#define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF
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#define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF
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#if 0
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/*
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* Reset the NPE and its coprocessor using the
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* fuse bits in the feature control register.
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*/
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static void
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npe_reset(int npeid)
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{
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uint32_t mask = EXP_FCTRL_NPEA << npeid;
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uint32_t v;
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v = ixp4xx_read_feature_bits();
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ixp4xx_write_feature_bits(v &~ mask);
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/* un-fuse and un-reset the NPE & coprocessor */
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ixp4xx_write_feature_bits(v | mask);
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}
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#endif
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static int
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npe_cpu_reset(struct ixpnpe_softc *sc)
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{
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#define N(a) (sizeof(a) / sizeof(a[0]))
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struct ixp425_softc *sa =
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device_get_softc(device_get_parent(sc->sc_dev));
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uint32_t ctxtReg; /* identifies Context Store reg (0-3) */
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uint32_t regAddr;
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uint32_t regVal;
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uint32_t resetNpeParity;
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uint32_t ixNpeConfigCtrlRegVal;
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int i, error = 0;
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@ -935,33 +949,15 @@ npe_cpu_reset(struct ixpnpe_softc *sc)
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/* Reset the Watch-count register */
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npe_reg_write(sc, IX_NPEDL_REG_OFFSET_WC, 0);
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#if 0
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/*
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* WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation
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* XXX Removed because it breaks IXP435 operation; e.g. on Gateworks
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* XXX 2358 boards reseting NPE-A after NPE-C is running causes both
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* XXX npe's to stop working
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*/
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/*
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* Reset the NPE and its coprocessor - to reset internal
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* states and remove parity error. Note this makes no
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* sense based on the documentation. The feature control
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* register always reads back as 0 on the ixp425 and further
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* the bit definition of NPEA/NPEB is off by 1 according to
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* the Intel documention--so we're blindly following the
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* Intel code w/o any real understanding.
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*/
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regVal = EXP_BUS_READ_4(sa, EXP_FCTRL_OFFSET);
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DPRINTFn(2, sc->sc_dev, "%s: FCTRL 0x%x\n", __func__, regVal);
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resetNpeParity =
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IX_NPEDL_RESET_NPE_PARITY << (1 + device_get_unit(sc->sc_dev));
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DPRINTFn(2, sc->sc_dev, "%s: FCTRL fuse parity, write 0x%x\n",
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__func__, regVal | resetNpeParity);
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EXP_BUS_WRITE_4(sa, EXP_FCTRL_OFFSET, regVal | resetNpeParity);
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/* un-fuse and un-reset the NPE & coprocessor */
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DPRINTFn(2, sc->sc_dev, "%s: FCTRL unfuse parity, write 0x%x\n",
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__func__, regVal & resetNpeParity);
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EXP_BUS_WRITE_4(sa, EXP_FCTRL_OFFSET, regVal &~ resetNpeParity);
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npe_reset(sc->sc_npeid);
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#endif
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/*
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* Call NpeMgr function to stop the NPE again after the Feature Control
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* has unfused and Un-Reset the NPE and its associated Coprocessors.
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