Import DTS files from Linux 5.0
This commit is contained in:
Emmanuel Vadot
parent
a31d1ff13c
commit
2131505c51
2
Bindings/.gitignore
vendored
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2
Bindings/.gitignore
vendored
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@ -0,0 +1,2 @@
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*.example.dts
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processed-schema.yaml
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31
Bindings/Makefile
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31
Bindings/Makefile
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@ -0,0 +1,31 @@
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# SPDX-License-Identifier: GPL-2.0
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DT_DOC_CHECKER ?= dt-doc-validate
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DT_EXTRACT_EX ?= dt-extract-example
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DT_MK_SCHEMA ?= dt-mk-schema
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DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u)
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quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
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cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \
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$(DT_EXTRACT_EX) $< > $@
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$(obj)/%.example.dts: $(src)/%.yaml FORCE
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$(call if_changed,chk_binding)
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DT_TMP_SCHEMA := processed-schema.yaml
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extra-y += $(DT_TMP_SCHEMA)
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quiet_cmd_mk_schema = SCHEMA $@
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cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(filter-out FORCE, $^)
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DT_DOCS = $(shell \
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cd $(srctree)/$(src) && \
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find * \( -name '*.yaml' ! -name $(DT_TMP_SCHEMA) \) \
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)
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DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS))
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extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
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extra-y += $(patsubst $(src)/%.yaml,%.example.dtb, $(DT_SCHEMA_FILES))
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$(obj)/$(DT_TMP_SCHEMA): $(DT_SCHEMA_FILES) FORCE
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$(call if_changed,mk_schema)
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@ -1,14 +0,0 @@
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Altera's SoCFPGA platform device tree bindings
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---------------------------------------------
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Boards with Cyclone 5 SoC:
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Required root node properties:
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compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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Boards with Arria 5 SoC:
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Required root node properties:
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compatible = "altr,socfpga-arria5", "altr,socfpga";
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Boards with Arria 10 SoC:
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Required root node properties:
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compatible = "altr,socfpga-arria10", "altr,socfpga";
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20
Bindings/arm/altera.yaml
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20
Bindings/arm/altera.yaml
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@ -0,0 +1,20 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/altera.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Altera's SoCFPGA platform device tree bindings
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maintainers:
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- Dinh Nguyen <dinguyen@kernel.org>
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properties:
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compatible:
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items:
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- enum:
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- altr,socfpga-cyclone5
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- altr,socfpga-arria5
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- altr,socfpga-arria10
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- const: altr,socfpga
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...
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@ -1,11 +0,0 @@
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Altera SOCFPGA Clock Manager
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Required properties:
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- compatible : "altr,clk-mgr"
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- reg : Should contain base address and length for Clock Manager
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Example:
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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};
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31
Bindings/arm/altera/socfpga-clk-manager.yaml
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31
Bindings/arm/altera/socfpga-clk-manager.yaml
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@ -0,0 +1,31 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Altera SOCFPGA Clock Manager
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maintainers:
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- Dinh Nguyen <dinguyen@kernel.org>
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description: test
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properties:
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compatible:
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items:
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- const: altr,clk-mgr
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reg:
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maxItems: 1
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required:
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- compatible
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examples:
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- |
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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};
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...
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@ -17,4 +17,11 @@ Required sub-node properties:
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- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
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memory on Amlogic GXBB SoC.
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Sensor bindings for the sensors based on SCPI Message Protocol
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--------------------------------------------------------------
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SCPI provides an API to access the various sensors on the SoC.
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Required properties:
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- compatible : should be "amlogic,meson-gxbb-scpi-sensors".
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[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
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@ -91,8 +91,10 @@ Board compatible values (alphabetically, grouped by SoC):
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- "amlogic,p230" (Meson gxl s905d)
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- "amlogic,p231" (Meson gxl s905d)
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- "phicomm,n1" (Meson gxl s905d)
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- "amlogic,p241" (Meson gxl s805x)
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- "libretech,aml-s805x-ac" (Meson gxl s805x)
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- "amlogic,p281" (Meson gxl s905w)
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- "oranth,tx3-mini" (Meson gxl s905w)
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@ -158,14 +158,24 @@ Security Module (SECUMOD)
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The Security Module macrocell provides all necessary secure functions to avoid
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voltage, temperature, frequency and mechanical attacks on the chip. It also
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embeds secure memories that can be scrambled
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embeds secure memories that can be scrambled.
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The Security Module also offers the PIOBU pins which can be used as GPIO pins.
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Note that they maintain their voltage during Backup/Self-refresh.
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required properties:
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- compatible: Should be "atmel,<chip>-secumod", "syscon".
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<chip> can be "sama5d2".
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- reg: Should contain registers location and length
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- gpio-controller: Marks the port as GPIO controller.
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- #gpio-cells: There are 2. The pin number is the
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first, the second represents additional
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parameters such as GPIO_ACTIVE_HIGH/LOW.
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secumod@fc040000 {
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compatible = "atmel,sama5d2-secumod", "syscon";
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reg = <0xfc040000 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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@ -1,15 +0,0 @@
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Calxeda Platforms Device Tree Bindings
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-----------------------------------------------
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Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the
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following properties.
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Required root node properties:
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- compatible = "calxeda,highbank";
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Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
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properties.
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Required root node properties:
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- compatible = "calxeda,ecx-2000";
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22
Bindings/arm/calxeda.yaml
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22
Bindings/arm/calxeda.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/calxeda.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Calxeda Platforms Device Tree Bindings
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maintainers:
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- Rob Herring <robh@kernel.org>
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description: |+
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Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
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or Cortex-A15 based ECX-2000 SOCs
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properties:
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$nodename:
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const: '/'
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compatible:
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items:
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- enum:
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- calxeda,highbank
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- calxeda,ecx-2000
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@ -235,4 +235,4 @@ cpus {
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===========================================
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[1] ARM Linux Kernel documentation - CPUs bindings
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Documentation/devicetree/bindings/arm/cpus.txt
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Documentation/devicetree/bindings/arm/cpus.yaml
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@ -1,490 +0,0 @@
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=================
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ARM CPUs bindings
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=================
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The device tree allows to describe the layout of CPUs in a system through
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the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
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defining properties for every cpu.
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Bindings for CPU nodes follow the Devicetree Specification, available from:
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https://www.devicetree.org/specifications/
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with updates for 32-bit and 64-bit ARM systems provided in this document.
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================================
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Convention used in this document
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================================
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This document follows the conventions described in the Devicetree
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Specification, with the addition:
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- square brackets define bitfields, eg reg[7:0] value of the bitfield in
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the reg property contained in bits 7 down to 0
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=====================================
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cpus and cpu node bindings definition
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=====================================
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The ARM architecture, in accordance with the Devicetree Specification,
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requires the cpus and cpu nodes to be present and contain the properties
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described below.
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- cpus node
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Description: Container of cpu nodes
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The node name must be "cpus".
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A cpus node must define the following properties:
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition depends on ARM architecture version and
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configuration:
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# On uniprocessor ARM architectures previous to v7
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value must be 1, to enable a simple enumeration
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scheme for processors that do not have a HW CPU
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identification register.
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# On 32-bit ARM 11 MPcore, ARM v7 or later systems
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value must be 1, that corresponds to CPUID/MPIDR
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registers sizes.
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# On ARM v8 64-bit systems value should be set to 2,
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that corresponds to the MPIDR_EL1 register size.
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If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
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in the system, #address-cells can be set to 1, since
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MPIDR_EL1[63:32] bits are not used for CPUs
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identification.
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: must be set to 0
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- cpu node
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Description: Describes a CPU in an ARM based system
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PROPERTIES
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- device_type
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Usage: required
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Value type: <string>
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Definition: must be "cpu"
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- reg
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Usage and definition depend on ARM architecture version and
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configuration:
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# On uniprocessor ARM architectures previous to v7
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this property is required and must be set to 0.
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# On ARM 11 MPcore based systems this property is
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required and matches the CPUID[11:0] register bits.
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Bits [11:0] in the reg cell must be set to
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bits [11:0] in CPU ID register.
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All other bits in the reg cell must be set to 0.
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# On 32-bit ARM v7 or later systems this property is
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required and matches the CPU MPIDR[23:0] register
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bits.
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Bits [23:0] in the reg cell must be set to
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bits [23:0] in MPIDR.
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All other bits in the reg cell must be set to 0.
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# On ARM v8 64-bit systems this property is required
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and matches the MPIDR_EL1 register affinity bits.
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* If cpus node's #address-cells property is set to 2
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The first reg cell bits [7:0] must be set to
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bits [39:32] of MPIDR_EL1.
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The second reg cell bits [23:0] must be set to
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bits [23:0] of MPIDR_EL1.
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* If cpus node's #address-cells property is set to 1
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The reg cell bits [23:0] must be set to bits [23:0]
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of MPIDR_EL1.
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All other bits in the reg cells must be set to 0.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: should be one of:
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"arm,arm710t"
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"arm,arm720t"
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"arm,arm740t"
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"arm,arm7ej-s"
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"arm,arm7tdmi"
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"arm,arm7tdmi-s"
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"arm,arm9es"
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"arm,arm9ej-s"
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"arm,arm920t"
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"arm,arm922t"
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"arm,arm925"
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"arm,arm926e-s"
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"arm,arm926ej-s"
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"arm,arm940t"
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"arm,arm946e-s"
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"arm,arm966e-s"
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"arm,arm968e-s"
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"arm,arm9tdmi"
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"arm,arm1020e"
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"arm,arm1020t"
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"arm,arm1022e"
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"arm,arm1026ej-s"
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"arm,arm1136j-s"
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"arm,arm1136jf-s"
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"arm,arm1156t2-s"
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"arm,arm1156t2f-s"
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"arm,arm1176jzf"
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"arm,arm1176jz-s"
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"arm,arm1176jzf-s"
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"arm,arm11mpcore"
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"arm,cortex-a5"
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"arm,cortex-a7"
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"arm,cortex-a8"
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"arm,cortex-a9"
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"arm,cortex-a12"
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"arm,cortex-a15"
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"arm,cortex-a17"
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"arm,cortex-a53"
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"arm,cortex-a57"
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"arm,cortex-a72"
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"arm,cortex-a73"
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"arm,cortex-m0"
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"arm,cortex-m0+"
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"arm,cortex-m1"
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"arm,cortex-m3"
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"arm,cortex-m4"
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"arm,cortex-r4"
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"arm,cortex-r5"
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"arm,cortex-r7"
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"brcm,brahma-b15"
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"brcm,brahma-b53"
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"brcm,vulcan"
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"cavium,thunder"
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"cavium,thunder2"
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"faraday,fa526"
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"intel,sa110"
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"intel,sa1100"
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"marvell,feroceon"
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"marvell,mohawk"
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"marvell,pj4a"
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"marvell,pj4b"
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"marvell,sheeva-v5"
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"nvidia,tegra132-denver"
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"nvidia,tegra186-denver"
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"nvidia,tegra194-carmel"
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"qcom,krait"
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"qcom,kryo"
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"qcom,kryo385"
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"qcom,scorpion"
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- enable-method
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Value type: <stringlist>
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Usage and definition depend on ARM architecture version.
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# On ARM v8 64-bit this property is required and must
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be one of:
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"psci"
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"spin-table"
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# On ARM 32-bit systems this property is optional and
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can be one of:
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"actions,s500-smp"
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"allwinner,sun6i-a31"
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"allwinner,sun8i-a23"
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"allwinner,sun9i-a80-smp"
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"amlogic,meson8-smp"
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"amlogic,meson8b-smp"
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"arm,realview-smp"
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"brcm,bcm11351-cpu-method"
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"brcm,bcm23550"
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"brcm,bcm2836-smp"
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"brcm,bcm-nsp-smp"
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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"marvell,armada-380-smp"
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"marvell,armada-390-smp"
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"marvell,armada-xp-smp"
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"marvell,98dx3236-smp"
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"mediatek,mt6589-smp"
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"mediatek,mt81xx-tz-smp"
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"qcom,gcc-msm8660"
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"qcom,kpss-acc-v1"
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"qcom,kpss-acc-v2"
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"renesas,apmu"
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"renesas,r9a06g032-smp"
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"rockchip,rk3036-smp"
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"rockchip,rk3066-smp"
|
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"ste,dbx500-smp"
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- cpu-release-addr
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Usage: required for systems that have an "enable-method"
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property value of "spin-table".
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Value type: <prop-encoded-array>
|
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Definition:
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# On ARM v8 64-bit systems must be a two cell
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property identifying a 64-bit zero-initialised
|
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memory location.
|
||||
|
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- qcom,saw
|
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Usage: required for systems that have an "enable-method"
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property value of "qcom,kpss-acc-v1" or
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"qcom,kpss-acc-v2"
|
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Value type: <phandle>
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Definition: Specifies the SAW[1] node associated with this CPU.
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- qcom,acc
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Usage: required for systems that have an "enable-method"
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property value of "qcom,kpss-acc-v1" or
|
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"qcom,kpss-acc-v2"
|
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Value type: <phandle>
|
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Definition: Specifies the ACC[2] node associated with this CPU.
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- cpu-idle-states
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Usage: Optional
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Value type: <prop-encoded-array>
|
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Definition:
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# List of phandles to idle state nodes supported
|
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by this cpu [3].
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||||
|
||||
- capacity-dmips-mhz
|
||||
Usage: Optional
|
||||
Value type: <u32>
|
||||
Definition:
|
||||
# u32 value representing CPU capacity [4] in
|
||||
DMIPS/MHz, relative to highest capacity-dmips-mhz
|
||||
in the system.
|
||||
|
||||
- rockchip,pmu
|
||||
Usage: optional for systems that have an "enable-method"
|
||||
property value of "rockchip,rk3066-smp"
|
||||
While optional, it is the preferred way to get access to
|
||||
the cpu-core power-domains.
|
||||
Value type: <phandle>
|
||||
Definition: Specifies the syscon node controlling the cpu core
|
||||
power domains.
|
||||
|
||||
- dynamic-power-coefficient
|
||||
Usage: optional
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A u32 value that represents the running time dynamic
|
||||
power coefficient in units of uW/MHz/V^2. The
|
||||
coefficient can either be calculated from power
|
||||
measurements or derived by analysis.
|
||||
|
||||
The dynamic power consumption of the CPU is
|
||||
proportional to the square of the Voltage (V) and
|
||||
the clock frequency (f). The coefficient is used to
|
||||
calculate the dynamic power as below -
|
||||
|
||||
Pdyn = dynamic-power-coefficient * V^2 * f
|
||||
|
||||
where voltage is in V, frequency is in MHz.
|
||||
|
||||
Example 1 (dual-cluster big.LITTLE system 32-bit):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
};
|
||||
};
|
||||
|
||||
Example 2 (Cortex-A8 uniprocessor 32-bit system):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm926ej-s";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
Example 4 (ARM Cortex-A57 64-bit system):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <2>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
--
|
||||
[1] arm/msm/qcom,saw2.txt
|
||||
[2] arm/msm/qcom,kpss-acc.txt
|
||||
[3] ARM Linux kernel documentation - idle states bindings
|
||||
Documentation/devicetree/bindings/arm/idle-states.txt
|
||||
[4] ARM Linux kernel documentation - cpu capacity bindings
|
||||
Documentation/devicetree/bindings/arm/cpu-capacity.txt
|
||||
507
Bindings/arm/cpus.yaml
Normal file
507
Bindings/arm/cpus.yaml
Normal file
@ -0,0 +1,507 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/cpus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM CPUs bindings
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
|
||||
description: |+
|
||||
The device tree allows to describe the layout of CPUs in a system through
|
||||
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
|
||||
defining properties for every cpu.
|
||||
|
||||
Bindings for CPU nodes follow the Devicetree Specification, available from:
|
||||
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
with updates for 32-bit and 64-bit ARM systems provided in this document.
|
||||
|
||||
================================
|
||||
Convention used in this document
|
||||
================================
|
||||
|
||||
This document follows the conventions described in the Devicetree
|
||||
Specification, with the addition:
|
||||
|
||||
- square brackets define bitfields, eg reg[7:0] value of the bitfield in
|
||||
the reg property contained in bits 7 down to 0
|
||||
|
||||
=====================================
|
||||
cpus and cpu node bindings definition
|
||||
=====================================
|
||||
|
||||
The ARM architecture, in accordance with the Devicetree Specification,
|
||||
requires the cpus and cpu nodes to be present and contain the properties
|
||||
described below.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: cpus
|
||||
description: Container of cpu nodes
|
||||
|
||||
'#address-cells':
|
||||
enum: [1, 2]
|
||||
description: |
|
||||
Definition depends on ARM architecture version and configuration:
|
||||
|
||||
On uniprocessor ARM architectures previous to v7
|
||||
value must be 1, to enable a simple enumeration
|
||||
scheme for processors that do not have a HW CPU
|
||||
identification register.
|
||||
On 32-bit ARM 11 MPcore, ARM v7 or later systems
|
||||
value must be 1, that corresponds to CPUID/MPIDR
|
||||
registers sizes.
|
||||
On ARM v8 64-bit systems value should be set to 2,
|
||||
that corresponds to the MPIDR_EL1 register size.
|
||||
If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
|
||||
in the system, #address-cells can be set to 1, since
|
||||
MPIDR_EL1[63:32] bits are not used for CPUs
|
||||
identification.
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
'^cpu@[0-9a-f]+$':
|
||||
properties:
|
||||
device_type:
|
||||
const: cpu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: |
|
||||
Usage and definition depend on ARM architecture version and
|
||||
configuration:
|
||||
|
||||
On uniprocessor ARM architectures previous to v7
|
||||
this property is required and must be set to 0.
|
||||
|
||||
On ARM 11 MPcore based systems this property is
|
||||
required and matches the CPUID[11:0] register bits.
|
||||
|
||||
Bits [11:0] in the reg cell must be set to
|
||||
bits [11:0] in CPU ID register.
|
||||
|
||||
All other bits in the reg cell must be set to 0.
|
||||
|
||||
On 32-bit ARM v7 or later systems this property is
|
||||
required and matches the CPU MPIDR[23:0] register
|
||||
bits.
|
||||
|
||||
Bits [23:0] in the reg cell must be set to
|
||||
bits [23:0] in MPIDR.
|
||||
|
||||
All other bits in the reg cell must be set to 0.
|
||||
|
||||
On ARM v8 64-bit systems this property is required
|
||||
and matches the MPIDR_EL1 register affinity bits.
|
||||
|
||||
* If cpus node's #address-cells property is set to 2
|
||||
|
||||
The first reg cell bits [7:0] must be set to
|
||||
bits [39:32] of MPIDR_EL1.
|
||||
|
||||
The second reg cell bits [23:0] must be set to
|
||||
bits [23:0] of MPIDR_EL1.
|
||||
|
||||
* If cpus node's #address-cells property is set to 1
|
||||
|
||||
The reg cell bits [23:0] must be set to bits [23:0]
|
||||
of MPIDR_EL1.
|
||||
|
||||
All other bits in the reg cells must be set to 0.
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- arm,arm710t
|
||||
- arm,arm720t
|
||||
- arm,arm740t
|
||||
- arm,arm7ej-s
|
||||
- arm,arm7tdmi
|
||||
- arm,arm7tdmi-s
|
||||
- arm,arm9es
|
||||
- arm,arm9ej-s
|
||||
- arm,arm920t
|
||||
- arm,arm922t
|
||||
- arm,arm925
|
||||
- arm,arm926e-s
|
||||
- arm,arm926ej-s
|
||||
- arm,arm940t
|
||||
- arm,arm946e-s
|
||||
- arm,arm966e-s
|
||||
- arm,arm968e-s
|
||||
- arm,arm9tdmi
|
||||
- arm,arm1020e
|
||||
- arm,arm1020t
|
||||
- arm,arm1022e
|
||||
- arm,arm1026ej-s
|
||||
- arm,arm1136j-s
|
||||
- arm,arm1136jf-s
|
||||
- arm,arm1156t2-s
|
||||
- arm,arm1156t2f-s
|
||||
- arm,arm1176jzf
|
||||
- arm,arm1176jz-s
|
||||
- arm,arm1176jzf-s
|
||||
- arm,arm11mpcore
|
||||
- arm,armv8 # Only for s/w models
|
||||
- arm,cortex-a5
|
||||
- arm,cortex-a7
|
||||
- arm,cortex-a8
|
||||
- arm,cortex-a9
|
||||
- arm,cortex-a12
|
||||
- arm,cortex-a15
|
||||
- arm,cortex-a17
|
||||
- arm,cortex-a53
|
||||
- arm,cortex-a57
|
||||
- arm,cortex-a72
|
||||
- arm,cortex-a73
|
||||
- arm,cortex-m0
|
||||
- arm,cortex-m0+
|
||||
- arm,cortex-m1
|
||||
- arm,cortex-m3
|
||||
- arm,cortex-m4
|
||||
- arm,cortex-r4
|
||||
- arm,cortex-r5
|
||||
- arm,cortex-r7
|
||||
- brcm,brahma-b15
|
||||
- brcm,brahma-b53
|
||||
- brcm,vulcan
|
||||
- cavium,thunder
|
||||
- cavium,thunder2
|
||||
- faraday,fa526
|
||||
- intel,sa110
|
||||
- intel,sa1100
|
||||
- marvell,feroceon
|
||||
- marvell,mohawk
|
||||
- marvell,pj4a
|
||||
- marvell,pj4b
|
||||
- marvell,sheeva-v5
|
||||
- marvell,sheeva-v7
|
||||
- nvidia,tegra132-denver
|
||||
- nvidia,tegra186-denver
|
||||
- nvidia,tegra194-carmel
|
||||
- qcom,krait
|
||||
- qcom,kryo
|
||||
- qcom,kryo385
|
||||
- qcom,scorpion
|
||||
|
||||
enable-method:
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/string'
|
||||
- oneOf:
|
||||
# On ARM v8 64-bit this property is required
|
||||
- enum:
|
||||
- psci
|
||||
- spin-table
|
||||
# On ARM 32-bit systems this property is optional
|
||||
- enum:
|
||||
- actions,s500-smp
|
||||
- allwinner,sun6i-a31
|
||||
- allwinner,sun8i-a23
|
||||
- allwinner,sun9i-a80-smp
|
||||
- allwinner,sun8i-a83t-smp
|
||||
- amlogic,meson8-smp
|
||||
- amlogic,meson8b-smp
|
||||
- arm,realview-smp
|
||||
- brcm,bcm11351-cpu-method
|
||||
- brcm,bcm23550
|
||||
- brcm,bcm2836-smp
|
||||
- brcm,bcm63138
|
||||
- brcm,bcm-nsp-smp
|
||||
- brcm,brahma-b15
|
||||
- marvell,armada-375-smp
|
||||
- marvell,armada-380-smp
|
||||
- marvell,armada-390-smp
|
||||
- marvell,armada-xp-smp
|
||||
- marvell,98dx3236-smp
|
||||
- mediatek,mt6589-smp
|
||||
- mediatek,mt81xx-tz-smp
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,kpss-acc-v1
|
||||
- qcom,kpss-acc-v2
|
||||
- renesas,apmu
|
||||
- renesas,r9a06g032-smp
|
||||
- rockchip,rk3036-smp
|
||||
- rockchip,rk3066-smp
|
||||
- ste,dbx500-smp
|
||||
|
||||
cpu-release-addr:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint64'
|
||||
|
||||
description:
|
||||
Required for systems that have an "enable-method"
|
||||
property value of "spin-table".
|
||||
On ARM v8 64-bit systems must be a two cell
|
||||
property identifying a 64-bit zero-initialised
|
||||
memory location.
|
||||
|
||||
cpu-idle-states:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
description: |
|
||||
List of phandles to idle state nodes supported
|
||||
by this cpu (see ./idle-states.txt).
|
||||
|
||||
capacity-dmips-mhz:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description:
|
||||
u32 value representing CPU capacity (see ./cpu-capacity.txt) in
|
||||
DMIPS/MHz, relative to highest capacity-dmips-mhz
|
||||
in the system.
|
||||
|
||||
dynamic-power-coefficient:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description:
|
||||
A u32 value that represents the running time dynamic
|
||||
power coefficient in units of uW/MHz/V^2. The
|
||||
coefficient can either be calculated from power
|
||||
measurements or derived by analysis.
|
||||
|
||||
The dynamic power consumption of the CPU is
|
||||
proportional to the square of the Voltage (V) and
|
||||
the clock frequency (f). The coefficient is used to
|
||||
calculate the dynamic power as below -
|
||||
|
||||
Pdyn = dynamic-power-coefficient * V^2 * f
|
||||
|
||||
where voltage is in V, frequency is in MHz.
|
||||
|
||||
qcom,saw:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the SAW* node associated with this CPU.
|
||||
|
||||
Required for systems that have an "enable-method" property
|
||||
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
|
||||
|
||||
* arm/msm/qcom,saw2.txt
|
||||
|
||||
qcom,acc:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the ACC* node associated with this CPU.
|
||||
|
||||
Required for systems that have an "enable-method" property
|
||||
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
|
||||
|
||||
* arm/msm/qcom,kpss-acc.txt
|
||||
|
||||
rockchip,pmu:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the syscon node controlling the cpu core power domains.
|
||||
|
||||
Optional for systems that have an "enable-method"
|
||||
property value of "rockchip,rk3066-smp"
|
||||
While optional, it is the preferred way to get access to
|
||||
the cpu-core power-domains.
|
||||
|
||||
required:
|
||||
- device_type
|
||||
- reg
|
||||
- compatible
|
||||
|
||||
dependencies:
|
||||
cpu-release-addr: [enable-method]
|
||||
rockchip,pmu: [enable-method]
|
||||
|
||||
required:
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 2 (Cortex-A8 uniprocessor 32-bit system):
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm926ej-s";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 4 (ARM Cortex-A57 64-bit system):
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <2>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -1,25 +0,0 @@
|
||||
Texas Instruments DaVinci Platforms Device Tree Bindings
|
||||
--------------------------------------------------------
|
||||
|
||||
DA850/OMAP-L138/AM18x Evaluation Module (EVM) board
|
||||
Required root node properties:
|
||||
- compatible = "ti,da850-evm", "ti,da850";
|
||||
|
||||
DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board
|
||||
Required root node properties:
|
||||
- compatible = "ti,da850-lcdk", "ti,da850";
|
||||
|
||||
EnBW AM1808 based CMC board
|
||||
Required root node properties:
|
||||
- compatible = "enbw,cmc", "ti,da850;
|
||||
|
||||
LEGO MINDSTORMS EV3 (AM1808 based)
|
||||
Required root node properties:
|
||||
- compatible = "lego,ev3", "ti,da850";
|
||||
|
||||
Generic DaVinci Boards
|
||||
----------------------
|
||||
|
||||
DA850/OMAP-L138/AM18x generic board
|
||||
Required root node properties:
|
||||
- compatible = "ti,da850";
|
||||
12
Bindings/arm/emtrion.txt
Normal file
12
Bindings/arm/emtrion.txt
Normal file
@ -0,0 +1,12 @@
|
||||
Emtrion Devicetree Bindings
|
||||
===========================
|
||||
|
||||
emCON Series:
|
||||
-------------
|
||||
|
||||
Required root node properties
|
||||
- compatible:
|
||||
- "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM
|
||||
- "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base
|
||||
- "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM
|
||||
- "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base
|
||||
23
Bindings/arm/freescale/fsl,imx7ulp-pm.txt
Normal file
23
Bindings/arm/freescale/fsl,imx7ulp-pm.txt
Normal file
@ -0,0 +1,23 @@
|
||||
Freescale i.MX7ULP Power Management Components
|
||||
----------------------------------------------
|
||||
|
||||
The Multi-System Mode Controller (MSMC) is responsible for sequencing
|
||||
the MCU into and out of all stop and run power modes. Specifically, it
|
||||
monitors events to trigger transitions between power modes while
|
||||
controlling the power, clocks, and memories of the MCU to achieve the
|
||||
power consumption and functionality of that mode.
|
||||
|
||||
The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
|
||||
Standby modes for either Cortex family. Run, Wait, and Stop are the
|
||||
common terms used for the primary operating modes of Kinetis
|
||||
microcontrollers.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx7ulp-smc1".
|
||||
- reg: Specifies base physical address and size of the register sets.
|
||||
|
||||
Example:
|
||||
smc1: smc1@40410000 {
|
||||
compatible = "fsl,imx7ulp-smc1";
|
||||
reg = <0x40410000 0x1000>;
|
||||
};
|
||||
@ -58,19 +58,11 @@ This binding for the SCU power domain providers uses the generic power
|
||||
domain binding[2].
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,scu-pd".
|
||||
- #address-cells: Should be 1.
|
||||
- #size-cells: Should be 0.
|
||||
|
||||
Required properties for power domain sub nodes:
|
||||
- #power-domain-cells: Must be 0.
|
||||
|
||||
Optional Properties:
|
||||
- reg: Resource ID of this power domain.
|
||||
No exist means uncontrollable by user.
|
||||
- compatible: Should be "fsl,imx8qxp-scu-pd".
|
||||
- #power-domain-cells: Must be 1. Contains the Resource ID used by
|
||||
SCU commands.
|
||||
See detailed Resource ID list from:
|
||||
include/dt-bindings/power/imx-rsrc.h
|
||||
- power-domains: phandle pointing to the parent power domain.
|
||||
include/dt-bindings/firmware/imx/rsrc.h
|
||||
|
||||
Clock bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
@ -96,13 +88,16 @@ Pinctrl bindings based on SCU Message Protocol
|
||||
This binding uses the i.MX common pinctrl binding[3].
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8qxp-iomuxc".
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8qm-iomuxc",
|
||||
"fsl,imx8qxp-iomuxc".
|
||||
|
||||
Required properties for Pinctrl sub nodes:
|
||||
- fsl,pins: Each entry consists of 3 integers which represents
|
||||
the mux and config setting for one pin. The first 2
|
||||
integers <pin_id mux_mode> are specified using a
|
||||
PIN_FUNC_ID macro, which can be found in
|
||||
<dt-bindings/pinctrl/pads-imx8qm.h>,
|
||||
<dt-bindings/pinctrl/pads-imx8qxp.h>.
|
||||
The last integer CONFIG is the pad setting value like
|
||||
pull-up on this pin.
|
||||
@ -114,6 +109,12 @@ Required properties for Pinctrl sub nodes:
|
||||
[2] Documentation/devicetree/bindings/power/power_domain.txt
|
||||
[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
|
||||
|
||||
RTC bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "fsl,imx8qxp-sc-rtc";
|
||||
|
||||
Example (imx8qxp):
|
||||
-------------
|
||||
lsio_mu1: mailbox@5d1c0000 {
|
||||
@ -152,22 +153,13 @@ firmware {
|
||||
...
|
||||
};
|
||||
|
||||
imx8qx-pm {
|
||||
compatible = "fsl,scu-pd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pd: imx8qx-pd {
|
||||
compatible = "fsl,imx8qxp-scu-pd";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pd_dma: dma-power-domain {
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
pd_dma_lpuart0: dma-lpuart0@57 {
|
||||
reg = <SC_R_UART_0>;
|
||||
#power-domain-cells = <0>;
|
||||
power-domains = <&pd_dma>;
|
||||
};
|
||||
...
|
||||
};
|
||||
...
|
||||
rtc: rtc {
|
||||
compatible = "fsl,imx8qxp-sc-rtc";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -179,5 +171,5 @@ serial@5a060000 {
|
||||
clocks = <&clk IMX8QXP_UART0_CLK>,
|
||||
<&clk IMX8QXP_UART0_IPG_CLK>;
|
||||
clock-names = "per", "ipg";
|
||||
power-domains = <&pd_dma_lpuart0>;
|
||||
power-domains = <&pd IMX_SC_R_UART_0>;
|
||||
};
|
||||
|
||||
@ -101,6 +101,10 @@ i.MX7 SabreSD Board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx7d-sdb", "fsl,imx7d";
|
||||
|
||||
i.MX7ULP Evaluation Kit
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
|
||||
|
||||
Generic i.MX boards
|
||||
-------------------
|
||||
|
||||
@ -123,6 +127,10 @@ i.MX6q generic board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx6q";
|
||||
|
||||
i.MX7ULP generic board
|
||||
Required root node properties:
|
||||
- compatible = "fsl,imx7ulp";
|
||||
|
||||
Freescale Vybrid Platform Device Tree Bindings
|
||||
----------------------------------------------
|
||||
|
||||
|
||||
@ -142,7 +142,7 @@ characterised by the following graph:
|
||||
|
||||
The graph is split in two parts delimited by time 1ms on the X-axis.
|
||||
The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
|
||||
and denotes the energy costs incurred whilst entering and leaving the idle
|
||||
and denotes the energy costs incurred while entering and leaving the idle
|
||||
state.
|
||||
The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
|
||||
shallower slope and essentially represents the energy consumption of the idle
|
||||
@ -684,7 +684,7 @@ cpus {
|
||||
===========================================
|
||||
|
||||
[1] ARM Linux Kernel documentation - CPUs bindings
|
||||
Documentation/devicetree/bindings/arm/cpus.txt
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
|
||||
[2] ARM Linux Kernel documentation - PSCI bindings
|
||||
Documentation/devicetree/bindings/arm/psci.txt
|
||||
|
||||
@ -114,12 +114,17 @@ Documentation/devicetree/bindings/thermal/thermal.txt
|
||||
The thermal IP can probe the temperature all around the processor. It
|
||||
may feature several channels, each of them wired to one sensor.
|
||||
|
||||
It is possible to setup an overheat interrupt by giving at least one
|
||||
critical point to any subnode of the thermal-zone node.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be one of:
|
||||
* marvell,armada-ap806-thermal
|
||||
- reg: register range associated with the thermal functions.
|
||||
|
||||
Optional properties:
|
||||
- interrupts: overheat interrupt handle. Should point to line 18 of the
|
||||
SEI irqchip. See interrupt-controller/interrupts.txt
|
||||
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
|
||||
to this IP and represents the channel ID. There is one sensor per
|
||||
channel. O refers to the thermal IP internal channel, while positive
|
||||
@ -133,6 +138,8 @@ ap_syscon1: system-controller@6f8000 {
|
||||
ap_thermal: thermal-sensor@80 {
|
||||
compatible = "marvell,armada-ap806-thermal";
|
||||
reg = <0x80 0x10>;
|
||||
interrupt-parent = <&sei>;
|
||||
interrupts = <18>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -199,6 +199,9 @@ Thermal:
|
||||
The thermal IP can probe the temperature all around the processor. It
|
||||
may feature several channels, each of them wired to one sensor.
|
||||
|
||||
It is possible to setup an overheat interrupt by giving at least one
|
||||
critical point to any subnode of the thermal-zone node.
|
||||
|
||||
For common binding part and usage, refer to
|
||||
Documentation/devicetree/bindings/thermal/thermal.txt
|
||||
|
||||
@ -208,6 +211,11 @@ Required properties:
|
||||
- reg: register range associated with the thermal functions.
|
||||
|
||||
Optional properties:
|
||||
- interrupts-extended: overheat interrupt handle. Should point to
|
||||
a line of the ICU-SEI irqchip (116 is what is usually used by the
|
||||
firmware). The ICU-SEI will redirect towards interrupt line #37 of the
|
||||
AP SEI which is shared across all CPs.
|
||||
See interrupt-controller/interrupts.txt
|
||||
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
|
||||
to this IP and represents the channel ID. There is one sensor per
|
||||
channel. O refers to the thermal IP internal channel.
|
||||
@ -220,6 +228,7 @@ CP110_LABEL(syscon1): system-controller@6f8000 {
|
||||
CP110_LABEL(thermal): thermal-sensor@70 {
|
||||
compatible = "marvell,armada-cp110-thermal";
|
||||
reg = <0x70 0x10>;
|
||||
interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -11,6 +11,7 @@ Required Properties:
|
||||
- "mediatek,mt6797-apmixedsys"
|
||||
- "mediatek,mt7622-apmixedsys"
|
||||
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
|
||||
- "mediatek,mt7629-apmixedsys"
|
||||
- "mediatek,mt8135-apmixedsys"
|
||||
- "mediatek,mt8173-apmixedsys"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
@ -9,6 +9,7 @@ Required Properties:
|
||||
- "mediatek,mt2701-ethsys", "syscon"
|
||||
- "mediatek,mt7622-ethsys", "syscon"
|
||||
- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
|
||||
- "mediatek,mt7629-ethsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
- #reset-cells: Must be 1
|
||||
|
||||
|
||||
@ -12,6 +12,7 @@ Required Properties:
|
||||
- "mediatek,mt6797-infracfg", "syscon"
|
||||
- "mediatek,mt7622-infracfg", "syscon"
|
||||
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
|
||||
- "mediatek,mt7629-infracfg", "syscon"
|
||||
- "mediatek,mt8135-infracfg", "syscon"
|
||||
- "mediatek,mt8173-infracfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt7622-pciesys", "syscon"
|
||||
- "mediatek,mt7629-pciesys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
- #reset-cells: Must be 1
|
||||
|
||||
|
||||
@ -11,6 +11,7 @@ Required Properties:
|
||||
- "mediatek,mt2712-pericfg", "syscon"
|
||||
- "mediatek,mt7622-pericfg", "syscon"
|
||||
- "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
|
||||
- "mediatek,mt7629-pericfg", "syscon"
|
||||
- "mediatek,mt8135-pericfg", "syscon"
|
||||
- "mediatek,mt8173-pericfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt7622-sgmiisys", "syscon"
|
||||
- "mediatek,mt7629-sgmiisys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The SGMIISYS controller uses the common clk binding from
|
||||
|
||||
@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt7622-ssusbsys", "syscon"
|
||||
- "mediatek,mt7629-ssusbsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
- #reset-cells: Must be 1
|
||||
|
||||
|
||||
@ -11,6 +11,7 @@ Required Properties:
|
||||
- "mediatek,mt6797-topckgen"
|
||||
- "mediatek,mt7622-topckgen"
|
||||
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
|
||||
- "mediatek,mt7629-topckgen"
|
||||
- "mediatek,mt8135-topckgen"
|
||||
- "mediatek,mt8173-topckgen"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
@ -11,4 +11,4 @@ Required root node properties:
|
||||
|
||||
MMP2 Brownstone Board
|
||||
Required root node properties:
|
||||
- compatible = "mrvl,mmp2-brownstone";
|
||||
- compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
TI-NSPIRE calculators
|
||||
|
||||
Required properties:
|
||||
- compatible: Compatible property value should contain "ti,nspire".
|
||||
CX models should have "ti,nspire-cx"
|
||||
Touchpad models should have "ti,nspire-tp"
|
||||
Clickpad models should have "ti,nspire-clp"
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
model = "TI-NSPIRE CX";
|
||||
compatible = "ti,nspire-cx";
|
||||
...
|
||||
@ -1,46 +0,0 @@
|
||||
* ARM Primecell Peripherals
|
||||
|
||||
ARM, Ltd. Primecell peripherals have a standard id register that can be used to
|
||||
identify the peripheral type, vendor, and revision. This value can be used for
|
||||
driver matching.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be a specific name for the peripheral and
|
||||
"arm,primecell". The specific name will match the ARM
|
||||
engineering name for the logic block in the form: "arm,pl???"
|
||||
|
||||
Optional properties:
|
||||
|
||||
- arm,primecell-periphid : Value to override the h/w value with
|
||||
- clocks : From common clock binding. First clock is phandle to clock for apb
|
||||
pclk. Additional clocks are optional and specific to those peripherals.
|
||||
- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.
|
||||
- dmas : From common DMA binding. If present, refers to one or more dma channels.
|
||||
- dma-names : From common DMA binding, needs to match the 'dmas' property.
|
||||
Devices with exactly one receive and transmit channel shall name
|
||||
these "rx" and "tx", respectively.
|
||||
- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
|
||||
- pinctrl-names : Names corresponding to the numbered pinctrl states
|
||||
- interrupts : one or more interrupt specifiers
|
||||
- interrupt-names : names corresponding to the interrupts properties
|
||||
|
||||
Example:
|
||||
|
||||
serial@fff36000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00341011>;
|
||||
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
dmas = <&dma-controller 4>, <&dma-controller 5>;
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
|
||||
pinctrl-1 = <&uart0_sleep_mode>;
|
||||
pinctrl-names = "default","sleep";
|
||||
|
||||
interrupts = <0 11 0x4>;
|
||||
};
|
||||
|
||||
36
Bindings/arm/primecell.yaml
Normal file
36
Bindings/arm/primecell.yaml
Normal file
@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/primecell.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Primecell Peripherals
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
description: |+
|
||||
ARM, Ltd. Primecell peripherals have a standard id register that can be used to
|
||||
identify the peripheral type, vendor, and revision. This value can be used for
|
||||
driver matching.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,primecell
|
||||
description:
|
||||
Should be a specific name for the peripheral followed by "arm,primecell".
|
||||
The specific name will match the ARM engineering name for the logic block
|
||||
in the form "arm,pl???"
|
||||
|
||||
arm,primecell-periphid:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Value to override the h/w ID value
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
clock-names:
|
||||
contains:
|
||||
const: apb_pclk
|
||||
additionalItems: true
|
||||
...
|
||||
@ -1,57 +0,0 @@
|
||||
QCOM device tree bindings
|
||||
-------------------------
|
||||
|
||||
Some qcom based bootloaders identify the dtb blob based on a set of
|
||||
device properties like SoC and platform and revisions of those components.
|
||||
To support this scheme, we encode this information into the board compatible
|
||||
string.
|
||||
|
||||
Each board must specify a top-level board compatible string with the following
|
||||
format:
|
||||
|
||||
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
|
||||
|
||||
The 'SoC' and 'board' elements are required. All other elements are optional.
|
||||
|
||||
The 'SoC' element must be one of the following strings:
|
||||
|
||||
apq8016
|
||||
apq8074
|
||||
apq8084
|
||||
apq8096
|
||||
msm8916
|
||||
msm8974
|
||||
msm8992
|
||||
msm8994
|
||||
msm8996
|
||||
mdm9615
|
||||
ipq8074
|
||||
sdm845
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
cdp
|
||||
liquid
|
||||
dragonboard
|
||||
mtp
|
||||
sbc
|
||||
hk01
|
||||
|
||||
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
|
||||
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
|
||||
as v1. If all versions of the 'board_version' elements match, then a
|
||||
wildcard '*' should be used, e.g. 'v*'.
|
||||
|
||||
The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
|
||||
|
||||
Examples:
|
||||
|
||||
"qcom,msm8916-v1-cdp-pm8916-v2.1"
|
||||
|
||||
A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
|
||||
2.1.
|
||||
|
||||
"qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
|
||||
|
||||
A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
|
||||
foundry 2.
|
||||
125
Bindings/arm/qcom.yaml
Normal file
125
Bindings/arm/qcom.yaml
Normal file
@ -0,0 +1,125 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/arm/qcom.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: QCOM device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Some qcom based bootloaders identify the dtb blob based on a set of
|
||||
device properties like SoC and platform and revisions of those components.
|
||||
To support this scheme, we encode this information into the board compatible
|
||||
string.
|
||||
|
||||
Each board must specify a top-level board compatible string with the following
|
||||
format:
|
||||
|
||||
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
|
||||
|
||||
The 'SoC' and 'board' elements are required. All other elements are optional.
|
||||
|
||||
The 'SoC' element must be one of the following strings:
|
||||
|
||||
apq8016
|
||||
apq8074
|
||||
apq8084
|
||||
apq8096
|
||||
msm8916
|
||||
msm8974
|
||||
msm8992
|
||||
msm8994
|
||||
msm8996
|
||||
mdm9615
|
||||
ipq8074
|
||||
sdm845
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
cdp
|
||||
liquid
|
||||
dragonboard
|
||||
mtp
|
||||
sbc
|
||||
hk01
|
||||
|
||||
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
|
||||
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
|
||||
as v1. If all versions of the 'board_version' elements match, then a
|
||||
wildcard '*' should be used, e.g. 'v*'.
|
||||
|
||||
The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
|
||||
|
||||
Examples:
|
||||
|
||||
"qcom,msm8916-v1-cdp-pm8916-v2.1"
|
||||
|
||||
A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
|
||||
2.1.
|
||||
|
||||
"qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
|
||||
|
||||
A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
|
||||
foundry 2.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8016-sbc
|
||||
- const: qcom,apq8016
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8064-cm-qs600
|
||||
- qcom,apq8064-ifc6410
|
||||
- const: qcom,apq8064
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8074-dragonboard
|
||||
- const: qcom,apq8074
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8060-dragonboard
|
||||
- qcom,msm8660-surf
|
||||
- const: qcom,msm8660
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,apq8084-mtp
|
||||
- qcom,apq8084-sbc
|
||||
- const: qcom,apq8084
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,msm8960-cdp
|
||||
- const: qcom,msm8960
|
||||
|
||||
- items:
|
||||
- const: qcom,msm8916-mtp/1
|
||||
- const: qcom,msm8916-mtp
|
||||
- const: qcom,msm8916
|
||||
|
||||
- items:
|
||||
- const: qcom,msm8996-mtp
|
||||
|
||||
- items:
|
||||
- const: qcom,ipq4019
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq8064-ap148
|
||||
- const: qcom,ipq8064
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq8074-hk01
|
||||
- const: qcom,ipq8074
|
||||
|
||||
...
|
||||
17
Bindings/arm/rda.txt
Normal file
17
Bindings/arm/rda.txt
Normal file
@ -0,0 +1,17 @@
|
||||
RDA Micro platforms device tree bindings
|
||||
----------------------------------------
|
||||
|
||||
RDA8810PL SoC
|
||||
=============
|
||||
|
||||
Required root node properties:
|
||||
|
||||
- compatible : must contain "rda,8810pl"
|
||||
|
||||
|
||||
Boards:
|
||||
|
||||
Root node property compatible must contain, depending on board:
|
||||
|
||||
- Orange Pi 2G-IoT: "xunlong,orangepi-2g-iot"
|
||||
- Orange Pi i96: "xunlong,orangepi-i96"
|
||||
20
Bindings/arm/renesas,prr.txt
Normal file
20
Bindings/arm/renesas,prr.txt
Normal file
@ -0,0 +1,20 @@
|
||||
Renesas Product Register
|
||||
|
||||
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
|
||||
allows to retrieve SoC product and revision information. If present, a device
|
||||
node for this register should be added.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of:
|
||||
"renesas,prr"
|
||||
"renesas,bsid"
|
||||
- reg: Base address and length of the register block.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
prr: chipid@ff000044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
};
|
||||
@ -1,240 +0,0 @@
|
||||
Rockchip platforms device tree bindings
|
||||
---------------------------------------
|
||||
|
||||
- 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
|
||||
Required root node properties:
|
||||
- compatible = "vamrs,ficus", "rockchip,rk3399";
|
||||
|
||||
- 96boards RK3399 Rock960 (ROCK960 Consumer Edition)
|
||||
Required root node properties:
|
||||
- compatible = "vamrs,rock960", "rockchip,rk3399";
|
||||
|
||||
- Amarula Vyasa RK3288 board
|
||||
Required root node properties:
|
||||
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
|
||||
|
||||
- Asus Tinker board
|
||||
Required root node properties:
|
||||
- compatible = "asus,rk3288-tinker", "rockchip,rk3288";
|
||||
|
||||
- Asus Tinker board S
|
||||
Required root node properties:
|
||||
- compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
|
||||
|
||||
- Kylin RK3036 board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
|
||||
|
||||
- MarsBoard RK3066 board:
|
||||
Required root node properties:
|
||||
- compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
|
||||
|
||||
- bq Curie 2 tablet:
|
||||
Required root node properties:
|
||||
- compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
|
||||
|
||||
- ChipSPARK Rayeager PX2 board:
|
||||
Required root node properties:
|
||||
- compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";
|
||||
|
||||
- Radxa Rock board:
|
||||
Required root node properties:
|
||||
- compatible = "radxa,rock", "rockchip,rk3188";
|
||||
|
||||
- Radxa Rock2 Square board:
|
||||
Required root node properties:
|
||||
- compatible = "radxa,rock2-square", "rockchip,rk3288";
|
||||
|
||||
- Rikomagic MK808 v1 board:
|
||||
Required root node properties:
|
||||
- compatible = "rikomagic,mk808", "rockchip,rk3066a";
|
||||
|
||||
- Firefly Firefly-RK3288 board:
|
||||
Required root node properties:
|
||||
- compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
|
||||
or
|
||||
- compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288";
|
||||
|
||||
- Firefly Firefly-RK3288 Reload board:
|
||||
Required root node properties:
|
||||
- compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
|
||||
|
||||
- Firefly Firefly-RK3399 board:
|
||||
Required root node properties:
|
||||
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
|
||||
|
||||
- Firefly roc-rk3328-cc board:
|
||||
Required root node properties:
|
||||
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
|
||||
|
||||
- Firefly ROC-RK3399-PC board:
|
||||
Required root node properties:
|
||||
- compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
|
||||
|
||||
- ChipSPARK PopMetal-RK3288 board:
|
||||
Required root node properties:
|
||||
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
|
||||
|
||||
- Netxeon R89 board:
|
||||
Required root node properties:
|
||||
- compatible = "netxeon,r89", "rockchip,rk3288";
|
||||
|
||||
- GeekBuying GeekBox:
|
||||
Required root node properties:
|
||||
- compatible = "geekbuying,geekbox", "rockchip,rk3368";
|
||||
|
||||
- Google Bob (Asus Chromebook Flip C101PA):
|
||||
Required root node properties:
|
||||
compatible = "google,bob-rev13", "google,bob-rev12",
|
||||
"google,bob-rev11", "google,bob-rev10",
|
||||
"google,bob-rev9", "google,bob-rev8",
|
||||
"google,bob-rev7", "google,bob-rev6",
|
||||
"google,bob-rev5", "google,bob-rev4",
|
||||
"google,bob", "google,gru", "rockchip,rk3399";
|
||||
|
||||
- Google Brain (dev-board):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Gru (dev-board):
|
||||
Required root node properties:
|
||||
- compatible = "google,gru-rev15", "google,gru-rev14",
|
||||
"google,gru-rev13", "google,gru-rev12",
|
||||
"google,gru-rev11", "google,gru-rev10",
|
||||
"google,gru-rev9", "google,gru-rev8",
|
||||
"google,gru-rev7", "google,gru-rev6",
|
||||
"google,gru-rev5", "google,gru-rev4",
|
||||
"google,gru-rev3", "google,gru-rev2",
|
||||
"google,gru", "rockchip,rk3399";
|
||||
|
||||
- Google Jaq (Haier Chromebook 11 and more):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
|
||||
"google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
|
||||
"google,veyron-jaq-rev1", "google,veyron-jaq",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Jerry (Hisense Chromebook C11 and more):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
|
||||
"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
|
||||
"google,veyron-jerry-rev3", "google,veyron-jerry",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Kevin (Samsung Chromebook Plus):
|
||||
Required root node properties:
|
||||
- compatible = "google,kevin-rev15", "google,kevin-rev14",
|
||||
"google,kevin-rev13", "google,kevin-rev12",
|
||||
"google,kevin-rev11", "google,kevin-rev10",
|
||||
"google,kevin-rev9", "google,kevin-rev8",
|
||||
"google,kevin-rev7", "google,kevin-rev6",
|
||||
"google,kevin", "google,gru", "rockchip,rk3399";
|
||||
|
||||
- Google Mickey (Asus Chromebit CS10):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
|
||||
"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
|
||||
"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
|
||||
"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
|
||||
"google,veyron-mickey-rev0", "google,veyron-mickey",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Minnie (Asus Chromebook Flip C100P):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
|
||||
"google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
|
||||
"google,veyron-minnie-rev0", "google,veyron-minnie",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Pinky (dev-board):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
|
||||
"google,veyron", "rockchip,rk3288";
|
||||
|
||||
- Google Speedy (Asus C201 Chromebook):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
|
||||
"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
|
||||
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
|
||||
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
|
||||
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
|
||||
|
||||
- mqmaker MiQi:
|
||||
Required root node properties:
|
||||
- compatible = "mqmaker,miqi", "rockchip,rk3288";
|
||||
|
||||
- Phytec phyCORE-RK3288: Rapid Development Kit
|
||||
Required root node properties:
|
||||
- compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
|
||||
|
||||
- Pine64 Rock64 board:
|
||||
Required root node properties:
|
||||
- compatible = "pine64,rock64", "rockchip,rk3328";
|
||||
|
||||
- Pine64 RockPro64 board:
|
||||
Required root node properties:
|
||||
- compatible = "pine64,rockpro64", "rockchip,rk3399";
|
||||
|
||||
- Rockchip PX3 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
|
||||
|
||||
- Rockchip PX5 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
|
||||
|
||||
- Rockchip PX30 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,px30-evb", "rockchip,px30";
|
||||
|
||||
- Rockchip RV1108 Evaluation board
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
|
||||
|
||||
- Rockchip RK3368 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
|
||||
|
||||
- Rockchip R88 board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,r88", "rockchip,rk3368";
|
||||
|
||||
- Rockchip RK3228 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
|
||||
|
||||
- Rockchip RK3229 Evaluation board:
|
||||
- compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
|
||||
|
||||
- Rockchip RK3288 Fennec board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
|
||||
|
||||
- Rockchip RK3328 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
|
||||
|
||||
- Rockchip RK3399 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
|
||||
|
||||
- Rockchip RK3399 Sapphire board standalone:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
|
||||
|
||||
- Rockchip RK3399 Sapphire Excavator board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
|
||||
|
||||
- Theobroma Systems RK3368-uQ7 Haikou Baseboard:
|
||||
Required root node properties:
|
||||
- compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368";
|
||||
|
||||
- Theobroma Systems RK3399-Q7 Haikou Baseboard:
|
||||
Required root node properties:
|
||||
- compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
|
||||
|
||||
- Tronsmart Orion R68 Meta
|
||||
Required root node properties:
|
||||
- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
|
||||
423
Bindings/arm/rockchip.yaml
Normal file
423
Bindings/arm/rockchip.yaml
Normal file
@ -0,0 +1,423 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/rockchip.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
|
||||
- description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
|
||||
items:
|
||||
- const: vamrs,ficus
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: 96boards RK3399 Rock960 (ROCK960 Consumer Edition)
|
||||
items:
|
||||
- const: vamrs,rock960
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Amarula Vyasa RK3288
|
||||
items:
|
||||
- const: amarula,vyasa-rk3288
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Asus Tinker board
|
||||
items:
|
||||
- const: asus,rk3288-tinker
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Asus Tinker board S
|
||||
items:
|
||||
- const: asus,rk3288-tinker-s
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: bq Curie 2 tablet
|
||||
items:
|
||||
- const: mundoreader,bq-curie2
|
||||
- const: rockchip,rk3066a
|
||||
|
||||
- description: bq Edison 2 Quad-Core tablet
|
||||
items:
|
||||
- const: mundoreader,bq-edison2qc
|
||||
- const: rockchip,rk3188
|
||||
|
||||
- description: ChipSPARK PopMetal-RK3288
|
||||
items:
|
||||
- const: chipspark,popmetal-rk3288
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: ChipSPARK Rayeager PX2
|
||||
items:
|
||||
- const: chipspark,rayeager-px2
|
||||
- const: rockchip,rk3066a
|
||||
|
||||
- description: Firefly Firefly-RK3288
|
||||
items:
|
||||
- enum:
|
||||
- firefly,firefly-rk3288
|
||||
- firefly,firefly-rk3288-beta
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Firefly Firefly-RK3288 Reload
|
||||
items:
|
||||
- const: firefly,firefly-rk3288-reload
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Firefly Firefly-RK3399
|
||||
items:
|
||||
- const: firefly,firefly-rk3399
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Firefly roc-rk3328-cc
|
||||
items:
|
||||
- const: firefly,roc-rk3328-cc
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: Firefly ROC-RK3399-PC
|
||||
items:
|
||||
- const: firefly,roc-rk3399-pc
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: GeekBuying GeekBox
|
||||
items:
|
||||
- const: geekbuying,geekbox
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Google Bob (Asus Chromebook Flip C101PA)
|
||||
items:
|
||||
- const: google,bob-rev13
|
||||
- const: google,bob-rev12
|
||||
- const: google,bob-rev11
|
||||
- const: google,bob-rev10
|
||||
- const: google,bob-rev9
|
||||
- const: google,bob-rev8
|
||||
- const: google,bob-rev7
|
||||
- const: google,bob-rev6
|
||||
- const: google,bob-rev5
|
||||
- const: google,bob-rev4
|
||||
- const: google,bob
|
||||
- const: google,gru
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Google Brain (dev-board)
|
||||
items:
|
||||
- const: google,veyron-brain-rev0
|
||||
- const: google,veyron-brain
|
||||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Google Gru (dev-board)
|
||||
items:
|
||||
- const: google,gru-rev15
|
||||
- const: google,gru-rev14
|
||||
- const: google,gru-rev13
|
||||
- const: google,gru-rev12
|
||||
- const: google,gru-rev11
|
||||
- const: google,gru-rev10
|
||||
- const: google,gru-rev9
|
||||
- const: google,gru-rev8
|
||||
- const: google,gru-rev7
|
||||
- const: google,gru-rev6
|
||||
- const: google,gru-rev5
|
||||
- const: google,gru-rev4
|
||||
- const: google,gru-rev3
|
||||
- const: google,gru-rev2
|
||||
- const: google,gru
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Google Jaq (Haier Chromebook 11 and more)
|
||||
items:
|
||||
- const: google,veyron-jaq-rev5
|
||||
- const: google,veyron-jaq-rev4
|
||||
- const: google,veyron-jaq-rev3
|
||||
- const: google,veyron-jaq-rev2
|
||||
- const: google,veyron-jaq-rev1
|
||||
- const: google,veyron-jaq
|
||||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Google Jerry (Hisense Chromebook C11 and more)
|
||||
items:
|
||||
- const: google,veyron-jerry-rev7
|
||||
- const: google,veyron-jerry-rev6
|
||||
- const: google,veyron-jerry-rev5
|
||||
- const: google,veyron-jerry-rev4
|
||||
- const: google,veyron-jerry-rev3
|
||||
- const: google,veyron-jerry
|
||||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Google Kevin (Samsung Chromebook Plus)
|
||||
items:
|
||||
- const: google,kevin-rev15
|
||||
- const: google,kevin-rev14
|
||||
- const: google,kevin-rev13
|
||||
- const: google,kevin-rev12
|
||||
- const: google,kevin-rev11
|
||||
- const: google,kevin-rev10
|
||||
- const: google,kevin-rev9
|
||||
- const: google,kevin-rev8
|
||||
- const: google,kevin-rev7
|
||||
- const: google,kevin-rev6
|
||||
- const: google,kevin
|
||||
- const: google,gru
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Google Mickey (Asus Chromebit CS10)
|
||||
items:
|
||||
- const: google,veyron-mickey-rev8
|
||||
- const: google,veyron-mickey-rev7
|
||||
- const: google,veyron-mickey-rev6
|
||||
- const: google,veyron-mickey-rev5
|
||||
- const: google,veyron-mickey-rev4
|
||||
- const: google,veyron-mickey-rev3
|
||||
- const: google,veyron-mickey-rev2
|
||||
- const: google,veyron-mickey-rev1
|
||||
- const: google,veyron-mickey-rev0
|
||||
- const: google,veyron-mickey
|
||||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Google Minnie (Asus Chromebook Flip C100P)
|
||||
items:
|
||||
- const: google,veyron-minnie-rev4
|
||||
- const: google,veyron-minnie-rev3
|
||||
- const: google,veyron-minnie-rev2
|
||||
- const: google,veyron-minnie-rev1
|
||||
- const: google,veyron-minnie-rev0
|
||||
- const: google,veyron-minnie
|
||||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Google Pinky (dev-board)
|
||||
items:
|
||||
- const: google,veyron-pinky-rev2
|
||||
- const: google,veyron-pinky
|
||||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10)
|
||||
items:
|
||||
- const: google,scarlet-rev15-sku7
|
||||
- const: google,scarlet-rev15
|
||||
- const: google,scarlet-rev14-sku7
|
||||
- const: google,scarlet-rev14
|
||||
- const: google,scarlet-rev13-sku7
|
||||
- const: google,scarlet-rev13
|
||||
- const: google,scarlet-rev12-sku7
|
||||
- const: google,scarlet-rev12
|
||||
- const: google,scarlet-rev11-sku7
|
||||
- const: google,scarlet-rev11
|
||||
- const: google,scarlet-rev10-sku7
|
||||
- const: google,scarlet-rev10
|
||||
- const: google,scarlet-rev9-sku7
|
||||
- const: google,scarlet-rev9
|
||||
- const: google,scarlet-rev8-sku7
|
||||
- const: google,scarlet-rev8
|
||||
- const: google,scarlet-rev7-sku7
|
||||
- const: google,scarlet-rev7
|
||||
- const: google,scarlet-rev6-sku7
|
||||
- const: google,scarlet-rev6
|
||||
- const: google,scarlet-rev5-sku7
|
||||
- const: google,scarlet-rev5
|
||||
- const: google,scarlet-rev4-sku7
|
||||
- const: google,scarlet-rev4
|
||||
- const: google,scarlet-rev3-sku7
|
||||
- const: google,scarlet-rev3
|
||||
- const: google,scarlet
|
||||
- const: google,gru
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Google Scarlet - Innolux display (Acer Chromebook Tab 10)
|
||||
items:
|
||||
- const: google,scarlet-rev15-sku6
|
||||
- const: google,scarlet-rev15
|
||||
- const: google,scarlet-rev14-sku6
|
||||
- const: google,scarlet-rev14
|
||||
- const: google,scarlet-rev13-sku6
|
||||
- const: google,scarlet-rev13
|
||||
- const: google,scarlet-rev12-sku6
|
||||
- const: google,scarlet-rev12
|
||||
- const: google,scarlet-rev11-sku6
|
||||
- const: google,scarlet-rev11
|
||||
- const: google,scarlet-rev10-sku6
|
||||
- const: google,scarlet-rev10
|
||||
- const: google,scarlet-rev9-sku6
|
||||
- const: google,scarlet-rev9
|
||||
- const: google,scarlet-rev8-sku6
|
||||
- const: google,scarlet-rev8
|
||||
- const: google,scarlet-rev7-sku6
|
||||
- const: google,scarlet-rev7
|
||||
- const: google,scarlet-rev6-sku6
|
||||
- const: google,scarlet-rev6
|
||||
- const: google,scarlet-rev5-sku6
|
||||
- const: google,scarlet-rev5
|
||||
- const: google,scarlet-rev4-sku6
|
||||
- const: google,scarlet-rev4
|
||||
- const: google,scarlet
|
||||
- const: google,gru
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Google Speedy (Asus C201 Chromebook)
|
||||
items:
|
||||
- const: google,veyron-speedy-rev9
|
||||
- const: google,veyron-speedy-rev8
|
||||
- const: google,veyron-speedy-rev7
|
||||
- const: google,veyron-speedy-rev6
|
||||
- const: google,veyron-speedy-rev5
|
||||
- const: google,veyron-speedy-rev4
|
||||
- const: google,veyron-speedy-rev3
|
||||
- const: google,veyron-speedy-rev2
|
||||
- const: google,veyron-speedy
|
||||
- const: google,veyron
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Haoyu MarsBoard RK3066
|
||||
items:
|
||||
- const: haoyu,marsboard-rk3066
|
||||
- const: rockchip,rk3066a
|
||||
|
||||
- description: mqmaker MiQi
|
||||
items:
|
||||
- const: mqmaker,miqi
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Netxeon R89 board
|
||||
items:
|
||||
- const: netxeon,r89
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Phytec phyCORE-RK3288 Rapid Development Kit
|
||||
items:
|
||||
- const: phytec,rk3288-pcm-947
|
||||
- const: phytec,rk3288-phycore-som
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Pine64 Rock64
|
||||
items:
|
||||
- const: pine64,rock64
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: Pine64 RockPro64
|
||||
items:
|
||||
- const: pine64,rockpro64
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Radxa Rock
|
||||
items:
|
||||
- const: radxa,rock
|
||||
- const: rockchip,rk3188
|
||||
|
||||
- description: Radxa Rock2 Square
|
||||
items:
|
||||
- const: radxa,rock2-square
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Rikomagic MK808 v1
|
||||
items:
|
||||
- const: rikomagic,mk808
|
||||
- const: rockchip,rk3066a
|
||||
|
||||
- description: Rockchip Kylin
|
||||
items:
|
||||
- const: rockchip,kylin-rk3036
|
||||
- const: rockchip,rk3036
|
||||
|
||||
- description: Rockchip PX3 Evaluation board
|
||||
items:
|
||||
- const: rockchip,px3-evb
|
||||
- const: rockchip,px3
|
||||
- const: rockchip,rk3188
|
||||
|
||||
- description: Rockchip PX30 Evaluation board
|
||||
items:
|
||||
- const: rockchip,px30-evb
|
||||
- const: rockchip,px30
|
||||
|
||||
- description: Rockchip PX5 Evaluation board
|
||||
items:
|
||||
- const: rockchip,px5-evb
|
||||
- const: rockchip,px5
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Rockchip R88
|
||||
items:
|
||||
- const: rockchip,r88
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Rockchip RK3228 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3228-evb
|
||||
- const: rockchip,rk3228
|
||||
|
||||
- description: Rockchip RK3229 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3229-evb
|
||||
- const: rockchip,rk3229
|
||||
|
||||
- description: Rockchip RK3288 Evaluation board
|
||||
items:
|
||||
- enum:
|
||||
- rockchip,rk3288-evb-act8846
|
||||
- rockchip,rk3288-evb-rk808
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Rockchip RK3288 Fennec
|
||||
items:
|
||||
- const: rockchip,rk3288-fennec
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Rockchip RK3328 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3328-evb
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: Rockchip RK3368 Evaluation board (act8846 pmic)
|
||||
items:
|
||||
- const: rockchip,rk3368-evb-act8846
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Rockchip RK3399 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3399-evb
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Rockchip RK3399 Sapphire standalone
|
||||
items:
|
||||
- const: rockchip,rk3399-sapphire
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Rockchip RK3399 Sapphire with Excavator Baseboard
|
||||
items:
|
||||
- const: rockchip,rk3399-sapphire-excavator
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Rockchip RV1108 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rv1108-evb
|
||||
- const: rockchip,rv1108
|
||||
|
||||
- description: Theobroma Systems RK3368-uQ7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,rk3368-uq7-haikou
|
||||
- const: rockchip,rk3368
|
||||
|
||||
- description: Theobroma Systems RK3399-Q7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,rk3399-q7-haikou
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Tronsmart Orion R68 Meta
|
||||
items:
|
||||
- const: tronsmart,orion-r68-meta
|
||||
- const: rockchip,rk3368
|
||||
...
|
||||
@ -101,6 +101,10 @@ Boards:
|
||||
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
|
||||
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
|
||||
compatible = "iwave,g20m", "renesas,r8a7743"
|
||||
- iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven)
|
||||
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"
|
||||
- iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven)
|
||||
compatible = "iwave,g20m", "renesas,r8a7744"
|
||||
- Kingfisher (SBEV-RCAR-KF-M03)
|
||||
compatible = "shimafuji,kingfisher"
|
||||
- Koelsch (RTP0RC7791SEB00010S)
|
||||
@ -149,21 +153,3 @@ Boards:
|
||||
compatible = "renesas,v3msk", "renesas,r8a77970"
|
||||
- Wheat (RTP0RC7792ASKB0000JE)
|
||||
compatible = "renesas,wheat", "renesas,r8a7792"
|
||||
|
||||
|
||||
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
|
||||
allows to retrieve SoC product and revision information. If present, a device
|
||||
node for this register should be added.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "renesas,prr" or "renesas,bsid"
|
||||
- reg: Base address and length of the register block.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
prr: chipid@ff000044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
};
|
||||
|
||||
@ -1,11 +0,0 @@
|
||||
CSR SiRFprimaII and SiRFmarco device tree bindings.
|
||||
========================================
|
||||
|
||||
Required root node properties:
|
||||
- compatible:
|
||||
- "sirf,atlas6-cb" : atlas6 "cb" evaluation board
|
||||
- "sirf,atlas6" : atlas6 device based board
|
||||
- "sirf,atlas7-cb" : atlas7 "cb" evaluation board
|
||||
- "sirf,atlas7" : atlas7 device based board
|
||||
- "sirf,prima2-cb" : prima2 "cb" evaluation board
|
||||
- "sirf,prima2" : prima2 device based board
|
||||
27
Bindings/arm/sirf.yaml
Normal file
27
Bindings/arm/sirf.yaml
Normal file
@ -0,0 +1,27 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/sirf.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: CSR SiRFprimaII and SiRFmarco device tree bindings.
|
||||
|
||||
maintainers:
|
||||
- Binghua Duan <binghua.duan@csr.com>
|
||||
- Barry Song <Baohua.Song@csr.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: sirf,atlas6-cb
|
||||
- const: sirf,atlas6
|
||||
- items:
|
||||
- const: sirf,atlas7-cb
|
||||
- const: sirf,atlas7
|
||||
- items:
|
||||
- const: sirf,prima2-cb
|
||||
- const: sirf,prima2
|
||||
...
|
||||
47
Bindings/arm/socionext/uniphier.txt
Normal file
47
Bindings/arm/socionext/uniphier.txt
Normal file
@ -0,0 +1,47 @@
|
||||
Socionext UniPhier SoC family
|
||||
-----------------------------
|
||||
|
||||
Required properties in the root node:
|
||||
- compatible: should contain board and SoC compatible strings
|
||||
|
||||
SoC and board compatible strings:
|
||||
(sorted chronologically)
|
||||
|
||||
- LD4 SoC: "socionext,uniphier-ld4"
|
||||
- Reference Board: "socionext,uniphier-ld4-ref"
|
||||
|
||||
- Pro4 SoC: "socionext,uniphier-pro4"
|
||||
- Reference Board: "socionext,uniphier-pro4-ref"
|
||||
- Ace Board: "socionext,uniphier-pro4-ace"
|
||||
- Sanji Board: "socionext,uniphier-pro4-sanji"
|
||||
|
||||
- sLD8 SoC: "socionext,uniphier-sld8"
|
||||
- Reference Board: "socionext,uniphier-sld8-ref"
|
||||
|
||||
- PXs2 SoC: "socionext,uniphier-pxs2"
|
||||
- Gentil Board: "socionext,uniphier-pxs2-gentil"
|
||||
- Vodka Board: "socionext,uniphier-pxs2-vodka"
|
||||
|
||||
- LD6b SoC: "socionext,uniphier-ld6b"
|
||||
- Reference Board: "socionext,uniphier-ld6b-ref"
|
||||
|
||||
- LD11 SoC: "socionext,uniphier-ld11"
|
||||
- Reference Board: "socionext,uniphier-ld11-ref"
|
||||
- Global Board: "socionext,uniphier-ld11-global"
|
||||
|
||||
- LD20 SoC: "socionext,uniphier-ld20"
|
||||
- Reference Board: "socionext,uniphier-ld20-ref"
|
||||
- Global Board: "socionext,uniphier-ld20-global"
|
||||
|
||||
- PXs3 SoC: "socionext,uniphier-pxs3"
|
||||
- Reference Board: "socionext,uniphier-pxs3-ref"
|
||||
|
||||
Example:
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
|
||||
|
||||
...
|
||||
};
|
||||
@ -4,7 +4,7 @@ SP810 System Controller
|
||||
Required properties:
|
||||
|
||||
- compatible: standard compatible string for a Primecell peripheral,
|
||||
see Documentation/devicetree/bindings/arm/primecell.txt
|
||||
see Documentation/devicetree/bindings/arm/primecell.yaml
|
||||
for more details
|
||||
should be: "arm,sp810", "arm,primecell"
|
||||
|
||||
|
||||
@ -1,26 +0,0 @@
|
||||
ST SPEAr Platforms Device Tree Bindings
|
||||
---------------------------------------
|
||||
|
||||
Boards with the ST SPEAr600 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,spear600";
|
||||
|
||||
Boards with the ST SPEAr300 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,spear300";
|
||||
|
||||
Boards with the ST SPEAr310 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,spear310";
|
||||
|
||||
Boards with the ST SPEAr320 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,spear320";
|
||||
|
||||
Boards with the ST SPEAr1310 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,spear1310";
|
||||
|
||||
Boards with the ST SPEAr1340 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,spear1340";
|
||||
25
Bindings/arm/spear.yaml
Normal file
25
Bindings/arm/spear.yaml
Normal file
@ -0,0 +1,25 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/spear.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ST SPEAr Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Viresh Kumar <vireshk@kernel.org>
|
||||
- Stefan Roese <sr@denx.de>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- st,spear600
|
||||
- st,spear300
|
||||
- st,spear310
|
||||
- st,spear320
|
||||
- st,spear1310
|
||||
- st,spear1340
|
||||
...
|
||||
@ -1,23 +0,0 @@
|
||||
ST STi Platforms Device Tree Bindings
|
||||
---------------------------------------
|
||||
|
||||
Boards with the ST STiH415 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih415";
|
||||
|
||||
Boards with the ST STiH416 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih416";
|
||||
|
||||
Boards with the ST STiH407 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih407";
|
||||
|
||||
Boards with the ST STiH410 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih410";
|
||||
|
||||
Boards with the ST STiH418 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih418";
|
||||
|
||||
23
Bindings/arm/sti.yaml
Normal file
23
Bindings/arm/sti.yaml
Normal file
@ -0,0 +1,23 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/sti.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ST STi Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Patrice Chotard <patrice.chotard@st.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- st,stih415
|
||||
- st,stih416
|
||||
- st,stih407
|
||||
- st,stih410
|
||||
- st,stih418
|
||||
...
|
||||
@ -14,8 +14,10 @@ using one of the following compatible strings:
|
||||
allwinner,sun8i-a83t
|
||||
allwinner,sun8i-h2-plus
|
||||
allwinner,sun8i-h3
|
||||
allwinner-sun8i-r40
|
||||
allwinner,sun8i-r40
|
||||
allwinner,sun8i-t3
|
||||
allwinner,sun8i-v3s
|
||||
allwinner,sun9i-a80
|
||||
allwinner,sun50i-a64
|
||||
allwinner,suniv-f1c100s
|
||||
nextthing,gr8
|
||||
|
||||
@ -1,65 +0,0 @@
|
||||
NVIDIA Tegra device tree bindings
|
||||
-------------------------------------------
|
||||
|
||||
SoCs
|
||||
-------------------------------------------
|
||||
|
||||
Each device tree must specify which Tegra SoC it uses, using one of the
|
||||
following compatible values:
|
||||
|
||||
nvidia,tegra20
|
||||
nvidia,tegra30
|
||||
nvidia,tegra114
|
||||
nvidia,tegra124
|
||||
nvidia,tegra132
|
||||
nvidia,tegra210
|
||||
nvidia,tegra186
|
||||
nvidia,tegra194
|
||||
|
||||
Boards
|
||||
-------------------------------------------
|
||||
|
||||
Each device tree must specify which one or more of the following
|
||||
board-specific compatible values:
|
||||
|
||||
ad,medcom-wide
|
||||
ad,plutux
|
||||
ad,tamonten
|
||||
ad,tec
|
||||
compal,paz00
|
||||
compulab,trimslice
|
||||
nvidia,beaver
|
||||
nvidia,cardhu
|
||||
nvidia,cardhu-a02
|
||||
nvidia,cardhu-a04
|
||||
nvidia,dalmore
|
||||
nvidia,harmony
|
||||
nvidia,jetson-tk1
|
||||
nvidia,norrin
|
||||
nvidia,p2371-0000
|
||||
nvidia,p2371-2180
|
||||
nvidia,p2571
|
||||
nvidia,p2771-0000
|
||||
nvidia,p2972-0000
|
||||
nvidia,roth
|
||||
nvidia,seaboard
|
||||
nvidia,tn7
|
||||
nvidia,ventana
|
||||
toradex,apalis_t30
|
||||
toradex,apalis_t30-eval
|
||||
toradex,apalis_t30-v1.1
|
||||
toradex,apalis_t30-v1.1-eval
|
||||
toradex,apalis-tk1
|
||||
toradex,apalis-tk1-eval
|
||||
toradex,apalis-tk1-v1.2
|
||||
toradex,apalis-tk1-v1.2-eval
|
||||
toradex,colibri_t20
|
||||
toradex,colibri_t20-eval-v3
|
||||
toradex,colibri_t20-iris
|
||||
toradex,colibri_t30
|
||||
toradex,colibri_t30-eval-v3
|
||||
|
||||
Trusted Foundations
|
||||
-------------------------------------------
|
||||
Tegra supports the Trusted Foundation secure monitor. See the
|
||||
"tlm,trusted-foundations" binding's documentation for more details.
|
||||
101
Bindings/arm/tegra.yaml
Normal file
101
Bindings/arm/tegra.yaml
Normal file
@ -0,0 +1,101 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/tegra.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jonathan Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- compal,paz00
|
||||
- compulab,trimslice
|
||||
- nvidia,harmony
|
||||
- nvidia,seaboard
|
||||
- nvidia,ventana
|
||||
- const: nvidia,tegra20
|
||||
- items:
|
||||
- enum:
|
||||
- ad,medcom-wide
|
||||
- ad,plutux
|
||||
- ad,tec
|
||||
- const: ad,tamonten
|
||||
- const: nvidia,tegra20
|
||||
- items:
|
||||
- enum:
|
||||
- toradex,colibri_t20-eval-v3
|
||||
- toradex,colibri_t20-iris
|
||||
- const: toradex,colibri_t20
|
||||
- const: nvidia,tegra20
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,beaver
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,cardhu-a02
|
||||
- nvidia,cardhu-a04
|
||||
- const: nvidia,cardhu
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: toradex,apalis_t30-eval
|
||||
- const: toradex,apalis_t30
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: toradex,apalis_t30-eval-v1.1
|
||||
- const: toradex,apalis_t30-eval
|
||||
- const: toradex,apalis_t30-v1.1
|
||||
- const: toradex,apalis_t30
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- enum:
|
||||
- toradex,colibri_t30-eval-v3
|
||||
- const: toradex,colibri_t30
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,dalmore
|
||||
- nvidia,roth
|
||||
- nvidia,tn7
|
||||
- const: nvidia,tegra114
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,jetson-tk1
|
||||
- nvidia,venice2
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: toradex,apalis-tk1-eval
|
||||
- const: toradex,apalis-tk1
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- const: toradex,apalis-tk1-v1.2-eval
|
||||
- const: toradex,apalis-tk1-eval
|
||||
- const: toradex,apalis-tk1-v1.2
|
||||
- const: toradex,apalis-tk1
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,norrin
|
||||
- const: nvidia,tegra132
|
||||
- const: nvidia,tegra124
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,p2371-0000
|
||||
- nvidia,p2371-2180
|
||||
- nvidia,p2571
|
||||
- const: nvidia,tegra210
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,p2771-0000
|
||||
- const: nvidia,tegra186
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,p2972-0000
|
||||
- const: nvidia,tegra194
|
||||
@ -15,6 +15,9 @@ Required properties:
|
||||
|
||||
Optional properties:
|
||||
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 2.
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
24
Bindings/arm/ti/nspire.yaml
Normal file
24
Bindings/arm/ti/nspire.yaml
Normal file
@ -0,0 +1,24 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/ti/nspire.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI-NSPIRE calculators
|
||||
|
||||
maintainers:
|
||||
- Daniel Tang <dt.tangr@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
# CX models
|
||||
- ti,nspire-cx
|
||||
# Touchpad models
|
||||
- ti,nspire-tp
|
||||
# Clickpad models
|
||||
- ti,nspire-clp
|
||||
...
|
||||
26
Bindings/arm/ti/ti,davinci.yaml
Normal file
26
Bindings/arm/ti/ti,davinci.yaml
Normal file
@ -0,0 +1,26 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/ti/davinci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments DaVinci Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Sekhar Nori <nsekhar@ti.com>
|
||||
|
||||
description:
|
||||
DA850/OMAP-L138/AM18x based boards
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- ti,da850-evm # DA850/OMAP-L138/AM18x Evaluation Module (EVM) board
|
||||
- ti,da850-lcdk # DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board
|
||||
- enbw,cmc # EnBW AM1808 based CMC board
|
||||
- lego,ev3 # LEGO MINDSTORMS EV3 (AM1808 based)
|
||||
- const: ti,da850
|
||||
...
|
||||
@ -472,4 +472,4 @@ cpus {
|
||||
|
||||
===============================================================================
|
||||
[1] ARM Linux kernel documentation
|
||||
Documentation/devicetree/bindings/arm/cpus.txt
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
|
||||
@ -1,22 +0,0 @@
|
||||
VIA/Wondermedia VT8500 Platforms Device Tree Bindings
|
||||
---------------------------------------
|
||||
|
||||
Boards with the VIA VT8500 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "via,vt8500";
|
||||
|
||||
Boards with the Wondermedia WM8505 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "wm,wm8505";
|
||||
|
||||
Boards with the Wondermedia WM8650 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "wm,wm8650";
|
||||
|
||||
Boards with the Wondermedia WM8750 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "wm,wm8750";
|
||||
|
||||
Boards with the Wondermedia WM8850 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "wm,wm8850";
|
||||
23
Bindings/arm/vt8500.yaml
Normal file
23
Bindings/arm/vt8500.yaml
Normal file
@ -0,0 +1,23 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/vt8500.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: VIA/Wondermedia VT8500 Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Tony Prisk <linux@prisktech.co.nz>
|
||||
description: test
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- via,vt8500
|
||||
- wm,wm8505
|
||||
- wm,wm8650
|
||||
- wm,wm8750
|
||||
- wm,wm8850
|
||||
@ -1,83 +0,0 @@
|
||||
Xilinx Zynq Platforms Device Tree Bindings
|
||||
|
||||
Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor
|
||||
shall have the following properties.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "xlnx,zynq-7000";
|
||||
|
||||
Additional compatible strings:
|
||||
|
||||
- Adapteva Parallella board
|
||||
"adapteva,parallella"
|
||||
|
||||
- Avnet MicroZed board
|
||||
"avnet,zynq-microzed"
|
||||
"xlnx,zynq-microzed"
|
||||
|
||||
- Avnet ZedBoard board
|
||||
"avnet,zynq-zed"
|
||||
"xlnx,zynq-zed"
|
||||
|
||||
- Digilent Zybo board
|
||||
"digilent,zynq-zybo"
|
||||
|
||||
- Digilent Zybo Z7 board
|
||||
"digilent,zynq-zybo-z7"
|
||||
|
||||
- Xilinx CC108 internal board
|
||||
"xlnx,zynq-cc108"
|
||||
|
||||
- Xilinx ZC702 internal board
|
||||
"xlnx,zynq-zc702"
|
||||
|
||||
- Xilinx ZC706 internal board
|
||||
"xlnx,zynq-zc706"
|
||||
|
||||
- Xilinx ZC770 internal board, with different FMC cards
|
||||
"xlnx,zynq-zc770-xm010"
|
||||
"xlnx,zynq-zc770-xm011"
|
||||
"xlnx,zynq-zc770-xm012"
|
||||
"xlnx,zynq-zc770-xm013"
|
||||
|
||||
---------------------------------------------------------------
|
||||
|
||||
Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
|
||||
|
||||
Boards with ZynqMP SOC based on an ARM Cortex A53 processor
|
||||
shall have the following properties.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "xlnx,zynqmp";
|
||||
|
||||
|
||||
Additional compatible strings:
|
||||
|
||||
- Xilinx internal board zc1232
|
||||
"xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232"
|
||||
|
||||
- Xilinx internal board zc1254
|
||||
"xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254"
|
||||
|
||||
- Xilinx internal board zc1275
|
||||
"xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275"
|
||||
|
||||
- Xilinx internal board zc1751
|
||||
"xlnx,zynqmp-zc1751"
|
||||
|
||||
- Xilinx 96boards compatible board zcu100
|
||||
"xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"
|
||||
|
||||
- Xilinx evaluation board zcu102
|
||||
"xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102"
|
||||
"xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102"
|
||||
"xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102"
|
||||
|
||||
- Xilinx evaluation board zcu104
|
||||
"xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104"
|
||||
|
||||
- Xilinx evaluation board zcu106
|
||||
"xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106"
|
||||
|
||||
- Xilinx evaluation board zcu111
|
||||
"xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111"
|
||||
114
Bindings/arm/xilinx.yaml
Normal file
114
Bindings/arm/xilinx.yaml
Normal file
@ -0,0 +1,114 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/xilinx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx Zynq Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@xilinx.com>
|
||||
|
||||
description: |
|
||||
Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- adapteva,parallella
|
||||
- digilent,zynq-zybo
|
||||
- digilent,zynq-zybo-z7
|
||||
- xlnx,zynq-cc108
|
||||
- xlnx,zynq-zc702
|
||||
- xlnx,zynq-zc706
|
||||
- xlnx,zynq-zc770-xm010
|
||||
- xlnx,zynq-zc770-xm011
|
||||
- xlnx,zynq-zc770-xm012
|
||||
- xlnx,zynq-zc770-xm013
|
||||
- const: xlnx,zynq-7000
|
||||
|
||||
- items:
|
||||
- const: avnet,zynq-microzed
|
||||
- const: xlnx,zynq-microzed
|
||||
- const: xlnx,zynq-7000
|
||||
|
||||
- items:
|
||||
- const: avnet,zynq-zed
|
||||
- const: xlnx,zynq-zed
|
||||
- const: xlnx,zynq-7000
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- xlnx,zynqmp-zc1751
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: Xilinx internal board zc1232
|
||||
items:
|
||||
- const: xlnx,zynqmp-zc1232-revA
|
||||
- const: xlnx,zynqmp-zc1232
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: Xilinx internal board zc1254
|
||||
items:
|
||||
- const: xlnx,zynqmp-zc1254-revA
|
||||
- const: xlnx,zynqmp-zc1254
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: Xilinx internal board zc1275
|
||||
items:
|
||||
- const: xlnx,zynqmp-zc1275-revA
|
||||
- const: xlnx,zynqmp-zc1275
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: Xilinx 96boards compatible board zcu100
|
||||
items:
|
||||
- const: xlnx,zynqmp-zcu100-revC
|
||||
- const: xlnx,zynqmp-zcu100
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: Xilinx 96boards compatible board Ultra96
|
||||
items:
|
||||
- const: avnet,ultra96-rev1
|
||||
- const: avnet,ultra96
|
||||
- const: xlnx,zynqmp-zcu100-revC
|
||||
- const: xlnx,zynqmp-zcu100
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: Xilinx evaluation board zcu102
|
||||
items:
|
||||
- enum:
|
||||
- xlnx,zynqmp-zcu102-revA
|
||||
- xlnx,zynqmp-zcu102-revB
|
||||
- xlnx,zynqmp-zcu102-rev1.0
|
||||
- const: xlnx,zynqmp-zcu102
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: Xilinx evaluation board zcu104
|
||||
items:
|
||||
- enum:
|
||||
- xlnx,zynqmp-zcu104-revA
|
||||
- xlnx,zynqmp-zcu104-rev1.0
|
||||
- const: xlnx,zynqmp-zcu104
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: Xilinx evaluation board zcu106
|
||||
items:
|
||||
- enum:
|
||||
- xlnx,zynqmp-zcu106-revA
|
||||
- xlnx,zynqmp-zcu106-rev1.0
|
||||
- const: xlnx,zynqmp-zcu106
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
- description: Xilinx evaluation board zcu111
|
||||
items:
|
||||
- enum:
|
||||
- xlnx,zynqmp-zcu111-revA
|
||||
- xlnx,zynqmp-zcu11-rev1.0
|
||||
- const: xlnx,zynqmp-zcu111
|
||||
- const: xlnx,zynqmp
|
||||
|
||||
...
|
||||
@ -1,14 +0,0 @@
|
||||
ZTE platforms device tree bindings
|
||||
|
||||
---------------------------------------
|
||||
- ZX296702 board:
|
||||
Required root node properties:
|
||||
- compatible = "zte,zx296702-ad1", "zte,zx296702"
|
||||
|
||||
---------------------------------------
|
||||
- ZX296718 SoC:
|
||||
Required root node properties:
|
||||
- compatible = "zte,zx296718"
|
||||
|
||||
ZX296718 EVB board:
|
||||
- "zte,zx296718-evb"
|
||||
26
Bindings/arm/zte.yaml
Normal file
26
Bindings/arm/zte.yaml
Normal file
@ -0,0 +1,26 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/zte.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ZTE platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Jun Nie <jun.nie@linaro.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- zte,zx296702-ad1
|
||||
- const: zte,zx296702
|
||||
- items:
|
||||
- enum:
|
||||
- zte,zx296718-evb
|
||||
- const: zte,zx296718
|
||||
|
||||
...
|
||||
@ -1,11 +1,14 @@
|
||||
Device tree bindings for Allwinner A64 DE2 bus
|
||||
Device tree bindings for Allwinner DE2/3 bus
|
||||
|
||||
The Allwinner A64 DE2 is on a special bus, which needs a SRAM region (SRAM C)
|
||||
to be claimed for enabling the access.
|
||||
to be claimed for enabling the access. The DE3 on Allwinner H6 is at the same
|
||||
situation, and the binding also applies.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should contain "allwinner,sun50i-a64-de2"
|
||||
- compatible: Should be one of:
|
||||
- "allwinner,sun50i-a64-de2"
|
||||
- "allwinner,sun50i-h6-de3", "allwinner,sun50i-a64-de2"
|
||||
- reg: A resource specifier for the register space
|
||||
- #address-cells: Must be set to 1
|
||||
- #size-cells: Must be set to 1
|
||||
|
||||
@ -35,6 +35,7 @@ Required standard properties:
|
||||
"ti,sysc-omap3-sham"
|
||||
"ti,sysc-omap-aes"
|
||||
"ti,sysc-mcasp"
|
||||
"ti,sysc-dra7-mcasp"
|
||||
"ti,sysc-usb-host-fs"
|
||||
"ti,sysc-dra7-mcan"
|
||||
|
||||
|
||||
@ -11,6 +11,13 @@ Required Properties:
|
||||
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
|
||||
- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
|
||||
followed by the common "amlogic,meson-gx-aoclkc"
|
||||
- clocks: list of clock phandle, one for each entry clock-names.
|
||||
- clock-names: should contain the following:
|
||||
* "xtal" : the platform xtal
|
||||
* "mpeg-clk" : the main clock controller mother clock (aka clk81)
|
||||
* "ext-32k-0" : external 32kHz reference #0 if any (optional)
|
||||
* "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
|
||||
* "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
@ -40,8 +47,9 @@ ao_sysctrl: sys-ctrl@0 {
|
||||
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&xtal>, <&clkc CLKID_CLK81>;
|
||||
clock-names = "xtal", "mpeg-clk";
|
||||
};
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock and reset generated
|
||||
by the clock controller:
|
||||
|
||||
@ -9,6 +9,9 @@ Required Properties:
|
||||
"amlogic,gxbb-clkc" for GXBB SoC,
|
||||
"amlogic,gxl-clkc" for GXL and GXM SoC,
|
||||
"amlogic,axg-clkc" for AXG SoC.
|
||||
- clocks : list of clock phandle, one for each entry clock-names.
|
||||
- clock-names : should contain the following:
|
||||
* "xtal": the platform xtal
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
@ -31,6 +34,8 @@ sysctrl: system-controller@0 {
|
||||
clkc: clock-controller {
|
||||
#clock-cells = <1>;
|
||||
compatible = "amlogic,gxbb-clkc";
|
||||
clocks = <&xtal>;
|
||||
clock-names = "xtal";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -9,15 +9,13 @@ Required Properties:
|
||||
- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
|
||||
- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
|
||||
- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
|
||||
- reg: it must be composed by two tuples:
|
||||
0) physical base address of the xtal register and length of memory
|
||||
mapped region.
|
||||
1) physical base address of the clock controller and length of memory
|
||||
mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
|
||||
- reg: base address and size of the HHI system control register space.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
|
||||
@ -30,9 +28,8 @@ device tree sources).
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clkc: clock-controller@c1104000 {
|
||||
clkc: clock-controller {
|
||||
compatible = "amlogic,meson8b-clkc";
|
||||
reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
@ -13,6 +13,9 @@ Optional properties:
|
||||
management IC (PMIC) triggered via PMIC_STBY_REQ signal.
|
||||
Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
|
||||
be using "syscon-poweroff" driver instead.
|
||||
- clocks: list of clock specifiers, must contain an entry for each entry
|
||||
in clock-names
|
||||
- clock-names: valid names are "osc", "ckil", "ckih1", "anaclk1" and "anaclk2"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
|
||||
|
||||
104
Bindings/clock/imx7ulp-clock.txt
Normal file
104
Bindings/clock/imx7ulp-clock.txt
Normal file
@ -0,0 +1,104 @@
|
||||
* Clock bindings for Freescale i.MX7ULP
|
||||
|
||||
i.MX7ULP Clock functions are under joint control of the System
|
||||
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
|
||||
modules, and Core Mode Controller (CMC)1 blocks
|
||||
|
||||
The clocking scheme provides clear separation between M4 domain
|
||||
and A7 domain. Except for a few clock sources shared between two
|
||||
domains, such as the System Oscillator clock, the Slow IRC (SIRC),
|
||||
and and the Fast IRC clock (FIRCLK), clock sources and clock
|
||||
management are separated and contained within each domain.
|
||||
|
||||
M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
|
||||
A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
|
||||
|
||||
Note: this binding doc is only for A7 clock domain.
|
||||
|
||||
System Clock Generation (SCG) modules:
|
||||
---------------------------------------------------------------------
|
||||
The System Clock Generation (SCG) is responsible for clock generation
|
||||
and distribution across this device. Functions performed by the SCG
|
||||
include: clock reference selection, generation of clock used to derive
|
||||
processor, system, peripheral bus and external memory interface clocks,
|
||||
source selection for peripheral clocks and control of power saving
|
||||
clock gating mode.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "fsl,imx7ulp-scg1".
|
||||
- reg : Should contain registers location and length.
|
||||
- #clock-cells: Should be <1>.
|
||||
- clocks: Should contain the fixed input clocks.
|
||||
- clock-names: Should contain the following clock names:
|
||||
"rosc", "sosc", "sirc", "firc", "upll", "mpll".
|
||||
|
||||
Peripheral Clock Control (PCC) modules:
|
||||
---------------------------------------------------------------------
|
||||
The Peripheral Clock Control (PCC) is responsible for clock selection,
|
||||
optional division and clock gating mode for peripherals in their
|
||||
respected power domain
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx7ulp-pcc2",
|
||||
"fsl,imx7ulp-pcc3".
|
||||
- reg : Should contain registers location and length.
|
||||
- #clock-cells: Should be <1>.
|
||||
- clocks: Should contain the fixed input clocks.
|
||||
- clock-names: Should contain the following clock names:
|
||||
"nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2",
|
||||
"apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk",
|
||||
"mpll", "firc_bus_clk", "rosc", "spll_bus_clk";
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell.
|
||||
See include/dt-bindings/clock/imx7ulp-clock.h
|
||||
for the full list of i.MX7ULP clock IDs of each module.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx7ulp-clock.h>
|
||||
|
||||
scg1: scg1@403e0000 {
|
||||
compatible = "fsl,imx7ulp-scg1;
|
||||
reg = <0x403e0000 0x10000>;
|
||||
clocks = <&rosc>, <&sosc>, <&sirc>,
|
||||
<&firc>, <&upll>, <&mpll>;
|
||||
clock-names = "rosc", "sosc", "sirc",
|
||||
"firc", "upll", "mpll";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pcc2: pcc2@403f0000 {
|
||||
compatible = "fsl,imx7ulp-pcc2";
|
||||
reg = <0x403f0000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_DDR_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD2>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD1>,
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
|
||||
<&scg1 IMX7ULP_CLK_UPLL>,
|
||||
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_MIPI_PLL>,
|
||||
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_ROSC>,
|
||||
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
|
||||
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
|
||||
"apll_pfd2", "apll_pfd1", "apll_pfd0",
|
||||
"upll", "sosc_bus_clk", "mpll",
|
||||
"firc_bus_clk", "rosc", "spll_bus_clk";
|
||||
};
|
||||
|
||||
usdhc1: usdhc@40380000 {
|
||||
compatible = "fsl,imx7ulp-usdhc";
|
||||
reg = <0x40380000 0x10000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&pcc2 IMX7ULP_CLK_USDHC1>;
|
||||
clock-names ="ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
};
|
||||
20
Bindings/clock/imx8mq-clock.txt
Normal file
20
Bindings/clock/imx8mq-clock.txt
Normal file
@ -0,0 +1,20 @@
|
||||
* Clock bindings for NXP i.MX8M Quad
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8mq-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include the following entries:
|
||||
- "ckil"
|
||||
- "osc_25m"
|
||||
- "osc_27m"
|
||||
- "clk_ext1"
|
||||
- "clk_ext2"
|
||||
- "clk_ext3"
|
||||
- "clk_ext4"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
|
||||
for the full list of i.MX8M Quad clock IDs.
|
||||
51
Bindings/clock/imx8qxp-lpcg.txt
Normal file
51
Bindings/clock/imx8qxp-lpcg.txt
Normal file
@ -0,0 +1,51 @@
|
||||
* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
|
||||
|
||||
The Low-Power Clock Gate (LPCG) modules contain a local programming
|
||||
model to control the clock gates for the peripherals. An LPCG module
|
||||
is used to locally gate the clocks for the associated peripheral.
|
||||
|
||||
Note:
|
||||
This level of clock gating is provided after the clocks are generated
|
||||
by the SCU resources and clock controls. Thus even if the clock is
|
||||
enabled by these control bits, it might still not be running based
|
||||
on the base resource.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8qxp-lpcg-adma",
|
||||
"fsl,imx8qxp-lpcg-conn",
|
||||
"fsl,imx8qxp-lpcg-dc",
|
||||
"fsl,imx8qxp-lpcg-dsp",
|
||||
"fsl,imx8qxp-lpcg-gpu",
|
||||
"fsl,imx8qxp-lpcg-hsio",
|
||||
"fsl,imx8qxp-lpcg-img",
|
||||
"fsl,imx8qxp-lpcg-lsio",
|
||||
"fsl,imx8qxp-lpcg-vpu"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell.
|
||||
See the full list of clock IDs from:
|
||||
include/dt-bindings/clock/imx8qxp-clock.h
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx8qxp-clock.h>
|
||||
|
||||
conn_lpcg: clock-controller@5b200000 {
|
||||
compatible = "fsl,imx8qxp-lpcg-conn";
|
||||
reg = <0x5b200000 0xb0000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usdhc1: mmc@5b010000 {
|
||||
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x5b010000 0x10000>;
|
||||
clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>,
|
||||
<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>,
|
||||
<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>;
|
||||
clock-names = "ipg", "per", "ahb";
|
||||
};
|
||||
@ -18,4 +18,4 @@ Required Properties:
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>.
|
||||
All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
|
||||
|
||||
@ -35,6 +35,8 @@ be part of GCC and hence the TSENS properties can also be
|
||||
part of the GCC/clock-controller node.
|
||||
For more details on the TSENS properties please refer
|
||||
Documentation/devicetree/bindings/thermal/qcom-tsens.txt
|
||||
- protected-clocks : Protected clock specifier list as per common clock
|
||||
binding.
|
||||
|
||||
Example:
|
||||
clock-controller@900000 {
|
||||
@ -55,3 +57,17 @@ Example of GCC with TSENS properties:
|
||||
#reset-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
Example of GCC with protected-clocks properties:
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sdm845";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
|
||||
<GCC_LPASS_Q6_AXI_CLK>,
|
||||
<GCC_LPASS_SWAY_CLK>;
|
||||
};
|
||||
|
||||
22
Bindings/clock/qcom,gpucc.txt
Normal file
22
Bindings/clock/qcom,gpucc.txt
Normal file
@ -0,0 +1,22 @@
|
||||
Qualcomm Graphics Clock & Reset Controller Binding
|
||||
--------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain "qcom,sdm845-gpucc"
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : from common clock binding, shall contain 1
|
||||
- #reset-cells : from common reset binding, shall contain 1
|
||||
- #power-domain-cells : from generic power domain binding, shall contain 1
|
||||
- clocks : shall contain the XO clock
|
||||
- clock-names : shall be "xo"
|
||||
|
||||
Example:
|
||||
gpucc: clock-controller@5090000 {
|
||||
compatible = "qcom,sdm845-gpucc";
|
||||
reg = <0x5090000 0x9000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
};
|
||||
26
Bindings/clock/qcom,lpasscc.txt
Normal file
26
Bindings/clock/qcom,lpasscc.txt
Normal file
@ -0,0 +1,26 @@
|
||||
Qualcomm LPASS Clock Controller Binding
|
||||
-----------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain "qcom,sdm845-lpasscc"
|
||||
- #clock-cells : from common clock binding, shall contain 1.
|
||||
- reg : shall contain base register address and size,
|
||||
in the order
|
||||
Index-0 maps to LPASS_CC register region
|
||||
Index-1 maps to LPASS_QDSP6SS register region
|
||||
|
||||
Optional properties :
|
||||
- reg-names : register names of LPASS domain
|
||||
"cc", "qdsp6ss".
|
||||
|
||||
Example:
|
||||
|
||||
The below node has to be defined in the cases where the LPASS peripheral loader
|
||||
would bring the subsystem out of reset.
|
||||
|
||||
lpasscc: clock-controller@17014000 {
|
||||
compatible = "qcom,sdm845-lpasscc";
|
||||
reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
|
||||
reg-names = "cc", "qdsp6ss";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -16,6 +16,7 @@ Required properties :
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8996", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcs404", "qcom,rpmcc"
|
||||
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
|
||||
@ -6,8 +6,6 @@ Required properties :
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : from common clock binding, shall contain 1.
|
||||
- #power-domain-cells : from generic power domain binding, shall contain 1.
|
||||
|
||||
Optional properties :
|
||||
- #reset-cells : from common reset binding, shall contain 1.
|
||||
|
||||
Example:
|
||||
@ -16,4 +14,5 @@ Example:
|
||||
reg = <0xab00000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
@ -28,6 +28,12 @@ Required properties:
|
||||
* "fsl,p4080-clockgen"
|
||||
* "fsl,p5020-clockgen"
|
||||
* "fsl,p5040-clockgen"
|
||||
* "fsl,t1023-clockgen"
|
||||
* "fsl,t1024-clockgen"
|
||||
* "fsl,t1040-clockgen"
|
||||
* "fsl,t1042-clockgen"
|
||||
* "fsl,t2080-clockgen"
|
||||
* "fsl,t2081-clockgen"
|
||||
* "fsl,t4240-clockgen"
|
||||
* "fsl,b4420-clockgen"
|
||||
* "fsl,b4860-clockgen"
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Allwinner Display Engine 2.0 Clock Control Binding
|
||||
--------------------------------------------------
|
||||
Allwinner Display Engine 2.0/3.0 Clock Control Binding
|
||||
------------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible: must contain one of the following compatibles:
|
||||
@ -8,6 +8,7 @@ Required properties :
|
||||
- "allwinner,sun8i-v3s-de2-clk"
|
||||
- "allwinner,sun50i-a64-de2-clk"
|
||||
- "allwinner,sun50i-h5-de2-clk"
|
||||
- "allwinner,sun50i-h6-de3-clk"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
- clocks: phandle to the clocks feeding the display engine subsystem.
|
||||
|
||||
@ -22,6 +22,7 @@ Required properties :
|
||||
- "allwinner,sun50i-h5-ccu"
|
||||
- "allwinner,sun50i-h6-ccu"
|
||||
- "allwinner,sun50i-h6-r-ccu"
|
||||
- "allwinner,suniv-f1c100s-ccu"
|
||||
- "nextthing,gr8-ccu"
|
||||
|
||||
- reg: Must contain the registers base address and length
|
||||
|
||||
@ -14,6 +14,8 @@ Optional properties:
|
||||
- label: symbolic name for the connector,
|
||||
- type: size of the connector, should be specified in case of USB-A, USB-B
|
||||
non-fullsize connectors: "mini", "micro".
|
||||
- self-powered: Set this property if the usb device that has its own power
|
||||
source.
|
||||
|
||||
Optional properties for usb-c-connector:
|
||||
- power-role: should be one of "source", "sink" or "dual"(DRP) if typec
|
||||
|
||||
172
Bindings/cpufreq/cpufreq-qcom-hw.txt
Normal file
172
Bindings/cpufreq/cpufreq-qcom-hw.txt
Normal file
@ -0,0 +1,172 @@
|
||||
Qualcomm Technologies, Inc. CPUFREQ Bindings
|
||||
|
||||
CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
|
||||
SoCs to manage frequency in hardware. It is capable of controlling frequency
|
||||
for multiple clusters.
|
||||
|
||||
Properties:
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,cpufreq-hw".
|
||||
|
||||
- clocks
|
||||
Usage: required
|
||||
Value type: <phandle> From common clock binding.
|
||||
Definition: clock handle for XO clock and GPLL0 clock.
|
||||
|
||||
- clock-names
|
||||
Usage: required
|
||||
Value type: <string> From common clock binding.
|
||||
Definition: must be "xo", "alternate".
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Addresses and sizes for the memory of the HW bases in
|
||||
each frequency domain.
|
||||
- reg-names
|
||||
Usage: Optional
|
||||
Value type: <string>
|
||||
Definition: Frequency domain name i.e.
|
||||
"freq-domain0", "freq-domain1".
|
||||
|
||||
- #freq-domain-cells:
|
||||
Usage: required.
|
||||
Definition: Number of cells in a freqency domain specifier.
|
||||
|
||||
* Property qcom,freq-domain
|
||||
Devices supporting freq-domain must set their "qcom,freq-domain" property with
|
||||
phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch
|
||||
DCVS state together.
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
L3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_100>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_200>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_400>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_500>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x600>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_600>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x700>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_700>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
cpufreq_hw: cpufreq@17d43000 {
|
||||
compatible = "qcom,cpufreq-hw";
|
||||
reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
|
||||
reg-names = "freq-domain0", "freq-domain1";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#freq-domain-cells = <1>;
|
||||
};
|
||||
}
|
||||
@ -1,8 +1,12 @@
|
||||
Arm TrustZone CryptoCell cryptographic engine
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of: "arm,cryptocell-712-ree",
|
||||
"arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree".
|
||||
- compatible: Should be one of -
|
||||
"arm,cryptocell-713-ree"
|
||||
"arm,cryptocell-703-ree"
|
||||
"arm,cryptocell-712-ree"
|
||||
"arm,cryptocell-710-ree"
|
||||
"arm,cryptocell-630p-ree"
|
||||
- reg: Base physical address of the engine and length of memory mapped region.
|
||||
- interrupts: Interrupt number for the device.
|
||||
|
||||
|
||||
@ -6,6 +6,8 @@ Required properties:
|
||||
- interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ
|
||||
must be supplied, optionally Secure IRQ can be present, but
|
||||
is currently not implemented and not used.
|
||||
- clocks : Clock reference (only required on some SOCs: 6ull and 6sll).
|
||||
- clock-names : Must be "dcp".
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
@ -67,6 +67,8 @@ Required properties:
|
||||
Optional properties:
|
||||
- power-domains: Optional phandle to associated power domain as described in
|
||||
the file ../power/power_domain.txt
|
||||
- amlogic,canvas: phandle to canvas provider node as described in the file
|
||||
../soc/amlogic/amlogic,canvas.txt
|
||||
|
||||
Required nodes:
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
* ARM PrimeCell Color LCD Controller PL110/PL111
|
||||
|
||||
See also Documentation/devicetree/bindings/arm/primecell.txt
|
||||
See also Documentation/devicetree/bindings/arm/primecell.yaml
|
||||
|
||||
Required properties:
|
||||
|
||||
|
||||
@ -13,6 +13,7 @@ Required properties:
|
||||
- "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
|
||||
- "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
|
||||
- "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
|
||||
- "renesas,r8a77965-lvds" for R8A77965 (R-Car M3-N) compatible LVDS encoders
|
||||
- "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
|
||||
- "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders
|
||||
- "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders
|
||||
|
||||
26
Bindings/display/himax,hx8357d.txt
Normal file
26
Bindings/display/himax,hx8357d.txt
Normal file
@ -0,0 +1,26 @@
|
||||
Himax HX8357D display panels
|
||||
|
||||
This binding is for display panels using a Himax HX8357D controller in SPI
|
||||
mode, such as the Adafruit 3.5" TFT for Raspberry Pi.
|
||||
|
||||
Required properties:
|
||||
- compatible: "adafruit,yx350hv15", "himax,hx8357d"
|
||||
- dc-gpios: D/C pin
|
||||
- reg: address of the panel on the SPI bus
|
||||
|
||||
The node for this driver must be a child node of a SPI controller, hence
|
||||
all mandatory properties described in ../spi/spi-bus.txt must be specified.
|
||||
|
||||
Optional properties:
|
||||
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
|
||||
Example:
|
||||
display@0{
|
||||
compatible = "adafruit,yx350hv15", "himax,hx8357d";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <32000000>;
|
||||
dc-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
|
||||
rotation = <90>;
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
@ -106,6 +106,7 @@ Required properties:
|
||||
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
|
||||
- clock-names: the following clocks are required:
|
||||
* "iface"
|
||||
* "ref" (only required for new DTS files/entries)
|
||||
For 28nm HPM/LP, 28nm 8960 PHYs:
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
For 20nm PHY:
|
||||
|
||||
@ -1,11 +1,13 @@
|
||||
Qualcomm adreno/snapdragon GPU
|
||||
|
||||
Required properties:
|
||||
- compatible: "qcom,adreno-XYZ.W", "qcom,adreno"
|
||||
- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
|
||||
"amd,imageon-XYZ.W", "amd,imageon"
|
||||
for example: "qcom,adreno-306.0", "qcom,adreno"
|
||||
Note that you need to list the less specific "qcom,adreno" (since this
|
||||
is what the device is matched on), in addition to the more specific
|
||||
with the chip-id.
|
||||
If "amd,imageon" is used, there should be no top level msm device.
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the gpu.
|
||||
- clocks: device clocks
|
||||
@ -25,7 +27,6 @@ Example:
|
||||
reg = <0x04300000 0x20000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
interrupts = <GIC_SPI 80 0>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
clock-names =
|
||||
"core",
|
||||
"iface",
|
||||
|
||||
@ -38,6 +38,8 @@ Required properties:
|
||||
Optional properties:
|
||||
- clock-names: the following clocks are optional:
|
||||
* "lut_clk"
|
||||
- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be
|
||||
used for LCDC. This is only valid for 18bpp panels.
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
12
Bindings/display/panel/auo,g101evn010
Normal file
12
Bindings/display/panel/auo,g101evn010
Normal file
@ -0,0 +1,12 @@
|
||||
AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "auo,g101evn010"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
Optional properties:
|
||||
- backlight: as specified in the base binding
|
||||
- enable-gpios: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
12
Bindings/display/panel/bananapi,s070wv20-ct16.txt
Normal file
12
Bindings/display/panel/bananapi,s070wv20-ct16.txt
Normal file
@ -0,0 +1,12 @@
|
||||
Banana Pi 7" (S070WV20-CT16) TFT LCD Panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "bananapi,s070wv20-ct16"
|
||||
- power-supply: see ./panel-common.txt
|
||||
|
||||
Optional properties:
|
||||
- enable-gpios: see ./simple-panel.txt
|
||||
- backlight: see ./simple-panel.txt
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in ./simple-panel.txt.
|
||||
12
Bindings/display/panel/cdtech,s043wq26h-ct7.txt
Normal file
12
Bindings/display/panel/cdtech,s043wq26h-ct7.txt
Normal file
@ -0,0 +1,12 @@
|
||||
CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "cdtech,s043wq26h-ct7"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
Optional properties:
|
||||
- backlight: as specified in the base binding
|
||||
- enable-gpios: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
12
Bindings/display/panel/cdtech,s070wv95-ct16.txt
Normal file
12
Bindings/display/panel/cdtech,s070wv95-ct16.txt
Normal file
@ -0,0 +1,12 @@
|
||||
CDTech(H.K.) Electronics Limited 7" 800x480 color TFT-LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "cdtech,s070wv95-ct16"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
Optional properties:
|
||||
- backlight: as specified in the base binding
|
||||
- enable-gpios: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
12
Bindings/display/panel/dlc,dlc1010gig.txt
Normal file
12
Bindings/display/panel/dlc,dlc1010gig.txt
Normal file
@ -0,0 +1,12 @@
|
||||
DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "dlc,dlc1010gig"
|
||||
- power-supply: See simple-panel.txt
|
||||
|
||||
Optional properties:
|
||||
- enable-gpios: See simple-panel.txt
|
||||
- backlight: See simple-panel.txt
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
42
Bindings/display/panel/olimex,lcd-olinuxino.txt
Normal file
42
Bindings/display/panel/olimex,lcd-olinuxino.txt
Normal file
@ -0,0 +1,42 @@
|
||||
Binding for Olimex Ltd. LCD-OLinuXino bridge panel.
|
||||
|
||||
This device can be used as bridge between a host controller and LCD panels.
|
||||
Currently supported LCDs are:
|
||||
- LCD-OLinuXino-4.3TS
|
||||
- LCD-OLinuXino-5
|
||||
- LCD-OLinuXino-7
|
||||
- LCD-OLinuXino-10
|
||||
|
||||
The panel itself contains:
|
||||
- AT24C16C EEPROM holding panel identification and timing requirements
|
||||
- AR1021 resistive touch screen controller (optional)
|
||||
- FT5x6 capacitive touch screnn controller (optional)
|
||||
- GT911/GT928 capacitive touch screen controller (optional)
|
||||
|
||||
The above chips share same I2C bus. The EEPROM is factory preprogrammed with
|
||||
device information (id, serial, etc.) and timing requirements.
|
||||
|
||||
Touchscreen bingings can be found in these files:
|
||||
- input/touchscreen/goodix.txt
|
||||
- input/touchscreen/edt-ft5x06.txt
|
||||
- input/touchscreen/ar1021.txt
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "olimex,lcd-olinuxino"
|
||||
- reg: address of the configuration EEPROM, should be <0x50>
|
||||
- power-supply: phandle of the regulator that provides the supply voltage
|
||||
|
||||
Optional properties:
|
||||
- enable-gpios: GPIO pin to enable or disable the panel
|
||||
- backlight: phandle of the backlight device attacked to the panel
|
||||
|
||||
Example:
|
||||
&i2c2 {
|
||||
panel@50 {
|
||||
compatible = "olimex,lcd-olinuxino";
|
||||
reg = <0x50>;
|
||||
power-supply = <®_vcc5v0>;
|
||||
enable-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>;
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
};
|
||||
30
Bindings/display/panel/samsung,s6d16d0.txt
Normal file
30
Bindings/display/panel/samsung,s6d16d0.txt
Normal file
@ -0,0 +1,30 @@
|
||||
Samsung S6D16D0 4" 864x480 AMOLED panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be:
|
||||
"samsung,s6d16d0",
|
||||
- reg: the virtual channel number of a DSI peripheral
|
||||
- vdd1-supply: I/O voltage supply
|
||||
- reset-gpios: a GPIO spec for the reset pin (active low)
|
||||
|
||||
The device node can contain one 'port' child node with one child
|
||||
'endpoint' node, according to the bindings defined in
|
||||
media/video-interfaces.txt. This node should describe panel's video bus.
|
||||
|
||||
Example:
|
||||
&dsi {
|
||||
...
|
||||
|
||||
panel@0 {
|
||||
compatible = "samsung,s6d16d0";
|
||||
reg = <0>;
|
||||
vdd1-supply = <&foo>;
|
||||
reset-gpios = <&foo_gpio 0 GPIO_ACTIVE_LOW>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,47 +1,70 @@
|
||||
TPO TPG110 Panel
|
||||
================
|
||||
|
||||
This binding builds on the DPI bindings, adding a few properties
|
||||
as a superset of a DPI. See panel-dpi.txt for the required DPI
|
||||
bindings.
|
||||
This panel driver is a component that acts as an intermediary
|
||||
between an RGB output and a variety of panels. The panel
|
||||
driver is strapped up in electronics to the desired resolution
|
||||
and other properties, and has a control interface over 3WIRE
|
||||
SPI. By talking to the TPG110 over SPI, the strapped properties
|
||||
can be discovered and the hardware is therefore mostly
|
||||
self-describing.
|
||||
|
||||
+--------+
|
||||
SPI -> | TPO | -> physical display
|
||||
RGB -> | TPG110 |
|
||||
+--------+
|
||||
|
||||
If some electrical strap or alternate resolution is desired,
|
||||
this can be set up by taking software control of the display
|
||||
over the SPI interface. The interface can also adjust
|
||||
for properties of the display such as gamma correction and
|
||||
certain electrical driving levels.
|
||||
|
||||
The TPG110 does not know the physical dimensions of the panel
|
||||
connected, so this needs to be specified in the device tree.
|
||||
|
||||
It requires a GPIO line for control of its reset line.
|
||||
|
||||
The serial protocol has line names that resemble I2C but the
|
||||
protocol is not I2C but 3WIRE SPI.
|
||||
|
||||
Required properties:
|
||||
- compatible : "tpo,tpg110"
|
||||
- compatible : one of:
|
||||
"ste,nomadik-nhk15-display", "tpo,tpg110"
|
||||
"tpo,tpg110"
|
||||
- grestb-gpios : panel reset GPIO
|
||||
- scen-gpios : serial control enable GPIO
|
||||
- scl-gpios : serial control clock line GPIO
|
||||
- sda-gpios : serial control data line GPIO
|
||||
- width-mm : see display/panel/panel-common.txt
|
||||
- height-mm : see display/panel/panel-common.txt
|
||||
|
||||
Required nodes:
|
||||
- Video port for DPI input, see panel-dpi.txt
|
||||
- Panel timing for DPI setup, see panel-dpi.txt
|
||||
The device needs to be a child of an SPI bus, see
|
||||
spi/spi-bus.txt. The SPI child must set the following
|
||||
properties:
|
||||
- spi-3wire
|
||||
- spi-max-frequency = <3000000>;
|
||||
as these are characteristics of this device.
|
||||
|
||||
The device node can contain one 'port' child node with one child
|
||||
'endpoint' node, according to the bindings defined in
|
||||
media/video-interfaces.txt. This node should describe panel's video bus.
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
panel {
|
||||
compatible = "tpo,tpg110", "panel-dpi";
|
||||
grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>;
|
||||
scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
||||
scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
panel: display@0 {
|
||||
compatible = "tpo,tpg110";
|
||||
reg = <0>;
|
||||
spi-3wire;
|
||||
/* 320 ns min period ~= 3 MHz */
|
||||
spi-max-frequency = <3000000>;
|
||||
/* Width and height from data sheet */
|
||||
width-mm = <116>;
|
||||
height-mm = <87>;
|
||||
grestb-gpios = <&foo_gpio 5 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&bl>;
|
||||
|
||||
port {
|
||||
nomadik_clcd_panel: endpoint {
|
||||
remote-endpoint = <&nomadik_clcd_pads>;
|
||||
remote-endpoint = <&foo>;
|
||||
};
|
||||
};
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <33200000>;
|
||||
hactive = <800>;
|
||||
hback-porch = <216>;
|
||||
hfront-porch = <40>;
|
||||
hsync-len = <1>;
|
||||
vactive = <480>;
|
||||
vback-porch = <35>;
|
||||
vfront-porch = <10>;
|
||||
vsync-len = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user