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Split CESA memory resource into TDMA and CESA regs

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TDMA and CESA registers are placed in different ranges of memory. Split
memory resource in DTS to reflect that. This change is needed to support
multiple CESA nodes as otherwise the ranges of different nodes would
overlap.

In consequence, CESA_WRITE and CESA_READ macros have been split depending
on which range of registers is accessed. Offsets for CESA registers have
been modified as the base address has changed.

Submitted by:	Michal Stanek <mst@semihalf.com>
Obtained from:	Semihalf
Sponsored by:	Stormshield
Differential revision:	https://reviews.freebsd.org/D6217
This commit is contained in:
Zbigniew Bodek 2016-06-02 18:35:35 +00:00
parent 5d7cb9a803
commit 22c7a03178
8 changed files with 62 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
sys/boot/fdt/dts/arm/db78100.dts
View File

@ -283,7 +283,8 @@
crypto@90000 {
compatible = "mrvl,cesa";
reg = <0x90000 0x10000>;
reg = <0x90000 0x1000 /* tdma base reg chan 0 */
0x9D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <19>;
interrupt-parent = <&PIC>;
};

3
sys/boot/fdt/dts/arm/db88f6281.dts
View File

@ -221,7 +221,8 @@
crypto@30000 {
compatible = "mrvl,cesa";
reg = <0x30000 0x10000>;
reg = <0x30000 0x1000 /* tdma base reg chan 0 */
0x3D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <22>;
interrupt-parent = <&PIC>;

3
sys/boot/fdt/dts/arm/dockstar.dts
View File

@ -206,7 +206,8 @@
crypto@30000 {
compatible = "mrvl,cesa";
reg = <0x30000 0x10000>;
reg = <0x30000 0x1000 /* tdma base reg chan 0 */
0x3D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <22>;
interrupt-parent = <&PIC>;

3
sys/boot/fdt/dts/arm/dreamplug-1001.dts
View File

@ -270,7 +270,8 @@
crypto@30000 {
compatible = "mrvl,cesa";
reg = <0x30000 0x10000>;
reg = <0x30000 0x1000 /* tdma base reg chan 0 */
0x3D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <22>;
interrupt-parent = <&PIC>;

3
sys/boot/fdt/dts/arm/dreamplug-1001N.dts
View File

@ -291,7 +291,8 @@
crypto@30000 {
compatible = "mrvl,cesa";
reg = <0x30000 0x10000>;
reg = <0x30000 0x1000 /* tdma base reg chan 0 */
0x3D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <22>;
interrupt-parent = <&PIC>;

3
sys/boot/fdt/dts/arm/sheevaplug.dts
View File

@ -218,7 +218,8 @@
crypto@30000 {
compatible = "mrvl,cesa";
reg = <0x30000 0x10000>;
reg = <0x30000 0x1000 /* tdma base reg chan 0 */
0x3D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <22>;
interrupt-parent = <&PIC>;

53
sys/dev/cesa/cesa.c
View File

@ -83,6 +83,7 @@ static int decode_win_cesa_setup(struct cesa_softc *sc);
static struct resource_spec cesa_res_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_MEMORY, 1, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
{ -1, 0 }
};
@ -940,8 +941,8 @@ cesa_execute(struct cesa_softc *sc)
cr = STAILQ_FIRST(&sc->sc_queued_requests);
ctd = STAILQ_FIRST(&cr->cr_tdesc);
CESA_WRITE(sc, CESA_TDMA_ND, ctd->ctd_cthd_paddr);
CESA_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE);
CESA_TDMA_WRITE(sc, CESA_TDMA_ND, ctd->ctd_cthd_paddr);
CESA_REG_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE);
CESA_UNLOCK(sc, requests);
}
@ -1056,9 +1057,6 @@ cesa_attach(device_t dev)
goto err0;
}
sc->sc_bsh = rman_get_bushandle(*(sc->sc_res));
sc->sc_bst = rman_get_bustag(*(sc->sc_res));
/* Setup CESA decoding windows */
error = decode_win_cesa_setup(sc);
if (error) {
@ -1074,8 +1072,8 @@ cesa_attach(device_t dev)
}
/* Setup interrupt handler */
error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
NULL, cesa_intr, sc, &(sc->sc_icookie));
error = bus_setup_intr(dev, sc->sc_res[RES_CESA_IRQ], INTR_TYPE_NET |
INTR_MPSAFE, NULL, cesa_intr, sc, &(sc->sc_icookie));
if (error) {
device_printf(dev, "could not setup engine completion irq\n");
goto err2;
@ -1174,8 +1172,9 @@ cesa_attach(device_t dev)
* - Outstanding reads enabled,
* - No byte-swap.
*/
CESA_WRITE(sc, CESA_TDMA_CR, CESA_TDMA_CR_DBL128 | CESA_TDMA_CR_SBL128 |
CESA_TDMA_CR_ORDEN | CESA_TDMA_CR_NBS | CESA_TDMA_CR_ENABLE);
CESA_TDMA_WRITE(sc, CESA_TDMA_CR, CESA_TDMA_CR_DBL128 |
CESA_TDMA_CR_SBL128 | CESA_TDMA_CR_ORDEN | CESA_TDMA_CR_NBS |
CESA_TDMA_CR_ENABLE);
/*
* Initialize SA:
@ -1183,15 +1182,15 @@ cesa_attach(device_t dev)
* - Multi-packet chain mode,
* - Cooperation with TDMA enabled.
*/
CESA_WRITE(sc, CESA_SA_DPR, 0);
CESA_WRITE(sc, CESA_SA_CR, CESA_SA_CR_ACTIVATE_TDMA |
CESA_REG_WRITE(sc, CESA_SA_DPR, 0);
CESA_REG_WRITE(sc, CESA_SA_CR, CESA_SA_CR_ACTIVATE_TDMA |
CESA_SA_CR_WAIT_FOR_TDMA | CESA_SA_CR_MULTI_MODE);
/* Unmask interrupts */
CESA_WRITE(sc, CESA_ICR, 0);
CESA_WRITE(sc, CESA_ICM, CESA_ICM_ACCTDMA | sc->sc_tperr);
CESA_WRITE(sc, CESA_TDMA_ECR, 0);
CESA_WRITE(sc, CESA_TDMA_EMR, CESA_TDMA_EMR_MISS |
CESA_REG_WRITE(sc, CESA_ICR, 0);
CESA_REG_WRITE(sc, CESA_ICM, CESA_ICM_ACCTDMA | sc->sc_tperr);
CESA_TDMA_WRITE(sc, CESA_TDMA_ECR, 0);
CESA_TDMA_WRITE(sc, CESA_TDMA_EMR, CESA_TDMA_EMR_MISS |
CESA_TDMA_EMR_DOUBLE_HIT | CESA_TDMA_EMR_BOTH_HIT |
CESA_TDMA_EMR_DATA_ERROR);
@ -1224,7 +1223,7 @@ cesa_attach(device_t dev)
err4:
bus_dma_tag_destroy(sc->sc_data_dtag);
err3:
bus_teardown_intr(dev, sc->sc_res[1], sc->sc_icookie);
bus_teardown_intr(dev, sc->sc_res[RES_CESA_IRQ], sc->sc_icookie);
err2:
#if defined(SOC_MV_ARMADA38X)
bus_space_unmap(fdtbus_bs_tag, sc->sc_sram_base_va, sc->sc_sram_size);
@ -1251,8 +1250,8 @@ cesa_detach(device_t dev)
/* TODO: Wait for queued requests completion before shutdown. */
/* Mask interrupts */
CESA_WRITE(sc, CESA_ICM, 0);
CESA_WRITE(sc, CESA_TDMA_EMR, 0);
CESA_REG_WRITE(sc, CESA_ICM, 0);
CESA_TDMA_WRITE(sc, CESA_TDMA_EMR, 0);
/* Unregister from OCF */
crypto_unregister_all(sc->sc_cid);
@ -1271,7 +1270,7 @@ cesa_detach(device_t dev)
bus_dma_tag_destroy(sc->sc_data_dtag);
/* Stop interrupt */
bus_teardown_intr(dev, sc->sc_res[1], sc->sc_icookie);
bus_teardown_intr(dev, sc->sc_res[RES_CESA_IRQ], sc->sc_icookie);
/* Relase I/O and IRQ resources */
bus_release_resources(dev, cesa_res_spec, sc->sc_res);
@ -1302,10 +1301,10 @@ cesa_intr(void *arg)
sc = arg;
/* Ack interrupt */
ecr = CESA_READ(sc, CESA_TDMA_ECR);
CESA_WRITE(sc, CESA_TDMA_ECR, 0);
icr = CESA_READ(sc, CESA_ICR);
CESA_WRITE(sc, CESA_ICR, 0);
ecr = CESA_TDMA_READ(sc, CESA_TDMA_ECR);
CESA_TDMA_WRITE(sc, CESA_TDMA_ECR, 0);
icr = CESA_REG_READ(sc, CESA_ICR);
CESA_REG_WRITE(sc, CESA_ICR, 0);
/* Check for TDMA errors */
if (ecr & CESA_TDMA_ECR_MISS) {
@ -1676,8 +1675,8 @@ decode_win_cesa_setup(struct cesa_softc *sc)
/* Disable and clear all CESA windows */
for (i = 0; i < MV_WIN_CESA_MAX; i++) {
CESA_WRITE(sc, MV_WIN_CESA_BASE(i), 0);
CESA_WRITE(sc, MV_WIN_CESA_CTRL(i), 0);
CESA_TDMA_WRITE(sc, MV_WIN_CESA_BASE(i), 0);
CESA_TDMA_WRITE(sc, MV_WIN_CESA_CTRL(i), 0);
}
/* Fill CESA TDMA decoding windows with information acquired from DTS */
@ -1691,8 +1690,8 @@ decode_win_cesa_setup(struct cesa_softc *sc)
(MV_WIN_DDR_ATTR(i) << MV_WIN_CPU_ATTR_SHIFT) |
(MV_WIN_DDR_TARGET << MV_WIN_CPU_TARGET_SHIFT) |
MV_WIN_CPU_ENABLE_BIT);
CESA_WRITE(sc, MV_WIN_CESA_BASE(i), br);
CESA_WRITE(sc, MV_WIN_CESA_CTRL(i), cr);
CESA_TDMA_WRITE(sc, MV_WIN_CESA_BASE(i), br);
CESA_TDMA_WRITE(sc, MV_WIN_CESA_CTRL(i), cr);
}
}

37
sys/dev/cesa/cesa.h
View File

@ -93,10 +93,15 @@
mtx_assert(&(sc)->sc_ ## what ## _lock, MA_OWNED)
/* Registers read/write macros */
#define CESA_READ(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
#define CESA_WRITE(sc, reg, val) \
bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
#define CESA_REG_READ(sc, reg) \
bus_read_4((sc)->sc_res[RES_CESA_REGS], (reg))
#define CESA_REG_WRITE(sc, reg, val) \
bus_write_4((sc)->sc_res[RES_CESA_REGS], (reg), (val))
#define CESA_TDMA_READ(sc, reg) \
bus_read_4((sc)->sc_res[RES_TDMA_REGS], (reg))
#define CESA_TDMA_WRITE(sc, reg, val) \
bus_write_4((sc)->sc_res[RES_TDMA_REGS], (reg), (val))
/* Generic allocator for objects */
#define CESA_GENERIC_ALLOC_LOCKED(sc, obj, pool) do { \
@ -126,6 +131,14 @@
#define CESA_DATA(offset) \
(sizeof(struct cesa_sa_hdesc) + sizeof(struct cesa_sa_data) + offset)
/* CESA memory and IRQ resources */
enum cesa_res_type {
RES_TDMA_REGS,
RES_CESA_REGS,
RES_CESA_IRQ,
RES_CESA_NUM
};
struct cesa_tdma_hdesc {
uint16_t cthd_byte_count;
uint16_t cthd_flags;
@ -220,11 +233,9 @@ struct cesa_packet {
struct cesa_softc {
device_t sc_dev;
int32_t sc_cid;
struct resource *sc_res[2];
struct resource *sc_res[RES_CESA_NUM];
void *sc_icookie;
bus_dma_tag_t sc_data_dtag;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
int sc_error;
int sc_tperr;
@ -303,11 +314,11 @@ struct cesa_chain_info {
#define CESA_CSHD_FRAG_MIDDLE (3U << 30)
/* CESA registers definitions */
#define CESA_ICR 0xDE20
#define CESA_ICR 0x0E20
#define CESA_ICR_ACCTDMA (1 << 7)
#define CESA_ICR_TPERR (1 << 12)
#define CESA_ICM 0xDE24
#define CESA_ICM 0x0E24
#define CESA_ICM_ACCTDMA CESA_ICR_ACCTDMA
#define CESA_ICM_TPERR CESA_ICR_TPERR
@ -341,17 +352,17 @@ struct cesa_chain_info {
#define MV_WIN_CESA_MAX 4
/* CESA SA registers definitions */
#define CESA_SA_CMD 0xDE00
#define CESA_SA_CMD 0x0E00
#define CESA_SA_CMD_ACTVATE (1 << 0)
#define CESA_SA_DPR 0xDE04
#define CESA_SA_DPR 0x0E04
#define CESA_SA_CR 0xDE08
#define CESA_SA_CR 0x0E08
#define CESA_SA_CR_WAIT_FOR_TDMA (1 << 7)
#define CESA_SA_CR_ACTIVATE_TDMA (1 << 9)
#define CESA_SA_CR_MULTI_MODE (1 << 11)
#define CESA_SA_SR 0xDE0C
#define CESA_SA_SR 0x0E0C
#define CESA_SA_SR_ACTIVE (1 << 0)
#endif