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sfxge(4): move legacy board config to ef10 NIC board cfg

Browse Source 
Submitted by:   Andy Moreton <amoreton at solarflare.com>
Sponsored by:   Solarflare Communications, Inc.
Differential Revision:  https://reviews.freebsd.org/D18187
This commit is contained in:
Andrew Rybchenko 2018-11-28 06:54:49 +00:00
parent d36ea92c49
commit 233c1e5e89
4 changed files with 45 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
sys/dev/sfxge/common/ef10_nic.c
View File

@ -1575,6 +1575,7 @@ ef10_nic_board_cfg(
const efx_nic_ops_t *enop = enp->en_enop;
efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t board_type = 0;
uint32_t port;
uint32_t pf;
uint32_t vf;
@ -1632,13 +1633,28 @@ ef10_nic_board_cfg(
EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
/* Board configuration (legacy) */
rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
if (rc != 0) {
/* Unprivileged functions may not be able to read board cfg */
if (rc == EACCES)
board_type = 0;
else
goto fail5;
}
encp->enc_board_type = board_type;
encp->enc_clk_mult = 1; /* not used for EF10 */
/* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)
if (rc != EACCES)
goto fail5;
goto fail6;
return (0);
fail6:
EFSYS_PROBE(fail6);
fail5:
EFSYS_PROBE(fail5);
fail4:

36
sys/dev/sfxge/common/hunt_nic.c
View File

@ -104,7 +104,6 @@ hunt_board_cfg(
__in efx_nic_t *enp)
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t board_type = 0;
ef10_link_state_t els;
efx_port_t *epp = &(enp->en_port);
uint32_t mask;
@ -124,26 +123,13 @@ hunt_board_cfg(
EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
/* Board configuration */
rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
if (rc != 0) {
/* Unprivileged functions may not be able to read board cfg */
if (rc == EACCES)
board_type = 0;
else
goto fail1;
}
encp->enc_board_type = board_type;
encp->enc_clk_mult = 1; /* not used for Huntington */
/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
goto fail2;
goto fail1;
/* Obtain the default PHY advertised capabilities */
if ((rc = ef10_phy_get_link(enp, &els)) != 0)
goto fail3;
goto fail2;
epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
epp->ep_adv_cap_mask = els.els_adv_cap_mask;
@ -174,7 +160,7 @@ hunt_board_cfg(
else if ((rc == ENOTSUP) || (rc == ENOENT))
encp->enc_bug35388_workaround = B_FALSE;
else
goto fail4;
goto fail3;
/*
* If the bug41750 workaround is enabled, then do not test interrupts,
@ -193,7 +179,7 @@ hunt_board_cfg(
} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
encp->enc_bug41750_workaround = B_FALSE;
} else {
goto fail5;
goto fail4;
}
if (EFX_PCI_FUNCTION_IS_VF(encp)) {
/* Interrupt testing does not work for VFs. See bug50084. */
@ -231,12 +217,12 @@ hunt_board_cfg(
} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
encp->enc_bug26807_workaround = B_FALSE;
} else {
goto fail6;
goto fail5;
}
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
goto fail7;
goto fail6;
/*
* The Huntington timer quantum is 1536 sysclk cycles, documented for
@ -255,7 +241,7 @@ hunt_board_cfg(
/* Check capabilities of running datapath firmware */
if ((rc = ef10_get_datapath_caps(enp)) != 0)
goto fail8;
goto fail7;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
@ -305,13 +291,13 @@ hunt_board_cfg(
* can result in time-of-check/time-of-use bugs.
*/
if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
goto fail9;
goto fail8;
encp->enc_privilege_mask = mask;
/* Get interrupt vector limits */
if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
if (EFX_PCI_FUNCTION_IS_PF(encp))
goto fail10;
goto fail9;
/* Ignore error (cannot query vector limits from a VF). */
base = 0;
@ -327,7 +313,7 @@ hunt_board_cfg(
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
goto fail11;
goto fail10;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
/* All Huntington devices have a PCIe Gen3, 8 lane connector */
@ -335,8 +321,6 @@ hunt_board_cfg(
return (0);
fail11:
EFSYS_PROBE(fail11);
fail10:
EFSYS_PROBE(fail10);
fail9:

34
sys/dev/sfxge/common/medford2_nic.c
View File

@ -78,7 +78,6 @@ medford2_board_cfg(
__in efx_nic_t *enp)
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t board_type = 0;
ef10_link_state_t els;
efx_port_t *epp = &(enp->en_port);
uint32_t mask;
@ -102,26 +101,13 @@ medford2_board_cfg(
encp->enc_vi_window_shift = vi_window_shift;
/* Board configuration */
rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
if (rc != 0) {
/* Unprivileged functions may not be able to read board cfg */
if (rc == EACCES)
board_type = 0;
else
goto fail2;
}
encp->enc_board_type = board_type;
encp->enc_clk_mult = 1; /* not used for Medford2 */
/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
goto fail3;
goto fail2;
/* Obtain the default PHY advertised capabilities */
if ((rc = ef10_phy_get_link(enp, &els)) != 0)
goto fail4;
goto fail3;
epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
epp->ep_adv_cap_mask = els.els_adv_cap_mask;
@ -165,11 +151,11 @@ medford2_board_cfg(
else if ((rc == ENOTSUP) || (rc == ENOENT))
encp->enc_bug61265_workaround = B_FALSE;
else
goto fail5;
goto fail4;
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
goto fail6;
goto fail5;
/*
* The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
@ -181,7 +167,7 @@ medford2_board_cfg(
/* Check capabilities of running datapath firmware */
if ((rc = ef10_get_datapath_caps(enp)) != 0)
goto fail7;
goto fail6;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
@ -189,7 +175,7 @@ medford2_board_cfg(
/* Get the RX DMA end padding alignment configuration */
if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
if (rc != EACCES)
goto fail8;
goto fail7;
/* Assume largest tail padding size supported by hardware */
end_padding = 256;
@ -241,13 +227,13 @@ medford2_board_cfg(
* can result in time-of-check/time-of-use bugs.
*/
if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
goto fail9;
goto fail8;
encp->enc_privilege_mask = mask;
/* Get interrupt vector limits */
if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
if (EFX_PCI_FUNCTION_IS_PF(encp))
goto fail10;
goto fail9;
/* Ignore error (cannot query vector limits from a VF). */
base = 0;
@ -270,14 +256,12 @@ medford2_board_cfg(
rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
goto fail11;
goto fail10;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
fail11:
EFSYS_PROBE(fail11);
fail10:
EFSYS_PROBE(fail10);
fail9:

34
sys/dev/sfxge/common/medford_nic.c
View File

@ -74,7 +74,6 @@ medford_board_cfg(
__in efx_nic_t *enp)
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t board_type = 0;
ef10_link_state_t els;
efx_port_t *epp = &(enp->en_port);
uint32_t mask;
@ -99,26 +98,13 @@ medford_board_cfg(
EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
/* Board configuration */
rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
if (rc != 0) {
/* Unprivileged functions may not be able to read board cfg */
if (rc == EACCES)
board_type = 0;
else
goto fail1;
}
encp->enc_board_type = board_type;
encp->enc_clk_mult = 1; /* not used for Medford */
/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
goto fail2;
goto fail1;
/* Obtain the default PHY advertised capabilities */
if ((rc = ef10_phy_get_link(enp, &els)) != 0)
goto fail3;
goto fail2;
epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
epp->ep_adv_cap_mask = els.els_adv_cap_mask;
@ -162,11 +148,11 @@ medford_board_cfg(
else if ((rc == ENOTSUP) || (rc == ENOENT))
encp->enc_bug61265_workaround = B_FALSE;
else
goto fail4;
goto fail3;
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
goto fail5;
goto fail4;
/*
* The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
@ -178,7 +164,7 @@ medford_board_cfg(
/* Check capabilities of running datapath firmware */
if ((rc = ef10_get_datapath_caps(enp)) != 0)
goto fail6;
goto fail5;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
@ -186,7 +172,7 @@ medford_board_cfg(
/* Get the RX DMA end padding alignment configuration */
if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
if (rc != EACCES)
goto fail7;
goto fail6;
/* Assume largest tail padding size supported by hardware */
end_padding = 256;
@ -238,13 +224,13 @@ medford_board_cfg(
* can result in time-of-check/time-of-use bugs.
*/
if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
goto fail8;
goto fail7;
encp->enc_privilege_mask = mask;
/* Get interrupt vector limits */
if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
if (EFX_PCI_FUNCTION_IS_PF(encp))
goto fail9;
goto fail8;
/* Ignore error (cannot query vector limits from a VF). */
base = 0;
@ -267,14 +253,12 @@ medford_board_cfg(
rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
goto fail10;
goto fail9;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
fail10:
EFSYS_PROBE(fail10);
fail9:
EFSYS_PROBE(fail9);
fail8: