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Use a register to set the cpsr bits. The ip register is safe to be changed

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within all of these functions, and is only stored in some to correctly pad
the stack.

This will be needed to build as Thumb-2 as, unlike with ARM instructions,
the msr instruction only takes a register as the input.
This commit is contained in:
Andrew Turner 2015-05-31 09:07:26 +00:00
parent f826bfc33f
commit 24e8388b29
2 changed files with 12 additions and 8 deletions
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10
lib/libc/arm/aeabi/aeabi_asm_double.S
View File

@ -56,7 +56,7 @@ ENTRY(__aeabi_cdcmple)
cmp r0, #1
bne 1f
/* Yes, clear Z and C */
msr cpsr_c, #(0)
mov ip, #(0)
b 99f
1:
@ -70,14 +70,15 @@ ENTRY(__aeabi_cdcmple)
cmp r0, #1
bne 2f
/* Yes, set Z and C */
msr cpsr_c, #(PCR_Z | PCR_C)
mov ip, #(PCR_Z | PCR_C)
b 99f
2:
/* Not less than or equal, set C and clear Z */
msr cpsr_c, #(PCR_C)
mov ip, #(PCR_C)
99:
msr cpsr_c, ip
pop {r4, r5, r6, r7, ip, pc}
END(__aeabi_cdcmple)
@ -112,6 +113,7 @@ ENTRY(__aeabi_cdcmpeq)
RET
1:
msr cpsr_c, #(PCR_C)
mov ip, #(PCR_C)
msr cpsr_c, ip
RET
END(__aeabi_cdcmpeq)

10
lib/libc/arm/aeabi/aeabi_asm_float.S
View File

@ -54,7 +54,7 @@ ENTRY(__aeabi_cfcmple)
cmp r0, #1
bne 1f
/* Yes, clear Z and C */
msr cpsr_c, #(0)
mov ip, #(0)
b 99f
1:
@ -66,14 +66,15 @@ ENTRY(__aeabi_cfcmple)
cmp r0, #1
bne 2f
/* Yes, set Z and C */
msr cpsr_c, #(PCR_Z | PCR_C)
mov ip, #(PCR_Z | PCR_C)
b 99f
2:
/* Not less than or equal, set C and clear Z */
msr cpsr_c, #(PCR_C)
mov ip, #(PCR_C)
99:
msr cpsr_c, ip
pop {r4, r5, ip, pc}
END(__aeabi_cfcmple)
@ -103,6 +104,7 @@ ENTRY(__aeabi_cfcmpeq)
RET
1:
msreq cpsr_c, #(PCR_C)
mov ip, #(PCR_C)
msr cpsr_c, ip
RET
END(__aeabi_cfcmpeq)