Partial revert of r258779 and r258780:
The directory sys/dev/drm2/i915 is apperently contributed code. Revert to the broken version of this file to make future imports easier. Requested by: kib
This commit is contained in:
Eitan Adler
parent
5f30ec9b63
commit
2526f9d725
@ -798,7 +798,7 @@ __FBSDID("$FreeBSD$");
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#define _DPLL_A 0x06014
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#define _DPLL_B 0x06018
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#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
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#define DPLL_VCO_ENABLE (1U << 31)
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#define DPLL_VCO_ENABLE (1 << 31)
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#define DPLL_DVO_HIGH_SPEED (1 << 30)
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#define DPLL_SYNCLOCK_ENABLE (1 << 29)
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#define DPLL_VGA_MODE_DIS (1 << 28)
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@ -1483,7 +1483,7 @@ __FBSDID("$FreeBSD$");
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/* SDVO port control */
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#define SDVOB 0x61140
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#define SDVOC 0x61160
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#define SDVO_ENABLE (1U << 31)
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#define SDVO_ENABLE (1 << 31)
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#define SDVO_PIPE_B_SELECT (1 << 30)
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#define SDVO_STALL_SELECT (1 << 29)
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#define SDVO_INTERRUPT_ENABLE (1 << 26)
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@ -1521,7 +1521,7 @@ __FBSDID("$FreeBSD$");
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#define DVOA 0x61120
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#define DVOB 0x61140
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#define DVOC 0x61160
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#define DVO_ENABLE (1U << 31)
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#define DVO_ENABLE (1 << 31)
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#define DVO_PIPE_B_SELECT (1 << 30)
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#define DVO_PIPE_STALL_UNUSED (0 << 28)
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#define DVO_PIPE_STALL (1 << 28)
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@ -1557,7 +1557,7 @@ __FBSDID("$FreeBSD$");
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* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
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* the DPLL semantics change when the LVDS is assigned to that pipe.
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*/
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#define LVDS_PORT_EN (1U << 31)
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#define LVDS_PORT_EN (1 << 31)
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/* Selects pipe B for LVDS data. Must be set on pre-965. */
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#define LVDS_PIPEB_SELECT (1 << 30)
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#define LVDS_PIPE_MASK (1 << 30)
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@ -1604,7 +1604,7 @@ __FBSDID("$FreeBSD$");
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/* Video Data Island Packet control */
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#define VIDEO_DIP_DATA 0x61178
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#define VIDEO_DIP_CTL 0x61170
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#define VIDEO_DIP_ENABLE (1U << 31)
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#define VIDEO_DIP_ENABLE (1 << 31)
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#define VIDEO_DIP_PORT_B (1 << 29)
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#define VIDEO_DIP_PORT_C (2 << 29)
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#define VIDEO_DIP_ENABLE_AVI (1 << 21)
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@ -1620,7 +1620,7 @@ __FBSDID("$FreeBSD$");
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/* Panel power sequencing */
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#define PP_STATUS 0x61200
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#define PP_ON (1U << 31)
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#define PP_ON (1 << 31)
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/*
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* Indicates that all dependencies of the panel are on:
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*
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@ -1653,7 +1653,7 @@ __FBSDID("$FreeBSD$");
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/* Panel fitting */
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#define PFIT_CONTROL 0x61230
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#define PFIT_ENABLE (1U << 31)
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#define PFIT_ENABLE (1 << 31)
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#define PFIT_PIPE_MASK (3 << 29)
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#define PFIT_PIPE_SHIFT 29
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#define VERT_INTERP_DISABLE (0 << 10)
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@ -1714,7 +1714,7 @@ __FBSDID("$FreeBSD$");
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/* TV port control */
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#define TV_CTL 0x68000
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/** Enables the TV encoder */
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# define TV_ENC_ENABLE (1U << 31)
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# define TV_ENC_ENABLE (1 << 31)
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/** Sources the TV encoder input from pipe B instead of A. */
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# define TV_ENC_PIPEB_SELECT (1 << 30)
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/** Outputs composite video (DAC A only) */
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@ -1786,7 +1786,7 @@ __FBSDID("$FreeBSD$");
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*
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* This gets cleared when TV_DAC_STATE_EN is cleared
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*/
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# define TVDAC_STATE_CHG (1U << 31)
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# define TVDAC_STATE_CHG (1 << 31)
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# define TVDAC_SENSE_MASK (7 << 28)
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/** Reports that DAC A voltage is above the detect threshold */
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# define TVDAC_A_SENSE (1 << 30)
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@ -1913,7 +1913,7 @@ __FBSDID("$FreeBSD$");
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#define TV_H_CTL_2 0x68034
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/** Enables the colorburst (needed for non-component color) */
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# define TV_BURST_ENA (1U << 31)
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# define TV_BURST_ENA (1 << 31)
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/** Offset of the colorburst from the start of hsync, in pixels minus one. */
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# define TV_HBURST_START_SHIFT 16
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# define TV_HBURST_START_MASK 0x1fff0000
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@ -1958,7 +1958,7 @@ __FBSDID("$FreeBSD$");
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#define TV_V_CTL_3 0x68044
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/** Enables generation of the equalization signal */
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# define TV_EQUAL_ENA (1U << 31)
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# define TV_EQUAL_ENA (1 << 31)
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/** Length of vsync, in half lines */
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# define TV_VEQ_LEN_MASK 0x007f0000
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# define TV_VEQ_LEN_SHIFT 16
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@ -2032,7 +2032,7 @@ __FBSDID("$FreeBSD$");
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#define TV_SC_CTL_1 0x68060
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/** Turns on the first subcarrier phase generation DDA */
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# define TV_SC_DDA1_EN (1U << 31)
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# define TV_SC_DDA1_EN (1 << 31)
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/** Turns on the first subcarrier phase generation DDA */
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# define TV_SC_DDA2_EN (1 << 30)
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/** Turns on the first subcarrier phase generation DDA */
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@ -2095,7 +2095,7 @@ __FBSDID("$FreeBSD$");
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* If set, the rest of the registers are ignored, and the calculated values can
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* be read back from the register.
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*/
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# define TV_AUTO_SCALE (1U << 31)
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# define TV_AUTO_SCALE (1 << 31)
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/**
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* Disables the vertical filter.
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*
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@ -2158,7 +2158,7 @@ __FBSDID("$FreeBSD$");
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# define TV_VSCALE_IP_FRAC_SHIFT 0
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#define TV_CC_CONTROL 0x68090
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# define TV_CC_ENABLE (1U << 31)
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# define TV_CC_ENABLE (1 << 31)
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/**
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* Specifies which field to send the CC data in.
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*
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@ -2174,7 +2174,7 @@ __FBSDID("$FreeBSD$");
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# define TV_CC_LINE_SHIFT 0
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#define TV_CC_DATA 0x68094
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# define TV_CC_RDY (1U << 31)
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# define TV_CC_RDY (1 << 31)
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/** Second word of CC data to be transmitted. */
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# define TV_CC_DATA_2_MASK 0x007f0000
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# define TV_CC_DATA_2_SHIFT 16
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@ -2197,7 +2197,7 @@ __FBSDID("$FreeBSD$");
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#define DP_C 0x64200
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#define DP_D 0x64300
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#define DP_PORT_EN (1U << 31)
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#define DP_PORT_EN (1 << 31)
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#define DP_PIPEB_SELECT (1 << 30)
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#define DP_PIPE_MASK (1 << 30)
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@ -2307,7 +2307,7 @@ __FBSDID("$FreeBSD$");
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#define DPD_AUX_CH_DATA4 0x64320
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#define DPD_AUX_CH_DATA5 0x64324
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#define DP_AUX_CH_CTL_SEND_BUSY (1U << 31)
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#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
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#define DP_AUX_CH_CTL_DONE (1 << 30)
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#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
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#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
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@ -2903,7 +2903,7 @@ __FBSDID("$FreeBSD$");
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/* VBIOS regs */
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#define VGACNTRL 0x71400
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# define VGA_DISP_DISABLE (1U << 31)
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# define VGA_DISP_DISABLE (1 << 31)
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# define VGA_2X_MODE (1 << 30)
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# define VGA_PIPE_B_SELECT (1 << 29)
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@ -3029,7 +3029,7 @@ __FBSDID("$FreeBSD$");
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#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
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/* interrupts */
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#define DE_MASTER_IRQ_CONTROL (1U << 31)
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#define DE_MASTER_IRQ_CONTROL (1 << 31)
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#define DE_SPRITEB_FLIP_DONE (1 << 29)
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#define DE_SPRITEA_FLIP_DONE (1 << 28)
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#define DE_PLANEB_FLIP_DONE (1 << 27)
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@ -3553,7 +3553,7 @@ __FBSDID("$FreeBSD$");
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/* or SDVOB */
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#define HDMIB 0xe1140
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#define PORT_ENABLE (1U << 31)
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#define PORT_ENABLE (1 << 31)
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#define TRANSCODER(pipe) ((pipe) << 30)
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#define TRANSCODER_CPT(pipe) ((pipe) << 29)
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#define TRANSCODER_MASK (1 << 30)
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@ -3583,13 +3583,13 @@ __FBSDID("$FreeBSD$");
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#define LVDS_DETECTED (1 << 1)
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#define BLC_PWM_CPU_CTL2 0x48250
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#define PWM_ENABLE (1U << 31)
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#define PWM_ENABLE (1 << 31)
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#define PWM_PIPE_A (0 << 29)
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#define PWM_PIPE_B (1 << 29)
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#define BLC_PWM_CPU_CTL 0x48254
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#define BLC_PWM_PCH_CTL1 0xc8250
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#define PWM_PCH_ENABLE (1U << 31)
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#define PWM_PCH_ENABLE (1 << 31)
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#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
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#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
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#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
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@ -3611,8 +3611,8 @@ __FBSDID("$FreeBSD$");
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#define PANEL_PORT_SELECT_LVDS (0 << 30)
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#define PANEL_PORT_SELECT_DPA (1 << 30)
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#define EDP_PANEL (1 << 30)
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#define PANEL_PORT_SELECT_DPC (2U << 30)
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#define PANEL_PORT_SELECT_DPD (3U << 30)
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#define PANEL_PORT_SELECT_DPC (2 << 30)
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#define PANEL_PORT_SELECT_DPD (3 << 30)
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#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
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#define PANEL_POWER_UP_DELAY_SHIFT 16
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#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
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