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kernel clean up to make the sun4v kernel build

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Reviewed by: jmg
Approved by: rwatson (mentor)
This commit is contained in:
Kip Macy 2006-10-09 04:45:19 +00:00
parent 0209c79363
commit 25e328499c
14 changed files with 199 additions and 27 deletions
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6
sys/conf/files.sun4v
View File

@ -58,12 +58,6 @@ sparc64/pci/ofw_pcib.c optional pci
sparc64/pci/ofw_pcib_subr.c optional pci
sparc64/pci/ofw_pcibus.c optional pci
sparc64/pci/ofw_pci_if.m optional pci
sparc64/dtrace/dtrace_asm.s optional dtrace
sparc64/dtrace/dtrace_isa.c optional dtrace
sparc64/dtrace/fasttrap_isa.c optional dtrace
sparc64/dtrace/fbt.c optional dtrace
sparc64/dtrace/sdt.c optional dtrace
sparc64/dtrace/dtrace_stub.c standard
# XXX hvcons should be optional
sun4v/sun4v/hvcons.c standard

33
sys/dev/ofw/openfirm.c
View File

@ -814,3 +814,36 @@ OF_chain(void *virt, u_int size,
entry(0, 0, openfirmware, arg, len);
}
#endif
/*
* Extensions added for sun4v support
*
*/
/*
* This interface allows the client to safely take over the %tba by
* the prom's service. The prom will take care of the quiescence of
* interrupts and handle any pending soft interrupts.
* This call also sets the MMU fault status area for the cpu.
*/
void
OF_set_mmfsa_traptable(void *tba_addr, uint64_t mmfsa_ra)
{
static struct {
cell_t name;
cell_t nargs;
cell_t nreturns;
cell_t tba_addr;
cell_t mmfsa_ra;
} args = {
(cell_t)"SUNW,set-trap-table",
2,
0,
};
args.tba_addr = p1275_ptr2cell(tba_addr);
args.mmfsa_ra = p1275_ptr2cell(mmfsa_ra);
openfirmware(&args);
}

26
sys/dev/ofw/openfirm.h
View File

@ -74,6 +74,27 @@ typedef unsigned int phandle_t;
#include <sys/types.h>
#include <sys/malloc.h>
#define p1275_ptr2cell(p) ((cell_t)((uintptr_t)((void *)(p))))
#define p1275_int2cell(i) ((cell_t)((int)(i)))
#define p1275_uint2cell(u) ((cell_t)((unsigned int)(u)))
#define p1275_size2cell(u) ((cell_t)((size_t)(u)))
#define p1275_phandle2cell(ph) ((cell_t)((unsigned int)((phandle_t)(ph))))
#define p1275_dnode2cell(d) ((cell_t)((unsigned int)((pnode_t)(d))))
#define p1275_ihandle2cell(ih) ((cell_t)((unsigned int)((ihandle_t)(ih))))
#define p1275_ull2cell_high(ll) (0LL)
#define p1275_ull2cell_low(ll) ((cell_t)(ll))
#define p1275_uintptr2cell(i) ((cell_t)((uintptr_t)(i)))
#define p1275_cell2ptr(p) ((void *)((cell_t)(p)))
#define p1275_cell2int(i) ((int)((cell_t)(i)))
#define p1275_cell2uint(u) ((unsigned int)((cell_t)(u)))
#define p1275_cell2size(u) ((size_t)((cell_t)(u)))
#define p1275_cell2phandle(ph) ((phandle_t)((cell_t)(ph)))
#define p1275_cell2dnode(d) ((pnode_t)((cell_t)(d)))
#define p1275_cell2ihandle(ih) ((ihandle_t)((cell_t)(ih)))
#define p1275_cells2ull(h, l) ((unsigned long long)(cell_t)(l))
#define p1275_cell2uintptr(i) ((uintptr_t)((cell_t)(i)))
MALLOC_DECLARE(M_OFWPROP);
/*
@ -138,5 +159,10 @@ void OF_set_symbol_lookup(void *, void *);
/* Time function */
int OF_milliseconds(void);
/* sun4v additions */
void OF_set_mmfsa_traptable(void *tba_addr, uint64_t mmfsa_ra);
int OF_translate_virt(vm_offset_t va, int *valid, vm_paddr_t *physaddr, int *mode);
vm_paddr_t OF_vtophys(vm_offset_t va);
#endif /* _KERNEL */
#endif /* _OPENFIRM_H_ */

2
sys/sparc64/include/asi.h
View File

@ -123,7 +123,7 @@
#define ASI_ITLB_DATA_IN_REG 0x54
/* US-III Cu: also ASI_ITLB_CAM_ADDRESS_REG */
#define ASI_ITLB_DATA_ACCESS_REG 0x55
#define ASI_ITLB_TAG_READ_REG 0x56
#define ASI_IMMU_DEMAP 0x57
#define ASI_DMMU_TAG_TARGET_REG 0x58

10
sys/sparc64/pci/ofw_pcibus.c
View File

@ -46,7 +46,9 @@ __FBSDID("$FreeBSD$");
#include <machine/bus.h>
#include <machine/bus_common.h>
#ifndef SUN4V
#include <machine/cache.h>
#endif
#include <machine/iommureg.h>
#include <machine/resource.h>
@ -123,8 +125,10 @@ ofw_pcibus_probe(device_t dev)
static void
ofw_pcibus_setup_device(device_t bridge, u_int busno, u_int slot, u_int func)
{
u_int lat, clnsz;
u_int lat;
#ifndef SUN4V
u_int clnsz;
#endif
/*
* Initialize the latency timer register for busmaster devices to work
* properly. This is another task which the firmware does not always
@ -146,6 +150,7 @@ ofw_pcibus_setup_device(device_t bridge, u_int busno, u_int slot, u_int func)
PCIR_LATTIMER, min(lat, 255), 1);
}
#ifndef SUN4V
/*
* Compute a value to write into the cache line size register.
* The role of the streaming cache is unclear in write invalidate
@ -158,6 +163,7 @@ ofw_pcibus_setup_device(device_t bridge, u_int busno, u_int slot, u_int func)
PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ,
clnsz / 4, 1);
#endif
/*
* The preset in the intline register is usually wrong. Reset it to 255,
* so that the PCI code will reroute the interrupt if needed.

90
sys/sparc64/sparc64/genassym.c
View File

@ -71,9 +71,13 @@ __FBSDID("$FreeBSD$");
#include <machine/tsb.h>
#include <machine/tstate.h>
#include <machine/utrap.h>
#ifdef SUN4V
#include <machine/mmu.h>
#include <machine/tte_hash.h>
#endif
ASSYM(KERNBASE, KERNBASE);
ASSYM(VM_MIN_PROM_ADDRESS, VM_MIN_PROM_ADDRESS);
ASSYM(EFAULT, EFAULT);
ASSYM(ENAMETOOLONG, ENAMETOOLONG);
@ -99,29 +103,34 @@ ASSYM(TLB_DEMAP_NUCLEUS, TLB_DEMAP_NUCLEUS);
ASSYM(TLB_DEMAP_PRIMARY, TLB_DEMAP_PRIMARY);
ASSYM(TLB_DEMAP_CONTEXT, TLB_DEMAP_CONTEXT);
ASSYM(TLB_DEMAP_PAGE, TLB_DEMAP_PAGE);
ASSYM(TLB_DIRECT_TO_TTE_MASK, TLB_DIRECT_TO_TTE_MASK);
#ifndef SUN4V
ASSYM(TSB_BUCKET_MASK, TSB_BUCKET_MASK);
ASSYM(TSB_BUCKET_SHIFT, TSB_BUCKET_SHIFT);
#endif
ASSYM(INT_SHIFT, INT_SHIFT);
ASSYM(PTR_SHIFT, PTR_SHIFT);
ASSYM(PAGE_SHIFT, PAGE_SHIFT);
ASSYM(PAGE_MASK, PAGE_MASK);
ASSYM(PAGE_MASK_4M, PAGE_MASK_4M);
ASSYM(PAGE_SHIFT_8K, PAGE_SHIFT_8K);
ASSYM(PAGE_SHIFT_4M, PAGE_SHIFT_4M);
ASSYM(PAGE_SIZE, PAGE_SIZE);
ASSYM(PAGE_SIZE_4M, PAGE_SIZE_4M);
ASSYM(CPU_CLKSYNC, CPU_CLKSYNC);
ASSYM(CPU_INIT, CPU_INIT);
ASSYM(CSA_MID, offsetof(struct cpu_start_args, csa_mid));
ASSYM(CSA_PCPU, offsetof(struct cpu_start_args, csa_pcpu));
ASSYM(CSA_STATE, offsetof(struct cpu_start_args, csa_state));
ASSYM(CSA_CPUID, offsetof(struct cpu_start_args, csa_cpuid));
#ifndef SUN4V
ASSYM(CSA_TICK, offsetof(struct cpu_start_args, csa_tick));
ASSYM(CSA_VER, offsetof(struct cpu_start_args, csa_ver));
ASSYM(CSA_MID, offsetof(struct cpu_start_args, csa_mid));
ASSYM(CSA_TTES, offsetof(struct cpu_start_args, csa_ttes));
#endif
ASSYM(DC_TAG_SHIFT, DC_TAG_SHIFT);
ASSYM(DC_TAG_MASK, DC_TAG_MASK);
ASSYM(DC_VALID_SHIFT, DC_VALID_SHIFT);
@ -151,9 +160,10 @@ ASSYM(KTR_PARM4, offsetof(struct ktr_entry, ktr_parms[3]));
ASSYM(KTR_PARM5, offsetof(struct ktr_entry, ktr_parms[4]));
ASSYM(KTR_PARM6, offsetof(struct ktr_entry, ktr_parms[5]));
ASSYM(TTE_SHIFT, TTE_SHIFT);
#ifndef SUN4V
ASSYM(TTE_VPN, offsetof(struct tte, tte_vpn));
ASSYM(TTE_DATA, offsetof(struct tte, tte_data));
ASSYM(TTE_SHIFT, TTE_SHIFT);
ASSYM(TD_EXEC, TD_EXEC);
ASSYM(TD_REF, TD_REF);
@ -167,25 +177,68 @@ ASSYM(TD_W, TD_W);
ASSYM(TS_MIN, TS_MIN);
ASSYM(TS_MAX, TS_MAX);
ASSYM(TLB_DIRECT_TO_TTE_MASK, TLB_DIRECT_TO_TTE_MASK);
ASSYM(TV_SIZE_BITS, TV_SIZE_BITS);
#else
ASSYM(VTD_REF, VTD_REF);
ASSYM(VTD_W, VTD_W);
ASSYM(VTD_SW_W, VTD_SW_W);
ASSYM(VTD_LOCK, VTD_LOCK);
ASSYM(THE_SHIFT, THE_SHIFT);
ASSYM(TH_COLLISION_SHIFT, TH_COLLISION_SHIFT);
ASSYM(HVTSB_PA, offsetof(struct hv_tsb_info, hvtsb_pa));
ASSYM(PM_HASHSCRATCH, offsetof(struct pmap, pm_hashscratch));
ASSYM(PM_TSBSCRATCH, offsetof(struct pmap, pm_tsbscratch));
ASSYM(PM_TSB_RA, offsetof(struct pmap, pm_tsb_ra));
ASSYM(PM_TLBACTIVE, offsetof(struct pmap, pm_tlbactive));
ASSYM(HASH_ENTRY_SHIFT, HASH_ENTRY_SHIFT);
#endif
ASSYM(V_INTR, offsetof(struct vmmeter, v_intr));
ASSYM(PC_CURTHREAD, offsetof(struct pcpu, pc_curthread));
ASSYM(PC_CALLER, offsetof(struct pcpu, pc_caller));
ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb));
ASSYM(PC_CPUID, offsetof(struct pcpu, pc_cpuid));
ASSYM(PC_CPUMASK, offsetof(struct pcpu, pc_cpumask));
ASSYM(PC_IRHEAD, offsetof(struct pcpu, pc_irhead));
ASSYM(PC_IRTAIL, offsetof(struct pcpu, pc_irtail));
ASSYM(PC_IRFREE, offsetof(struct pcpu, pc_irfree));
ASSYM(PC_CNT, offsetof(struct pcpu, pc_cnt));
ASSYM(PC_SIZEOF, sizeof(struct pcpu));
#ifdef SUN4V
ASSYM(PC_CPU_Q_RA, offsetof(struct pcpu, pc_cpu_q_ra));
ASSYM(PC_CPU_Q_SIZE, offsetof(struct pcpu, pc_cpu_q_size));
ASSYM(PC_DEV_Q_RA, offsetof(struct pcpu, pc_dev_q_ra));
ASSYM(PC_DEV_Q_SIZE, offsetof(struct pcpu, pc_dev_q_size));
ASSYM(PC_RQ_BASE, offsetof(struct pcpu, pc_rq_ra));
ASSYM(PC_RQ_SIZE, offsetof(struct pcpu, pc_rq_size));
ASSYM(PC_NRQ_BASE, offsetof(struct pcpu, pc_nrq_ra));
ASSYM(PC_NRQ_SIZE, offsetof(struct pcpu, pc_nrq_size));
ASSYM(PC_MONDO_DATA, offsetof(struct pcpu, pc_mondo_data));
ASSYM(PC_MONDO_DATA_RA, offsetof(struct pcpu, pc_mondo_data_ra));
ASSYM(PC_KWBUF_FULL, offsetof(struct pcpu, pc_kwbuf_full));
ASSYM(PC_KWBUF_SP, offsetof(struct pcpu, pc_kwbuf_sp));
ASSYM(PC_KWBUF, offsetof(struct pcpu, pc_kwbuf));
ASSYM(PC_PAD, offsetof(struct pcpu, pad));
ASSYM(PC_PMAP, offsetof(struct pcpu, pc_curpmap));
ASSYM(PC_TSBWBUF, offsetof(struct pcpu, pc_tsbwbuf));
ASSYM(PCB_KSTACK, offsetof(struct pcb, pcb_kstack));
ASSYM(INTR_REPORT_SIZE, INTR_REPORT_SIZE);
#else
ASSYM(PC_MID, offsetof(struct pcpu, pc_mid));
ASSYM(PC_TLB_CTX, offsetof(struct pcpu, pc_tlb_ctx));
ASSYM(PC_TLB_CTX_MAX, offsetof(struct pcpu, pc_tlb_ctx_max));
ASSYM(PC_TLB_CTX_MIN, offsetof(struct pcpu, pc_tlb_ctx_min));
ASSYM(PC_PMAP, offsetof(struct pcpu, pc_pmap));
ASSYM(PC_CNT, offsetof(struct pcpu, pc_cnt));
ASSYM(PC_SIZEOF, sizeof(struct pcpu));
#endif
ASSYM(IH_SHIFT, IH_SHIFT);
@ -232,6 +285,9 @@ ASSYM(TD_FRAME, offsetof(struct thread, td_frame));
ASSYM(TD_KSTACK, offsetof(struct thread, td_kstack));
ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
ASSYM(TD_PROC, offsetof(struct thread, td_proc));
ASSYM(TD_MD, offsetof(struct thread, td_md));
ASSYM(MD_SAVED_PIL, offsetof(struct mdthread, md_saved_pil));
ASSYM(PCB_SIZEOF, sizeof(struct pcb));
ASSYM(PCB_RW, offsetof(struct pcb, pcb_rw));
@ -242,6 +298,10 @@ ASSYM(PCB_FLAGS, offsetof(struct pcb, pcb_flags));
ASSYM(PCB_NSAVED, offsetof(struct pcb, pcb_nsaved));
ASSYM(PCB_PC, offsetof(struct pcb, pcb_pc));
ASSYM(PCB_SP, offsetof(struct pcb, pcb_sp));
ASSYM(PCB_FEF, PCB_FEF);
ASSYM(VM_PMAP, offsetof(struct vmspace, vm_pmap));
@ -276,17 +336,27 @@ ASSYM(TF_O7, offsetof(struct trapframe, tf_out[7]));
ASSYM(TF_FPRS, offsetof(struct trapframe, tf_fprs));
ASSYM(TF_FSR, offsetof(struct trapframe, tf_fsr));
ASSYM(TF_GSR, offsetof(struct trapframe, tf_gsr));
ASSYM(TF_LEVEL, offsetof(struct trapframe, tf_level));
ASSYM(TF_PIL, offsetof(struct trapframe, tf_pil));
#ifndef SUN4V
ASSYM(TF_LEVEL, offsetof(struct trapframe, tf_level));
ASSYM(TF_SFAR, offsetof(struct trapframe, tf_sfar));
ASSYM(TF_SFSR, offsetof(struct trapframe, tf_sfsr));
ASSYM(TF_TAR, offsetof(struct trapframe, tf_tar));
#else
ASSYM(TF_ASI, offsetof(struct trapframe, tf_asi));
#endif
ASSYM(TF_TNPC, offsetof(struct trapframe, tf_tnpc));
ASSYM(TF_TPC, offsetof(struct trapframe, tf_tpc));
ASSYM(TF_TSTATE, offsetof(struct trapframe, tf_tstate));
#if 0
ASSYM(TF_TYPE, offsetof(struct trapframe, tf_type));
ASSYM(TF_Y, offsetof(struct trapframe, tf_y));
#endif
ASSYM(TF_WSTATE, offsetof(struct trapframe, tf_wstate));
ASSYM(TF_SIZEOF, sizeof(struct trapframe));
ASSYM(UT_MAX, UT_MAX);
ASSYM(VM_MIN_DIRECT_ADDRESS, VM_MIN_DIRECT_ADDRESS);
ASSYM(VM_MIN_PROM_ADDRESS, VM_MIN_PROM_ADDRESS);
ASSYM(VM_MAX_PROM_ADDRESS, VM_MAX_PROM_ADDRESS);

7
sys/sun4v/conf/GENERIC
View File

@ -211,6 +211,9 @@ device ums # Mouse
#options DEBUG_VFS_LOCKS
device ccd
options SPIN_PROFILING
# sched_lock incurs a rather high overhead at a 1000Hz with 32 cpus
# on most arches and in most cases 1000Hz pessimizes performance
# its choice was not adequately researched
options HZ=100
#device vnet

15
sys/sun4v/include/asi.h
View File

@ -151,5 +151,20 @@
#define Q(queue_head) (queue_head >> 4)
/*
* sparc64 compat for the loader
*/
#define AA_IMMU_TAR 0x30
#define AA_DMMU_TAR 0x30
#define ASI_UPA_CONFIG_REG 0x4a /* US-I, II */
#define ASI_IMMU 0x50
#define ASI_ITLB_DATA_IN_REG 0x54
#define ASI_ITLB_DATA_ACCESS_REG 0x55
#define ASI_ITLB_TAG_READ_REG 0x56
#define ASI_DMMU 0x58
#define ASI_DTLB_DATA_IN_REG 0x5c
#define ASI_DTLB_DATA_ACCESS_REG 0x5d
#define ASI_DTLB_TAG_READ_REG 0x5e
#endif /* !_MACHINE_ASI_H_ */

11
sys/sun4v/include/tte.h
View File

@ -125,6 +125,17 @@ struct pmap;
#define VTD_32M TTE32M
#define VTD_256M TTE256M
/*
* sparc64 compatibility for the loader
*/
#define TD_SIZE_SHIFT (61)
#define TS_4M (3UL)
#define TD_V (1UL << 63)
#define TD_4M (TS_4M << TD_SIZE_SHIFT)
/*
* default flags for kernel pages
*/

19
sys/sun4v/sun4v/exception.S
View File

@ -41,7 +41,6 @@ __FBSDID("$FreeBSD$")
#include <machine/tstate.h>
#include <machine/wstate.h>
#include <machine/hypervisorvar.h>
#include <machine/errata.h>
#include "assym.s"
#include <machine/mmu.h>
@ -694,6 +693,7 @@ tick_ ## tl ## _entry: \
.align 32
.endm
#ifdef KDTRACE
.macro dtrace_fasttrap
sethi %hi(dtrace_fasttrap_probe_ptr), %g4
ldx [%g4 + %lo(dtrace_fasttrap_probe_ptr)], %g4
@ -716,7 +716,22 @@ tick_ ## tl ## _entry: \
sub %g0, 1, %g4
.align 32
.endm
#else
.macro dtrace_fasttrap
nop
.align 32
.endm
.macro dtrace_pid
nop
.align 32
.endm
.macro dtrace_return
nop
.align 32
.endm
#endif
.macro tl0_fp_restore
GET_PCB(PCB_REG) ! 3 instructions
ldx [%g6 + PCB_FLAGS], %g1

2
sys/sun4v/sun4v/machdep.c
View File

@ -376,7 +376,7 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
* Initialize proc0 stuff (p_contested needs to be done early).
*/
proc_linkup(&proc0, &thread0);
proc_linkup(&proc0, &ksegrp0, &thread0);
proc0.p_md.md_sigtramp = NULL;
proc0.p_md.md_utrap = NULL;
frame0.tf_tstate = TSTATE_IE | TSTATE_PEF | TSTATE_PRIV;

1
sys/sun4v/sun4v/t1_copy.S
View File

@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$")
#include <machine/tstate.h>
#include <machine/wstate.h>
#include <machine/hypervisorvar.h>
#include <machine/errata.h>
.register %g2,#ignore
.register %g3,#ignore

2
sys/sun4v/sun4v/tsb.c
View File

@ -120,8 +120,8 @@ tsb_deinit(hv_tsb_info_t *hvtsb)
for (i = 0, tm = m; i < TSB_SIZE; i++, m++) {
tm->wire_count--;
atomic_subtract_int(&cnt.v_wire_count, 1);
vm_page_free(tm);
}
vm_page_release_contig(m, TSB_SIZE);
}

2
sys/sun4v/sun4v/vnex.c
View File

@ -26,9 +26,9 @@
*
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/cdefs.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>