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Some code cleanup:

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- Fix some comments; remove numerous superfluous or outdated ones.
- Correctly pass on the requesting device when handing requests up
  to the parent bus.
- Use the complete device name, including unit number, to build the
  IOMMU instance name.
- Inline a function that was only used once, and was trivial.
This commit is contained in:
Thomas Moestl 2004-04-25 00:30:28 +00:00
parent 1822d00dc3
commit 2699b91e48
3 changed files with 28 additions and 128 deletions
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87
sys/sparc64/pci/psycho.c
View File

@ -74,7 +74,6 @@
#include "pcib_if.h"
static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *);
static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t,
int, driver_intr_t);
static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *,
@ -201,8 +200,8 @@ struct psycho_strayclr {
* the IIi. The APB let's the IIi handle two independednt PCI buses, and
* appears as two "simba"'s underneath the sabre.
*
* "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus
* and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while
* "psycho" and "psycho+" are dual UPA to PCI bridges. They sit on the UPA bus
* and manage two PCI buses. "psycho" has two 64-bit 33MHz buses, while
* "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
* will usually find a "psycho+" since I don't think the original "psycho"
* ever shipped, and if it did it would be in the U30.
@ -218,17 +217,6 @@ struct psycho_strayclr {
*
* On UltraII machines, there can be any number of "psycho+" ICs, each
* providing two PCI buses.
*
*
* XXXX The psycho/sabre node has an `interrupts' attribute. They contain
* the values of the following interrupts in this order:
*
* PCI Bus Error (30)
* DMA UE (2e)
* DMA CE (2f)
* Power Fail (25)
*
* We really should attach handlers for each.
*/
#ifdef DEBUGGER_ON_POWERFAIL
#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST
@ -302,18 +290,6 @@ psycho_probe(device_t dev)
return (ENXIO);
}
/*
* SUNW,psycho initialisation ..
* - find the per-psycho registers
* - figure out the IGN.
* - find our partner psycho
* - configure ourselves
* - bus range, bus,
* - interrupt map,
* - setup the chipsets.
* - if we're the first of the pair, initialise the IOMMU, otherwise
* just copy it's tags and addresses.
*/
static int
psycho_attach(device_t dev)
{
@ -349,11 +325,10 @@ psycho_attach(device_t dev)
* (0) per-PBM configuration and status registers
* (1) per-PBM PCI configuration space, containing only the
* PBM 256-byte PCI header
* (2) the shared psycho configuration registers (struct psychoreg)
* (2) the shared psycho configuration registers
*/
reg = nexus_get_reg(dev);
nreg = nexus_get_nreg(dev);
/* Register layouts are different. stuupid. */
if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
if (nreg <= 2)
panic("psycho_attach: %d not enough registers", nreg);
@ -421,9 +396,7 @@ psycho_attach(device_t dev)
desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr),
(int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half);
/*
* Setup the PCI control register
*/
/* Setup the PCI control register. */
csr = PCICTL_READ8(sc, PCR_CS);
csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE;
csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO |
@ -431,9 +404,7 @@ psycho_attach(device_t dev)
PCICTL_WRITE8(sc, PCR_CS, csr);
if (sc->sc_mode == PSYCHO_MODE_SABRE) {
/*
* Use the PROM preset for now.
*/
/* Use the PROM preset for now. */
csr = PCICTL_READ8(sc, PCR_TAS);
if (csr == 0)
panic("psycho_attach: sabre TAS not initialized.");
@ -441,9 +412,6 @@ psycho_attach(device_t dev)
} else
sc->sc_dvmabase = -1;
/* Grab the psycho ranges */
psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange);
/* Initialize memory and i/o rmans */
sc->sc_io_rman.rm_type = RMAN_ARRAY;
sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports";
@ -455,6 +423,11 @@ psycho_attach(device_t dev)
if (rman_init(&sc->sc_mem_rman) != 0 ||
rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
panic("psycho_probe: failed to set up memory rman");
sc->sc_nrange = OF_getprop_alloc(sc->sc_node, "ranges",
sizeof(*sc->sc_range), (void **)&sc->sc_range);
if (sc->sc_nrange == -1)
panic("could not get psycho ranges");
/*
* Find the addresses of the various bus spaces.
* There should not be multiple ones of one kind.
@ -599,7 +572,7 @@ psycho_attach(device_t dev)
sc->sc_secbus = sc->sc_subbus = ofw_pci_alloc_busno(sc->sc_node);
/*
* Program the bus range registers.
* NOTE: the psycho, the second write changes the bus number the
* NOTE: for the psycho, the second write changes the bus number the
* psycho itself uses for it's configuration space, so these
* writes must be kept in this order!
* The sabre always uses bus 0, but there only can be one sabre per
@ -705,16 +678,6 @@ psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr,
return (found);
}
/* grovel the OBP for various psycho properties */
static void
psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np)
{
*np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp);
if (*np == -1)
panic("could not get psycho ranges");
}
/*
* Interrupt handlers.
*/
@ -734,7 +697,6 @@ psycho_ue(void *arg)
*/
if ((afsr & UEAFSR_P_DTE) != 0)
iommu_decode_fault(sc->sc_is, afar);
/* It's uncorrectable. Dump the regs and panic. */
panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr);
}
@ -747,7 +709,6 @@ psycho_ce(void *arg)
afar = PSYCHO_READ8(sc, PSR_CE_AFA);
afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
/* It's correctable. Dump the regs and continue. */
device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
"AFSR %#lx\n", (u_long)afar, (u_long)afsr);
/* Clear the error bits that we caught. */
@ -763,7 +724,6 @@ psycho_bus_a(void *arg)
afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA);
afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS);
/* It's uncorrectable. Dump the regs and panic. */
panic("%s: PCI bus A error AFAR %#lx AFSR %#lx",
device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr);
}
@ -776,7 +736,6 @@ psycho_bus_b(void *arg)
afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA);
afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS);
/* It's uncorrectable. Dump the regs and panic. */
panic("%s: PCI bus B error AFAR %#lx AFSR %#lx",
device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr);
}
@ -785,7 +744,6 @@ static void
psycho_powerfail(void *arg)
{
/* We lost power. Try to shut down NOW. */
#ifdef DEBUGGER_ON_POWERFAIL
struct psycho_softc *sc = (struct psycho_softc *)arg;
@ -809,7 +767,6 @@ psycho_wakeup(void *arg)
}
#endif /* PSYCHO_MAP_WAKEUP */
/* initialise the IOMMU... */
void
psycho_iommu_init(struct psycho_softc *sc, int tsbsize)
{
@ -830,7 +787,7 @@ psycho_iommu_init(struct psycho_softc *sc, int tsbsize)
name = (char *)malloc(32, M_DEVBUF, M_NOWAIT);
if (name == 0)
panic("couldn't malloc iommu name");
snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev));
snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev));
iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0);
}
@ -998,7 +955,7 @@ psycho_route_interrupt(device_t bridge, device_t dev, int pin)
/*
* If this is outside of the range for an intpin, it's likely a full
* INO, and no mapping is required at all; this happens on the u30,
* where there's no interrupt map at the psycho node. Fortunately,
* where there's no interrupt map at the psycho node. Fortunately,
* there seem to be no INOs in the intpin range on this boxen, so
* this easy heuristics will do.
*/
@ -1085,7 +1042,7 @@ psycho_setup_intr(device_t dev, device_t child,
* interrupt vector.
*
* XXX We only compare INOs rather than IGNs since the firmware may
* not provide the IGN and the IGN is constant for all device on that
* not provide the IGN and the IGN is constant for all devices on that
* PCI controller. This could cause problems for the FFB/external
* interrupt which has a full vector that can be set arbitrarily.
*/
@ -1174,8 +1131,8 @@ psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
if (start != end)
panic("psycho_alloc_resource: XXX: interrupt range");
start = end |= sc->sc_ign;
return (bus_alloc_resource(bus, type, rid, start, end,
count, flags));
return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
rid, start, end, count, flags));
}
switch (type) {
case SYS_RES_MEMORY:
@ -1218,7 +1175,8 @@ psycho_activate_resource(device_t bus, device_t child, int type, int rid,
int error;
if (type == SYS_RES_IRQ)
return (bus_activate_resource(bus, type, rid, r));
return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
type, rid, r));
if (type == SYS_RES_MEMORY) {
/*
* Need to memory-map the device space, as some drivers depend
@ -1239,7 +1197,8 @@ psycho_deactivate_resource(device_t bus, device_t child, int type, int rid,
{
if (type == SYS_RES_IRQ)
return (bus_deactivate_resource(bus, type, rid, r));
return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
type, rid, r));
if (type == SYS_RES_MEMORY) {
sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
rman_set_virtual(r, NULL);
@ -1254,7 +1213,8 @@ psycho_release_resource(device_t bus, device_t child, int type, int rid,
int error;
if (type == SYS_RES_IRQ)
return (bus_release_resource(bus, type, rid, r));
return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
type, rid, r));
if (rman_get_flags(r) & RF_ACTIVE) {
error = bus_deactivate_resource(child, type, rid, r);
if (error)
@ -1353,9 +1313,6 @@ psycho_adjust_busrange(device_t dev, u_int subbus)
}
#endif
/*
* below here is bus space and bus dma support
*/
static bus_space_tag_t
psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
{

50
sys/sparc64/pci/psychoreg.h
View File

@ -46,7 +46,7 @@
*/
/*
* psycho register offset.s
* psycho register offsets.
*
* NB: FFB0 and FFB1 intr map regs also appear at 0x6000 and 0x8000
* respectively.
@ -266,52 +266,4 @@
#define PCSR_SECBUS 0x40 /* Secondary bus number register */
#define PCSR_SUBBUS 0x41 /* Subordinate bus number register */
/*
* these are the PROM structures we grovel
*/
/*
* For the physical adddresses split into 3 32 bit values, we deocde
* them like the following (IEEE1275 PCI Bus binding 2.0, 2.2.1.1
* Numerical Representation):
*
* phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
* phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
* phys.lo cell: llllllll llllllll llllllll llllllll
*
* where these bits affect the address' properties:
* n not-relocatable
* p prefetchable
* t aliased (non-relocatable IO), below 1MB (memory) or
* below 64KB (reloc. IO)
* ss address space code:
* 00 - configuration space
* 01 - I/O space
* 10 - 32 bit memory space
* 11 - 64 bit memory space
* bb..bb 8 bit bus number
* ddddd 5 bit device number
* fff 3 bit function number
* rr..rr 8 bit register number
* hh..hh 32 bit unsigned value
* ll..ll 32 bit unsigned value
* the values of hh..hh and ll..ll are combined to form a larger number.
*
* For config space, we don't have to do much special. For I/O space,
* hh..hh must be zero, and if n == 0 ll..ll is the offset from the
* start of I/O space, otherwise ll..ll is the I/O space. For memory
* space, hh..hh must be zero for the 32 bit space, and is the high 32
* bits in 64 bit space, with ll..ll being the low 32 bits in both cases,
* with offset handling being driver via `n == 0' as for I/O space.
*/
/* commonly used */
#define TAG2BUS(tag) ((tag) >> 16) & 0xff;
#define TAG2DEV(tag) ((tag) >> 11) & 0x1f;
#define TAG2FN(tag) ((tag) >> 8) & 0x7;
#define INTPCI_MAXOBINO 0x16 /* maximum OBIO INO value for PCI */
#define INTPCIOBINOX(x) ((x) & 0x1f) /* OBIO ino index (for PCI machines) */
#define INTPCIINOX(x) (((x) & 0x1c) >> 2) /* PCI ino index */
#endif /* _SPARC64_PCI_PSYCHOREG_H_ */

19
sys/sparc64/pci/psychovar.h
View File

@ -34,21 +34,17 @@
#define _SPARC64_PCI_PSYCHOVAR_H_
/*
* per-PCI bus on mainbus softc structure; one for sabre, or two
* per pair of psycho's.
* Per-PCI bus on mainbus softc structure; one for sabre, or two
* per pair of psychos.
*/
struct psycho_softc {
device_t sc_dev;
/*
* PSYCHO register. we record the base physical address of these
* also as it is the base of the entire PSYCHO
*/
vm_paddr_t sc_basepaddr;
/* Interrupt Group Number for this device */
int sc_ign;
/* our tags (from parent) */
/* Our tags (from parent). */
bus_space_tag_t sc_bustag;
bus_space_handle_t sc_bushandle;
bus_dma_tag_t sc_dmatag;
@ -56,7 +52,7 @@ struct psycho_softc {
bus_addr_t sc_pcictl;
int sc_clockfreq;
phandle_t sc_node; /* prom node */
phandle_t sc_node; /* Firmware node. */
int sc_mode;
#define PSYCHO_MODE_SABRE 1
#define PSYCHO_MODE_PSYCHO 2
@ -75,15 +71,10 @@ struct psycho_softc {
struct ofw_bus_iinfo sc_iinfo;
#endif
/*
* note that the sabre really only has one ranges property,
* used for both simba a and simba b (but the ranges for
* real psychos are the same for PCI A and PCI B anyway).
*/
struct upa_ranges *sc_range;
int sc_nrange;
/* our tags */
/* Tags for PCI access. */
bus_space_tag_t sc_cfgt;
bus_space_tag_t sc_memt;
bus_space_tag_t sc_iot;