Atomic operation acquire barriers also need to be isync on 64-bit systems.
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@ -52,7 +52,7 @@
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#define rmb() __asm __volatile("lwsync" : : : "memory")
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#define wmb() __asm __volatile("lwsync" : : : "memory")
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#define __ATOMIC_REL() __asm __volatile("lwsync" : : : "memory")
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#define __ATOMIC_ACQ() __asm __volatile("lwsync" : : : "memory")
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#define __ATOMIC_ACQ() __asm __volatile("isync" : : : "memory")
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#else
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#define mb() __asm __volatile("sync" : : : "memory")
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#define rmb() __asm __volatile("sync" : : : "memory")
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