Drop CACHE_LINE_SIZE to 64 bytes on x86
The actual cache line size has always been 64 bytes. The 128 number arose as an optimization for Core 2 era Intel processors. By default (configurable in BIOS), these CPUs would prefetch adjacent cache lines unintelligently. Newer CPUs prefetch more intelligently. The latest Core 2 era CPU was introduced in September 2008 (Xeon 7400 series, "Dunnington"). If you are still using one of these CPUs, especially in a multi-socket configuration, consider locating the "adjacent cache line prefetch" option in BIOS and disabling it. Reported by: mjg Reviewed by: np Discussed with: jhb Sponsored by: Dell EMC Isilon
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@ -89,7 +89,7 @@
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* CACHE_LINE_SIZE is the compile-time maximum cache line size for an
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* architecture. It should be used with appropriate caution.
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*/
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#define CACHE_LINE_SHIFT 7
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#define CACHE_LINE_SHIFT 6
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#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
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/* Size of the level 1 page table units */
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@ -82,7 +82,7 @@
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* CACHE_LINE_SIZE is the compile-time maximum cache line size for an
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* architecture. It should be used with appropriate caution.
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*/
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#define CACHE_LINE_SHIFT 7
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#define CACHE_LINE_SHIFT 6
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#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
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#define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
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@ -58,7 +58,7 @@
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* in the range 5 to 9.
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*/
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#undef __FreeBSD_version
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#define __FreeBSD_version 1200042 /* Master, propagated to newvers */
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#define __FreeBSD_version 1200043 /* Master, propagated to newvers */
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/*
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* __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD,
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