From 289f40c67b7239b8cd16b278ff5fef126483b75e Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Thu, 11 Sep 2008 18:33:57 +0000 Subject: [PATCH] Update the comments above the 0xcf9 register reset attempt to match the code. We only attempt a single reset using this method (a "hard" reset), and we use two writes to ensure there is a 0 -> 1 transition in bit 2 to force a reset. MFC after: 1 week --- sys/amd64/amd64/vm_machdep.c | 11 +++++++---- sys/i386/i386/vm_machdep.c | 11 +++++++---- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/sys/amd64/amd64/vm_machdep.c b/sys/amd64/amd64/vm_machdep.c index c181d42b9547..adddc1ca543c 100644 --- a/sys/amd64/amd64/vm_machdep.c +++ b/sys/amd64/amd64/vm_machdep.c @@ -466,10 +466,13 @@ cpu_reset_real() /* * Attempt to force a reset via the Reset Control register at - * I/O port 0xcf9. Bit 2 forces a system reset when it is - * written as 1. Bit 1 selects the type of reset to attempt: - * 0 selects a "soft" reset, and 1 selects a "hard" reset. We - * try to do a "soft" reset first, and then a "hard" reset. + * I/O port 0xcf9. Bit 2 forces a system reset when it + * transitions from 0 to 1. Bit 1 selects the type of reset + * to attempt: 0 selects a "soft" reset, and 1 selects a + * "hard" reset. We try a "hard" reset. The first write sets + * bit 1 to select a "hard" reset and clears bit 2. The + * second write forces a 0 -> 1 transition in bit 2 to trigger + * a reset. */ outb(0xcf9, 0x2); outb(0xcf9, 0x6); diff --git a/sys/i386/i386/vm_machdep.c b/sys/i386/i386/vm_machdep.c index 81e63749004a..71a995263d49 100644 --- a/sys/i386/i386/vm_machdep.c +++ b/sys/i386/i386/vm_machdep.c @@ -643,10 +643,13 @@ cpu_reset_real() /* * Attempt to force a reset via the Reset Control register at - * I/O port 0xcf9. Bit 2 forces a system reset when it is - * written as 1. Bit 1 selects the type of reset to attempt: - * 0 selects a "soft" reset, and 1 selects a "hard" reset. We - * try to do a "soft" reset first, and then a "hard" reset. + * I/O port 0xcf9. Bit 2 forces a system reset when it + * transitions from 0 to 1. Bit 1 selects the type of reset + * to attempt: 0 selects a "soft" reset, and 1 selects a + * "hard" reset. We try a "hard" reset. The first write sets + * bit 1 to select a "hard" reset and clears bit 2. The + * second write forces a 0 -> 1 transition in bit 2 to trigger + * a reset. */ outb(0xcf9, 0x2); outb(0xcf9, 0x6);