diff --git a/share/man/man4/urtwn.4 b/share/man/man4/urtwn.4
index d401a872a66d..ec1b612c9771 100644
--- a/share/man/man4/urtwn.4
+++ b/share/man/man4/urtwn.4
@@ -14,12 +14,12 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd October 31, 2013
+.Dd April 25, 2014
 .Dt URTWN 4
 .Os
 .Sh NAME
 .Nm urtwn
-.Nd Realtek RTL8188CU/RTL8192CU USB IEEE 802.11b/g/n wireless network device
+.Nd Realtek RTL8188CU/RTL8188EU/RTL8192CU USB IEEE 802.11b/g/n wireless network device
 .Sh SYNOPSIS
 To compile this driver into the kernel,
 place the following lines in your
@@ -50,11 +50,11 @@ legal.realtek.license_ack=1
 The
 .Nm
 driver supports USB 2.0 wireless network devices based on Realtek
-RTL8188CUS, RTL8188CE-VAU, RTL8188RU and RTL8192CU chipsets.
+RTL8188CUS, RTL8188CE-VAU, RTL8188EUS, RTL8188RU and RTL8192CU chipsets.
 .Pp
-The RTL8188CUS is a highly integrated 802.11n adapter that combines
-a MAC, a 1T1R capable baseband and an RF in a single chip.
-It operates in the 2GHz spectrum only.
+The RTL8188CUS and RTL8188EUS are highly integrated 802.11n adapter that
+combine a MAC, a 1T1R capable baseband and an RF in a single chip.
+They operate in the 2GHz spectrum only.
 The RTL8188RU is a high-power variant of the RTL8188CUS.
 The RTL8188CE-VAU is a PCI Express Mini Card adapter that attaches
 to the USB interface.
@@ -90,6 +90,8 @@ The following adapters should work:
 .It Netgear WNA1000M
 .It Realtek RTL8192CU
 .It Realtek RTL8188CUS
+.It TP-LINK TL-WN723N v3
+.It TP-LINK TL-WN725N v2
 .El
 .Sh EXAMPLES
 Join an existing BSS network (i.e., connect to an access point):
diff --git a/share/man/man4/urtwnfw.4 b/share/man/man4/urtwnfw.4
index 0ea2c84dc3a0..c25f944f1b5a 100644
--- a/share/man/man4/urtwnfw.4
+++ b/share/man/man4/urtwnfw.4
@@ -22,7 +22,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd October 31, 2013
+.Dd April 25, 2014
 .Dt URTWNFW 4
 .Os
 .Sh NAME
@@ -42,6 +42,7 @@ of the following:
 .Bd -ragged -offset indent
 .Cd "device urtwn-rtl8192cfwT"
 .Cd "device urtwn-rtl8192cfwU"
+.Cd "device urtwn-rtl8188eufw"
 .Ed
 .Pp
 Alternatively, to load the driver as a
@@ -50,10 +51,11 @@ module at boot time, place the following line in
 .Bd -literal -offset indent
 urtwn-rtl8192cfwT_load="YES"
 urtwn-rtl8192cfwU_load="YES"
+urtwn-rtl8188eufw_load="YES"
 .Ed
 .Sh DESCRIPTION
 This module provides access to firmware sets for the
-Realtek RTL8188CUS, RTL8188CE-VAU, RTL8188RU and RTL8192CU
+Realtek RTL8188CUS, RTL8188CE-VAU, RTL8188EUS, RTL8188RU and RTL8192CU
 chip based USB WiFi adapters.
 It may be
 statically linked into the kernel, or loaded as a module.
diff --git a/sys/conf/files b/sys/conf/files
index f30eb7e8688e..8c0c2fc61059 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -2373,6 +2373,20 @@ dev/usb/wlan/if_upgt.c		optional upgt
 dev/usb/wlan/if_ural.c		optional ural
 dev/usb/wlan/if_urtw.c		optional urtw
 dev/usb/wlan/if_urtwn.c		optional urtwn
+urtwn-rtl8188eufw.c		optional urtwn-rtl8188eufw | urtwnfw	\
+	compile-with	"${AWK} -f $S/tools/fw_stub.awk urtwn-rtl8188eufw.fw:urtwn-rtl8188eufw:111 -murtwn-rtl8188eufw -c${.TARGET}" \
+	no-implicit-rule before-depend local				\
+	clean		"urtwn-rtl8188eufw.c"
+urtwn-rtl8188eufw.fwo		optional urtwn-rtl8188eufw | urtwnfw	\
+	dependency	"urtwn-rtl8188eufw.fw"				\
+	compile-with	"${NORMAL_FWO}"					\
+	no-implicit-rule						\
+	clean		"urtwn-rtl8188eufw.fwo"
+urtwn-rtl8188eufw.fw		optional urtwn-rtl8188eufw | urtwnfw	\
+	dependency	"$S/contrib/dev/urtwn/urtwn-rtl8188eufw.fw.uu"	\
+	compile-with	"${NORMAL_FW}"					\
+	no-obj no-implicit-rule						\
+	clean		"urtwn-rtl8188eufw.fw"
 urtwn-rtl8192cfwT.c		optional urtwn-rtl8192cfwT | urtwnfw	\
 	compile-with	"${AWK} -f $S/tools/fw_stub.awk urtwn-rtl8192cfwT.fw:urtwn-rtl8192cfwT:111 -murtwn-rtl8192cfwT -c${.TARGET}" \
 	no-implicit-rule before-depend local				\
diff --git a/sys/contrib/dev/urtwn/urtwn-rtl8188eufw.fw.uu b/sys/contrib/dev/urtwn/urtwn-rtl8188eufw.fw.uu
new file mode 100644
index 000000000000..1039230f8cd6
--- /dev/null
+++ b/sys/contrib/dev/urtwn/urtwn-rtl8188eufw.fw.uu
@@ -0,0 +1,312 @@
+begin 644 urtwn-rtl8188eufw.fw.uu
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+M1`+P@`_@5/WPD`&Y=`'PD`&X!/"0@2?@8`,21RI_`0%NP^Z4`4`*#>T3D/T0
+M\.0O_R+#[I0!0"20_1'@;7`:D`$7X+4%#9`!Y'1W\)#]$>3P@`;M!)#]$?#D
+M+_\BY)"!3O"C\*/PD`"#X)"!3O"0`(/@_I"!3N#_M08!(L.0@5#@E&20@4_@
+ME`!`#9`!P.!$0/"0@4[@_R*0@4_D=?`!$D2I@,)T12_XYO[M]%[^]G0X+_6"
+MY#0!]8/N\"+3$*\!P\#0D((2[?"0@A'O\-.4!U!PX/]T`:@'"(`"PS/8_/3_
+MD`!'X%_]?T<2,AZ0@A'@_W0!J`<(@`+#,]C\_Y``1N!/_7]&$C(>D((2X&`8
+MD((1X/]T`:@'"(`"PS/8_/^0`$7@3X`7D((1X/]T`:@'"(`"PS/8_/3_D`!%
+MX%_]?T6`?I""$>`D^/#@)`3_=`&H!PB``L,SV/ST_Y``0^!?_7]#$C(>D((1
+MX/]T`:@'"(`"PS/8_/^0`$/@3_U_0Q(R'I""$N!@'9""$>`D!/]T`:@'"(`"
+MPS/8_/^0`$+@3_U_0H`<D((1X"0$_W0!J`<(@`+#,]C\]/^0`$+@7_U_0A(R
+M'M#0DJ\BD($DX%3[\.20@3#PD($K\"+O)/Y@#`1P*)"!+70!\*/P(NUP"I"!
+M.^"0@2WP@`60@2WM\)"!+>"C\)"!)>!$"/`B$DZK[V0!8`B0`;AT`?"`9Y"!
+M*^#_5`-@")`!N'0"\(!6D($IX/[DPYY0")`!N'0$\(!$[S#B")`!N'0(\(`X
+MD($KX##D")`!N'00\(`ID($EX!,35#\@X`B0`;AT(/"`%I"!/N!@")`!N'2`
+M\(`(D`&XY/!_`2*0`;ET!/!_`"+O8$*0@-[@9`%P.I"!)>!4_O"0!2)T#_"0
+M!@3@5+_PY/\23PV_`1*0@23@1$#PD($J=`;PD($C\"*0`;ET`?"0`;AT"/`B
+MD`4B=&_PD`4GX%2_\)"!*G0"\)"!(_`B$E1ED($J=`SPD($C\"*0@23@_Q,3
+M5#\PX!'O5/OPD($KX%3]\%0'<$*`/9"!,.`$\)"!*^!4[_"0@3#@_[0!`H`$
+M[[0"!I`%6.`$\)"!..#_D($PX-.?0`^0@-[@M`$+D($EX%3[\"(21RHB(I`%
+M*^!_`##G`G\!(I`%(G3_\)`%)^!$0/"0@2)T`_`BD`4GX$1`\!))W9"!(G0"
+M\"(22>.0@2)T`O`BD`4B=&_PD`4GX%2_\)"!(G0$\"*N!Q)1<[\!$I"!(^!D
+M`F`*KP9]`1)'/7\!(G\`(I`!5^!@2.3PD`$\=`+PD($DX/\3$U0_,.`,[U3[
+M\)"!*^!4_?`BD($PX`3PD($KX%3O\)"!..#_D($PX-.?0`Z0@-[@M`$'D($E
+MX%3[\"*0@#_@_WT!$FUICE2/5:U5K%2O4Q)/@J]5KE20!(#@5`_]K`=T$2SU
+M@N0T_/6#X$0!\'01+/6"Y#3\]8/@5/OPK`=T%BSU@N0T_/6#X$3Z\'05+/6"
+MY#3\]8/@1!_PK`=T!BSU@N0T_/6#X$0/\)`$4^3PD`12\)`$473_\)`$4'3]
+M\'04+/6"Y#3\]8/@5,!-_704+_6"Y#3\]8/M\"*K!ZH&[2O[Y#KZPY"`V^";
+MD(#:X)I0$Z/@)`'_D(#:X#0`_L/KG_OJGOKJD/T1\*\#=``O]8+D-/OU@^#_
+M(A(?I/]4`?Z0@4+@5/Y.\._#$S#@"I```1(?O9"!0_`BD(%%X##@+9"!2.`$
+L\.#_D(%&X+4''I`&DN!4''`+$D\+D(%)X`3P@`:0!I)T'/#DD(%(\"(`NXX`
+`
+end
diff --git a/sys/dev/usb/usbdevs b/sys/dev/usb/usbdevs
index b2272b6cacfe..253167ce98c7 100644
--- a/sys/dev/usb/usbdevs
+++ b/sys/dev/usb/usbdevs
@@ -3677,6 +3677,7 @@ product RATOC REXUSB60F		0xb020	USB serial adapter REX-USB60F
 /* Green House and CompUSA OEM this part */
 product REALTEK DUMMY		0x0000	Dummy product
 product REALTEK USB20CRW	0x0158	USB20CRW Card Reader
+product REALTEK RTL8188ETV	0x0179	RTL8188ETV
 product REALTEK RTL8188CTV      0x018a  RTL8188CTV
 product REALTEK USBKR100	0x8150	USBKR100 USB Ethernet
 product REALTEK RTL8188CE_0     0x8170  RTL8188CE
diff --git a/sys/dev/usb/wlan/if_urtwn.c b/sys/dev/usb/wlan/if_urtwn.c
index 2a5bfe96da3a..925717505b69 100644
--- a/sys/dev/usb/wlan/if_urtwn.c
+++ b/sys/dev/usb/wlan/if_urtwn.c
@@ -2,6 +2,7 @@
 
 /*-
  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -20,7 +21,7 @@
 __FBSDID("$FreeBSD$");
 
 /*
- * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU.
+ * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU.
  */
 
 #include <sys/param.h>
@@ -88,11 +89,13 @@ SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0,
 /* various supported device vendors/products */
 static const STRUCT_USB_HOST_ID urtwn_devs[] = {
 #define URTWN_DEV(v,p)  { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
+#define	URTWN_RTL8188E_DEV(v,p)	\
+	{ USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) }
+#define URTWN_RTL8188E  1
 	URTWN_DEV(ABOCOM,	RTL8188CU_1),
 	URTWN_DEV(ABOCOM,	RTL8188CU_2),
 	URTWN_DEV(ABOCOM,	RTL8192CU),
 	URTWN_DEV(ASUS,		RTL8192CU),
-	URTWN_DEV(ASUS,		USBN10NANO),
 	URTWN_DEV(AZUREWAVE,	RTL8188CE_1),
 	URTWN_DEV(AZUREWAVE,	RTL8188CE_2),
 	URTWN_DEV(AZUREWAVE,	RTL8188CU),
@@ -147,6 +150,10 @@ static const STRUCT_USB_HOST_ID urtwn_devs[] = {
 	URTWN_DEV(TRENDNET,	RTL8188CU),
 	URTWN_DEV(TRENDNET,	RTL8192CU),
 	URTWN_DEV(ZYXEL,	RTL8192CU),
+	/* URTWN_RTL8188E */
+	URTWN_RTL8188E_DEV(REALTEK,	RTL8188ETV),
+	URTWN_RTL8188E_DEV(REALTEK,	RTL8188EU),
+#undef URTWN_RTL8188E_DEV
 #undef URTWN_DEV
 };
 
@@ -191,15 +198,19 @@ static uint16_t		urtwn_read_2(struct urtwn_softc *, uint16_t);
 static uint32_t		urtwn_read_4(struct urtwn_softc *, uint16_t);
 static int		urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 
 			    const void *, int);
-static void		urtwn_rf_write(struct urtwn_softc *, int, uint8_t, 
-			    uint32_t);
+static void		urtwn_r92c_rf_write(struct urtwn_softc *, int,
+			    uint8_t, uint32_t);
+static void		urtwn_r88e_rf_write(struct urtwn_softc *, int, 
+			    uint8_t, uint32_t);
 static uint32_t		urtwn_rf_read(struct urtwn_softc *, int, uint8_t);
 static int		urtwn_llt_write(struct urtwn_softc *, uint32_t, 
 			    uint32_t);
 static uint8_t		urtwn_efuse_read_1(struct urtwn_softc *, uint16_t);
 static void		urtwn_efuse_read(struct urtwn_softc *);
+static void		urtwn_efuse_switch_power(struct urtwn_softc *);
 static int		urtwn_read_chipid(struct urtwn_softc *);
 static void		urtwn_read_rom(struct urtwn_softc *);
+static void		urtwn_r88e_read_rom(struct urtwn_softc *);
 static int		urtwn_ra_init(struct urtwn_softc *);
 static void		urtwn_tsf_sync_enable(struct urtwn_softc *);
 static void		urtwn_set_led(struct urtwn_softc *, int, int);
@@ -208,6 +219,7 @@ static int		urtwn_newstate(struct ieee80211vap *,
 static void		urtwn_watchdog(void *);
 static void		urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t);
 static int8_t		urtwn_get_rssi(struct urtwn_softc *, int, void *);
+static int8_t		urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *);
 static int		urtwn_tx_start(struct urtwn_softc *,
 			    struct ieee80211_node *, struct mbuf *,
 			    struct urtwn_data *);
@@ -215,13 +227,16 @@ static void		urtwn_start(struct ifnet *);
 static void		urtwn_start_locked(struct ifnet *,
 			    struct urtwn_softc *);
 static int		urtwn_ioctl(struct ifnet *, u_long, caddr_t);
-static int		urtwn_power_on(struct urtwn_softc *);
+static int		urtwn_r92c_power_on(struct urtwn_softc *);
+static int		urtwn_r88e_power_on(struct urtwn_softc *);
 static int		urtwn_llt_init(struct urtwn_softc *);
 static void		urtwn_fw_reset(struct urtwn_softc *);
+static void		urtwn_r88e_fw_reset(struct urtwn_softc *);
 static int		urtwn_fw_loadpage(struct urtwn_softc *, int, 
 			    const uint8_t *, int);
 static int		urtwn_load_firmware(struct urtwn_softc *);
-static int		urtwn_dma_init(struct urtwn_softc *);
+static int		urtwn_r92c_dma_init(struct urtwn_softc *);
+static int		urtwn_r88e_dma_init(struct urtwn_softc *);
 static void		urtwn_mac_init(struct urtwn_softc *);
 static void		urtwn_bb_init(struct urtwn_softc *);
 static void		urtwn_rf_init(struct urtwn_softc *);
@@ -234,6 +249,9 @@ static void		urtwn_write_txpower(struct urtwn_softc *, int,
 static void		urtwn_get_txpower(struct urtwn_softc *, int,
 		      	    struct ieee80211_channel *, 
 			    struct ieee80211_channel *, uint16_t[]);
+static void		urtwn_r88e_get_txpower(struct urtwn_softc *, int,
+		      	    struct ieee80211_channel *, 
+			    struct ieee80211_channel *, uint16_t[]);
 static void		urtwn_set_txpower(struct urtwn_softc *,
 		    	    struct ieee80211_channel *, 
 			    struct ieee80211_channel *);
@@ -352,6 +370,8 @@ urtwn_attach(device_t self)
 	device_set_usb_desc(self);
 	sc->sc_udev = uaa->device;
 	sc->sc_dev = self;
+	if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E)
+		sc->chip |= URTWN_CHIP_88E;
 
 	mtx_init(&sc->sc_mtx, device_get_nameunit(self),
 	    MTX_NETWORK_LOCK, MTX_DEF);
@@ -383,10 +403,15 @@ urtwn_attach(device_t self)
 		sc->ntxchains = 1;
 		sc->nrxchains = 1;
 	}
-	urtwn_read_rom(sc);
+
+	if (sc->chip & URTWN_CHIP_88E)
+		urtwn_r88e_read_rom(sc);
+	else
+		urtwn_read_rom(sc);
 
 	device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n",
 	    (sc->chip & URTWN_CHIP_92C) ? "8192CU" :
+	    (sc->chip & URTWN_CHIP_88E) ? "8188EU" :
 	    (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" :
 	    (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" :
 	    "8188CUS", sc->ntxchains, sc->nrxchains);
@@ -638,7 +663,10 @@ urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p)
 
 	/* Get RSSI from PHY status descriptor if present. */
 	if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
-		rssi = urtwn_get_rssi(sc, rate, &stat[1]);
+		if (sc->chip & URTWN_CHIP_88E) 
+			rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]);
+		else
+			rssi = urtwn_get_rssi(sc, rate, &stat[1]);
 		/* Update our average RSSI. */
 		urtwn_update_avgrssi(sc, rate, rssi);
 		/*
@@ -1056,14 +1084,31 @@ urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len)
 	return (0);
 }
 
-static void
+static __inline void
 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
+{
+
+	sc->sc_rf_write(sc, chain, addr, val);
+}
+
+static void
+urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
+    uint32_t val)
 {
 	urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
 	    SM(R92C_LSSI_PARAM_ADDR, addr) |
 	    SM(R92C_LSSI_PARAM_DATA, val));
 }
 
+static void
+urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
+uint32_t val)
+{
+	urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
+	    SM(R88E_LSSI_PARAM_ADDR, addr) |
+	    SM(R92C_LSSI_PARAM_DATA, val));
+}
+
 static uint32_t
 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr)
 {
@@ -1143,22 +1188,8 @@ urtwn_efuse_read(struct urtwn_softc *sc)
 	uint8_t off, msk;
 	int i;
 
-	reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
-	if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
-		urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
-		    reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
-	}
-	reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
-	if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
-		urtwn_write_2(sc, R92C_SYS_FUNC_EN,
-		    reg | R92C_SYS_FUNC_EN_ELDR);
-	}
-	reg = urtwn_read_2(sc, R92C_SYS_CLKR);
-	if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
-	    (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
-		urtwn_write_2(sc, R92C_SYS_CLKR,
-		    reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
-	}
+	urtwn_efuse_switch_power(sc);
+
 	memset(&sc->rom, 0xff, sizeof(sc->rom));
 	while (addr < 512) {
 		reg = urtwn_efuse_read_1(sc, addr);
@@ -1188,12 +1219,37 @@ urtwn_efuse_read(struct urtwn_softc *sc)
 	}
 #endif
 }
+static void
+urtwn_efuse_switch_power(struct urtwn_softc *sc)
+{
+	uint32_t reg;
+
+	reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
+	if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
+		urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
+		    reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
+	}
+	reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
+	if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
+		urtwn_write_2(sc, R92C_SYS_FUNC_EN,
+		    reg | R92C_SYS_FUNC_EN_ELDR);
+	}
+	reg = urtwn_read_2(sc, R92C_SYS_CLKR);
+	if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
+	    (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
+		urtwn_write_2(sc, R92C_SYS_CLKR,
+		    reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
+	}
+}
 
 static int
 urtwn_read_chipid(struct urtwn_softc *sc)
 {
 	uint32_t reg;
 
+	if (sc->chip & URTWN_CHIP_88E)
+		return (0);
+
 	reg = urtwn_read_4(sc, R92C_SYS_CFG);
 	if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
 		return (EIO);
@@ -1230,8 +1286,69 @@ urtwn_read_rom(struct urtwn_softc *sc)
 
 	sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
 	DPRINTF("regulatory type=%d\n", sc->regulatory);
-
 	IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr);
+
+	sc->sc_rf_write = urtwn_r92c_rf_write;
+	sc->sc_power_on = urtwn_r92c_power_on;
+	sc->sc_dma_init = urtwn_r92c_dma_init;
+}
+
+static void
+urtwn_r88e_read_rom(struct urtwn_softc *sc)
+{
+	uint8_t *rom = sc->r88e_rom;
+	uint16_t addr = 0;
+	uint32_t reg;
+	uint8_t off, msk, tmp;
+	int i;
+
+	urtwn_efuse_switch_power(sc);
+
+	/* Read full ROM image. */
+	memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom));
+	while (addr < 1024) {
+		reg = urtwn_efuse_read_1(sc, addr);
+		if (reg == 0xff)
+			break;
+		addr++;
+		if ((reg & 0x1f) == 0x0f) {
+			tmp = (reg & 0xe0) >> 5;
+			reg = urtwn_efuse_read_1(sc, addr);
+			if ((reg & 0x0f) != 0x0f)
+				off = ((reg & 0xf0) >> 1) | tmp;
+			addr++;
+		} else
+			off = reg >> 4;
+		msk = reg & 0xf;
+		for (i = 0; i < 4; i++) {
+			if (msk & (1 << i))
+				continue;
+			rom[off * 8 + i * 2 + 0] =
+			    urtwn_efuse_read_1(sc, addr);
+			addr++;
+			rom[off * 8 + i * 2 + 1] =
+			    urtwn_efuse_read_1(sc, addr);
+			addr++;
+		}
+	}
+
+	addr = 0x10;
+	for (i = 0; i < 6; i++)
+		sc->cck_tx_pwr[i] = sc->r88e_rom[addr++];
+	for (i = 0; i < 5; i++)
+		sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++];
+	sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4;
+	if (sc->bw20_tx_pwr_diff & 0x08)
+		sc->bw20_tx_pwr_diff |= 0xf0;
+	sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf);
+	if (sc->ofdm_tx_pwr_diff & 0x08)
+		sc->ofdm_tx_pwr_diff |= 0xf0;
+	sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY);
+	IEEE80211_ADDR_COPY(sc->sc_bssid, &sc->r88e_rom[0xd7]);
+
+	sc->sc_rf_write = urtwn_r88e_rf_write;
+	sc->sc_power_on = urtwn_r88e_power_on;
+	sc->sc_dma_init = urtwn_r88e_dma_init;
 }
 
 /*
@@ -1349,13 +1466,26 @@ static void
 urtwn_set_led(struct urtwn_softc *sc, int led, int on)
 {
 	uint8_t reg;
-
+	
 	if (led == URTWN_LED_LINK) {
-		reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
-		if (!on)
-			reg |= R92C_LEDCFG0_DIS;
-		urtwn_write_1(sc, R92C_LEDCFG0, reg);
-		sc->ledlink = on;	/* Save LED state. */
+		if (sc->chip & URTWN_CHIP_88E) {
+			reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
+			urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60);
+			if (!on) {
+				reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90;
+				urtwn_write_1(sc, R92C_LEDCFG2,
+				    reg | R92C_LEDCFG0_DIS);
+				urtwn_write_1(sc, R92C_MAC_PINMUX_CFG,
+				    urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) &
+				    0xfe);
+			}
+		} else {
+			reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
+			if (!on)
+				reg |= R92C_LEDCFG0_DIS;
+			urtwn_write_1(sc, R92C_LEDCFG0, reg);
+		}
+		sc->ledlink = on;       /* Save LED state. */
 	}
 }
 
@@ -1421,11 +1551,12 @@ urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
 			reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
 			urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
 
-			reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
-			reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
-			urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
+			if (!(sc->chip & URTWN_CHIP_88E)) {
+				reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
+				reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
+				urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
+			}
 		}
-
 		/* Make link LED blink during scan. */
 		urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
 
@@ -1441,10 +1572,11 @@ urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
 		reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
 		urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
 
-		reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
-		reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
-		urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
-
+		if (!(sc->chip & URTWN_CHIP_88E)) {
+			reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
+			reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
+			urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
+		}
 		urtwn_set_chan(sc, ic->ic_curchan, NULL);
 		break;
 	case IEEE80211_S_RUN:
@@ -1497,7 +1629,11 @@ urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
 		urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
 
 		/* Intialize rate adaptation. */
-		urtwn_ra_init(sc);
+		if (sc->chip & URTWN_CHIP_88E)
+			ni->ni_txrate =
+			    ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1];
+		else 
+			urtwn_ra_init(sc);
 		/* Turn link LED on. */
 		urtwn_set_led(sc, URTWN_LED_LINK, 1);
 
@@ -1543,19 +1679,21 @@ urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi)
 		pwdb = 100;
 	else
 		pwdb = 100 + rssi;
-	if (rate <= 3) {
-		/* CCK gain is smaller than OFDM/MCS gain. */
-		pwdb += 6;
-		if (pwdb > 100)
-			pwdb = 100;
-		if (pwdb <= 14)
-			pwdb -= 4;
-		else if (pwdb <= 26)
-			pwdb -= 8;
-		else if (pwdb <= 34)
-			pwdb -= 6;
-		else if (pwdb <= 42)
-			pwdb -= 2;
+	if (!(sc->chip & URTWN_CHIP_88E)) {
+		if (rate <= 3) {
+			/* CCK gain is smaller than OFDM/MCS gain. */
+			pwdb += 6;
+			if (pwdb > 100)
+				pwdb = 100;
+			if (pwdb <= 14)
+				pwdb -= 4;
+			else if (pwdb <= 26)
+				pwdb -= 8;
+			else if (pwdb <= 34)
+				pwdb -= 6;
+			else if (pwdb <= 42)
+				pwdb -= 2;
+		}
 	}
 	if (sc->avg_pwdb == -1)	/* Init. */
 		sc->avg_pwdb = pwdb;
@@ -1592,6 +1730,57 @@ urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
 	return (rssi);
 }
 
+static int8_t
+urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
+{
+	struct r92c_rx_phystat *phy;
+	struct r88e_rx_cck *cck;
+	uint8_t cck_agc_rpt, lna_idx, vga_idx;
+	int8_t rssi;
+
+	if (rate <= 3) {
+		cck = (struct r88e_rx_cck *)physt;
+		cck_agc_rpt = cck->agc_rpt;
+		lna_idx = (cck_agc_rpt & 0xe0) >> 5;
+		vga_idx = cck_agc_rpt & 0x1f; 
+		switch (lna_idx) {
+		case 7:
+			if (vga_idx <= 27)
+				rssi = -100 + 2* (27 - vga_idx);
+			else
+				rssi = -100;
+			break;
+		case 6:
+			rssi = -48 + 2 * (2 - vga_idx);
+			break;
+		case 5:
+			rssi = -42 + 2 * (7 - vga_idx);
+			break;
+		case 4:
+			rssi = -36 + 2 * (7 - vga_idx);
+			break;
+		case 3:
+			rssi = -24 + 2 * (7 - vga_idx);
+			break;
+		case 2:
+			rssi = -12 + 2 * (5 - vga_idx);
+			break;
+		case 1:
+			rssi = 8 - (2 * vga_idx);
+			break;
+		case 0:
+			rssi = 14 - (2 * vga_idx);
+			break;
+		}
+		rssi += 6;
+	} else {	/* OFDM/HT. */
+		phy = (struct r92c_rx_phystat *)physt;
+		rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
+	}
+	return (rssi);
+}
+
+
 static int
 urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 
     struct mbuf *m0, struct urtwn_data *data)
@@ -1619,6 +1808,8 @@ urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni,
 	 * Software crypto.
 	 */
 	wh = mtod(m0, struct ieee80211_frame *);
+	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
+
 	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
 		k = ieee80211_crypto_encap(ni, m0);
 		if (k == NULL) {
@@ -1633,7 +1824,7 @@ urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni,
 		wh = mtod(m0, struct ieee80211_frame *);
 	}
 	
-	switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
+	switch (type) {
 	case IEEE80211_FC0_TYPE_CTL:
 	case IEEE80211_FC0_TYPE_MGT:
 		xfer = sc->sc_xfer[URTWN_BULK_TX_VO];
@@ -1657,20 +1848,24 @@ urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni,
 	    R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
 	if (IEEE80211_IS_MULTICAST(wh->i_addr1))
 		txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
-
-	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
 	if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
 	    type == IEEE80211_FC0_TYPE_DATA) {
 		if (ic->ic_curmode == IEEE80211_MODE_11B)
 			raid = R92C_RAID_11B;
 		else
 			raid = R92C_RAID_11BG;
-		txd->txdw1 |= htole32(
-		    SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) |
-		    SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
-		    SM(R92C_TXDW1_RAID, raid) |
-		    R92C_TXDW1_AGGBK);
-
+		if (sc->chip & URTWN_CHIP_88E) {
+			txd->txdw1 |= htole32(
+			    SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) |
+			    SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
+			    SM(R92C_TXDW1_RAID, raid));
+			txd->txdw2 |= htole32(R88E_TXDW2_AGGBK);
+		} else {
+			txd->txdw1 |= htole32(
+			    SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) |
+			    SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
+		 	    SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK);
+		}
 		if (ic->ic_flags & IEEE80211_F_USEPROT) {
 			if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
 				txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
@@ -1684,7 +1879,10 @@ urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni,
 		txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8));
 		txd->txdw5 |= htole32(0x0001ff00);
 		/* Send data at OFDM54. */
-		txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
+		if (sc->chip & URTWN_CHIP_88E)
+			txd->txdw5 |= htole32(0x13 & 0x3f);
+		else
+			txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
 	} else {
 		txd->txdw1 |= htole32(
 		    SM(R92C_TXDW1_MACID, 0) |
@@ -1882,8 +2080,15 @@ urtwn_alloc_tx_list(struct urtwn_softc *sc)
 	return (0);
 }
 
-static int
+static __inline int
 urtwn_power_on(struct urtwn_softc *sc)
+{
+
+	return sc->sc_power_on(sc);
+}
+
+static int
+urtwn_r92c_power_on(struct urtwn_softc *sc)
 {
 	uint32_t reg;
 	int ntries;
@@ -1967,13 +2172,74 @@ urtwn_power_on(struct urtwn_softc *sc)
 	return (0);
 }
 
+static int
+urtwn_r88e_power_on(struct urtwn_softc *sc)
+{
+	uint8_t val;
+	uint32_t reg;
+	int ntries;
+
+	/* Wait for power ready bit. */
+	for (ntries = 0; ntries < 5000; ntries++) {
+		val = urtwn_read_1(sc, 0x6) & 0x2;
+		if (val == 0x2)
+			break;
+		DELAY(10);
+	}
+	if (ntries == 5000) {
+		device_printf(sc->sc_dev,
+		    "timeout waiting for chip power up\n");
+		return (ETIMEDOUT);
+	}
+
+	/* Reset BB. */
+	urtwn_write_1(sc, R92C_SYS_FUNC_EN,
+	    urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
+	    R92C_SYS_FUNC_EN_BB_GLB_RST));
+
+	urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80);
+
+	/* Disable HWPDN. */
+	urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80);
+
+	/* Disable WL suspend. */
+	urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18);
+
+	urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1);
+	for (ntries = 0; ntries < 5000; ntries++) {
+		if (!(urtwn_read_1(sc, 0x5) & 0x1))
+			break;
+		DELAY(10);
+	}
+	if (ntries == 5000)
+		return (ETIMEDOUT);
+
+	/* Enable LDO normal mode. */
+	urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10);
+
+	/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
+	urtwn_write_2(sc, R92C_CR, 0);
+	reg = urtwn_read_2(sc, R92C_CR);
+	reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
+	    R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
+	    R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN;
+	urtwn_write_2(sc, R92C_CR, reg);
+
+	return (0);
+}
+
 static int
 urtwn_llt_init(struct urtwn_softc *sc)
 {
-	int i, error;
+	int i, error, page_count, pktbuf_count;
 
-	/* Reserve pages [0; R92C_TX_PAGE_COUNT]. */
-	for (i = 0; i < R92C_TX_PAGE_COUNT; i++) {
+	page_count = (sc->chip & URTWN_CHIP_88E) ?
+	    R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT;
+	pktbuf_count = (sc->chip & URTWN_CHIP_88E) ?
+	    R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT;
+
+	/* Reserve pages [0; page_count]. */
+	for (i = 0; i < page_count; i++) {
 		if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
 			return (error);
 	}
@@ -1981,15 +2247,15 @@ urtwn_llt_init(struct urtwn_softc *sc)
 	if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
 		return (error);
 	/*
-	 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1]
+	 * Use pages [page_count + 1; pktbuf_count - 1]
 	 * as ring buffer.
 	 */
-	for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) {
+	for (++i; i < pktbuf_count - 1; i++) {
 		if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
 			return (error);
 	}
 	/* Make the last page point to the beginning of the ring buffer. */
-	error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1);
+	error = urtwn_llt_write(sc, i, page_count + 1);
 	return (error);
 }
 
@@ -2011,6 +2277,19 @@ urtwn_fw_reset(struct urtwn_softc *sc)
 	}
 	/* Force 8051 reset. */
 	urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
+	urtwn_write_2(sc, R92C_SYS_FUNC_EN,
+	    urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
+	    R92C_SYS_FUNC_EN_CPUEN);
+}
+
+static void
+urtwn_r88e_fw_reset(struct urtwn_softc *sc)
+{
+	uint16_t reg;
+
+	reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
+	urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
+	urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);
 }
 
 static int
@@ -2056,8 +2335,10 @@ urtwn_load_firmware(struct urtwn_softc *sc)
 
 	URTWN_UNLOCK(sc);
 	/* Read firmware image from the filesystem. */
-	if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
-	    URTWN_CHIP_UMC_A_CUT)
+	if (sc->chip & URTWN_CHIP_88E)
+		imagename = "urtwn-rtl8188eufw";
+	else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
+		    URTWN_CHIP_UMC_A_CUT)
 		imagename = "urtwn-rtl8192cfwU";
 	else
 		imagename = "urtwn-rtl8192cfwT";
@@ -2081,6 +2362,7 @@ urtwn_load_firmware(struct urtwn_softc *sc)
 	hdr = (const struct r92c_fw_hdr *)ptr;
 	/* Check if there is a valid FW header and skip it. */
 	if ((le16toh(hdr->signature) >> 4) == 0x88c ||
+	    (le16toh(hdr->signature) >> 4) == 0x88e ||
 	    (le16toh(hdr->signature) >> 4) == 0x92c) {
 		DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n",
 		    le16toh(hdr->version), le16toh(hdr->subversion),
@@ -2089,13 +2371,14 @@ urtwn_load_firmware(struct urtwn_softc *sc)
 		len -= sizeof(*hdr);
 	}
 
-	if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) {
-		urtwn_fw_reset(sc);
+	if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) {
+		if (sc->chip & URTWN_CHIP_88E)
+			urtwn_r88e_fw_reset(sc);
+		else
+			urtwn_fw_reset(sc);
 		urtwn_write_1(sc, R92C_MCUFWDL, 0);
 	}
-	urtwn_write_2(sc, R92C_SYS_FUNC_EN,
-	    urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
-	    R92C_SYS_FUNC_EN_CPUEN);
+
 	urtwn_write_1(sc, R92C_MCUFWDL,
 	    urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
 	urtwn_write_1(sc, R92C_MCUFWDL + 2,
@@ -2136,6 +2419,8 @@ urtwn_load_firmware(struct urtwn_softc *sc)
 	reg = urtwn_read_4(sc, R92C_MCUFWDL);
 	reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
 	urtwn_write_4(sc, R92C_MCUFWDL, reg);
+	if (sc->chip & URTWN_CHIP_88E)
+		urtwn_r88e_fw_reset(sc);
 	/* Wait for firmware readiness. */
 	for (ntries = 0; ntries < 1000; ntries++) {
 		if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
@@ -2153,8 +2438,15 @@ fail:
 	return (error);
 }
 
-static int
+static __inline int
 urtwn_dma_init(struct urtwn_softc *sc)
+{
+            
+	return sc->sc_dma_init(sc);
+}
+
+static int
+urtwn_r92c_dma_init(struct urtwn_softc *sc)
 {
 	int hashq, hasnq, haslq, nqueues, nqpages, nrempages;
 	uint32_t reg;
@@ -2233,14 +2525,75 @@ urtwn_dma_init(struct urtwn_softc *sc)
 	return (0);
 }
 
+static int
+urtwn_r88e_dma_init(struct urtwn_softc *sc)
+{
+	struct usb_interface *iface;
+	uint32_t reg;
+	int nqueues;
+	int error;
+
+	/* Initialize LLT table. */
+	error = urtwn_llt_init(sc);
+	if (error != 0)
+		return (error);
+
+	/* Get Tx queues to USB endpoints mapping. */
+	iface = usbd_get_iface(sc->sc_udev, 0);
+	nqueues = iface->idesc->bNumEndpoints - 1;
+	if (nqueues == 0)
+		return (EIO);
+
+	/* Set number of pages for normal priority queue. */
+	urtwn_write_2(sc, R92C_RQPN_NPQ, 0);
+	urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d);
+	urtwn_write_4(sc, R92C_RQPN, 0x808e000d);
+
+	urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY);
+	urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY);
+	urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY);
+	urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY);
+	urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY);
+
+	/* Set queue to USB pipe mapping. */
+	reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
+	reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
+	if (nqueues == 1)
+		reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
+	else if (nqueues == 2)
+		reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
+	else
+		reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
+	urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
+
+	/* Set Tx/Rx transfer page boundary. */
+	urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff);
+
+	/* Set Tx/Rx transfer page size. */
+	urtwn_write_1(sc, R92C_PBP,
+	    SM(R92C_PBP_PSRX, R92C_PBP_128) |
+	    SM(R92C_PBP_PSTX, R92C_PBP_128));
+
+	return (0);
+}
+
 static void
 urtwn_mac_init(struct urtwn_softc *sc)
 {
 	int i;
 
 	/* Write MAC initialization values. */
-	for (i = 0; i < nitems(rtl8192cu_mac); i++)
-		urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val);
+	if (sc->chip & URTWN_CHIP_88E) {
+		for (i = 0; i < nitems(rtl8188eu_mac); i++) {
+			urtwn_write_1(sc, rtl8188eu_mac[i].reg,
+			    rtl8188eu_mac[i].val);
+		}
+		urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07);
+	} else {
+		for (i = 0; i < nitems(rtl8192cu_mac); i++)
+			urtwn_write_1(sc, rtl8192cu_mac[i].reg,
+			    rtl8192cu_mac[i].val);
+	}
 }
 
 static void
@@ -2248,6 +2601,7 @@ urtwn_bb_init(struct urtwn_softc *sc)
 {
 	const struct urtwn_bb_prog *prog;
 	uint32_t reg;
+	uint8_t crystalcap;
 	int i;
 
 	/* Enable BB and RF. */
@@ -2256,7 +2610,8 @@ urtwn_bb_init(struct urtwn_softc *sc)
 	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
 	    R92C_SYS_FUNC_EN_DIO_RF);
 
-	urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
+	if (!(sc->chip & URTWN_CHIP_88E))
+		urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
 
 	urtwn_write_1(sc, R92C_RF_CTRL,
 	    R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
@@ -2264,12 +2619,16 @@ urtwn_bb_init(struct urtwn_softc *sc)
 	    R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
 	    R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
 
-	urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
-	urtwn_write_1(sc, 0x15, 0xe9);
-	urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
+	if (!(sc->chip & URTWN_CHIP_88E)) {
+		urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
+		urtwn_write_1(sc, 0x15, 0xe9);
+		urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
+	}
 
 	/* Select BB programming based on board type. */
-	if (!(sc->chip & URTWN_CHIP_92C)) {
+	if (sc->chip & URTWN_CHIP_88E)
+		prog = &rtl8188eu_bb_prog;
+	else if (!(sc->chip & URTWN_CHIP_92C)) {
 		if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
 			prog = &rtl8188ce_bb_prog;
 		else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
@@ -2334,9 +2693,25 @@ urtwn_bb_init(struct urtwn_softc *sc)
 		DELAY(1);
 	}
 
-	if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
-	    R92C_HSSI_PARAM2_CCK_HIPWR)
-		sc->sc_flags |= URTWN_FLAG_CCK_HIPWR;
+	if (sc->chip & URTWN_CHIP_88E) {
+		urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
+		DELAY(1);
+		urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
+		DELAY(1);
+
+		crystalcap = sc->r88e_rom[0xb9];
+		if (crystalcap == 0xff)
+			crystalcap = 0x20;
+		crystalcap &= 0x3f;
+		reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
+		urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
+		    RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
+		    crystalcap | crystalcap << 6));
+	} else {
+		if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
+		    R92C_HSSI_PARAM2_CCK_HIPWR)
+			sc->sc_flags |= URTWN_FLAG_CCK_HIPWR;
+	}
 }
 
 void
@@ -2347,7 +2722,9 @@ urtwn_rf_init(struct urtwn_softc *sc)
 	int i, j, idx, off;
 
 	/* Select RF programming based on board type. */
-	if (!(sc->chip & URTWN_CHIP_92C)) {
+	if (sc->chip & URTWN_CHIP_88E)
+		prog = rtl8188eu_rf_prog;
+	else if (!(sc->chip & URTWN_CHIP_92C)) {
 		if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
 			prog = rtl8188ce_rf_prog;
 		else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
@@ -2637,6 +3014,75 @@ urtwn_get_txpower(struct urtwn_softc *sc, int chain,
 #endif
 }
 
+void
+urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain,
+    struct ieee80211_channel *c, struct ieee80211_channel *extc,
+    uint16_t power[URTWN_RIDX_COUNT])
+{
+	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
+	uint16_t cckpow, ofdmpow, bw20pow, htpow;
+	const struct urtwn_r88e_txpwr *base;
+	int ridx, chan, group;
+
+	/* Determine channel group. */
+	chan = ieee80211_chan2ieee(ic, c);	/* XXX center freq! */
+	if (chan <= 2)
+		group = 0;
+	else if (chan <= 5)
+		group = 1;
+	else if (chan <= 8)
+		group = 2;
+	else if (chan <= 11)
+		group = 3;
+	else if (chan <= 13)
+		group = 4;
+	else
+		group = 5;
+
+	/* Get original Tx power based on board type and RF chain. */
+	base = &rtl8188eu_txagc[chain];
+
+	memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
+	if (sc->regulatory == 0) {
+		for (ridx = 0; ridx <= 3; ridx++)
+			power[ridx] = base->pwr[0][ridx];
+	}
+	for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) {
+		if (sc->regulatory == 3)
+			power[ridx] = base->pwr[0][ridx];
+		else if (sc->regulatory == 1) {
+			if (extc == NULL)
+				power[ridx] = base->pwr[group][ridx];
+		} else if (sc->regulatory != 2)
+			power[ridx] = base->pwr[0][ridx];
+	}
+
+	/* Compute per-CCK rate Tx power. */
+	cckpow = sc->cck_tx_pwr[group];
+	for (ridx = 0; ridx <= 3; ridx++) {
+		power[ridx] += cckpow;
+		if (power[ridx] > R92C_MAX_TX_PWR)
+			power[ridx] = R92C_MAX_TX_PWR;
+	}
+
+	htpow = sc->ht40_tx_pwr[group];
+
+	/* Compute per-OFDM rate Tx power. */
+	ofdmpow = htpow + sc->ofdm_tx_pwr_diff;
+	for (ridx = 4; ridx <= 11; ridx++) {
+		power[ridx] += ofdmpow;
+		if (power[ridx] > R92C_MAX_TX_PWR)
+			power[ridx] = R92C_MAX_TX_PWR;
+	}
+
+	bw20pow = htpow + sc->bw20_tx_pwr_diff;
+	for (ridx = 12; ridx <= 27; ridx++) {
+		power[ridx] += bw20pow;
+		if (power[ridx] > R92C_MAX_TX_PWR)
+			power[ridx] = R92C_MAX_TX_PWR;
+	}
+}
+
 void
 urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c,
     struct ieee80211_channel *extc)
@@ -2646,7 +3092,10 @@ urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c,
 
 	for (i = 0; i < sc->ntxchains; i++) {
 		/* Compute per-rate Tx power values. */
-		urtwn_get_txpower(sc, i, c, extc, power);
+		if (sc->chip & URTWN_CHIP_88E)
+			urtwn_r88e_get_txpower(sc, i, c, extc, power);
+		else
+			urtwn_get_txpower(sc, i, c, extc, power);
 		/* Write per-rate Tx power values to hardware. */
 		urtwn_write_txpower(sc, i, power);
 	}
@@ -2751,13 +3200,17 @@ urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c,
 		urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
 		    urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
 
-		urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
-		    urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
-		    R92C_FPGA0_ANAPARAM2_CBW20);
-
+		if (!(sc->chip & URTWN_CHIP_88E)) {
+			urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
+			    urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
+			    R92C_FPGA0_ANAPARAM2_CBW20);
+		}
+			
 		/* Select 20MHz bandwidth. */
 		urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
-		    (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan);
+		    (sc->rf_chnlbw[0] & ~0xfff) | chan | 
+		    ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 :
+		    R92C_RF_CHNLBW_BW20));
 	}
 }
 
@@ -2849,8 +3302,19 @@ urtwn_init_locked(void *arg)
 	urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
 
 	/* Init interrupts. */
-	urtwn_write_4(sc, R92C_HISR, 0xffffffff);
-	urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
+	if (sc->chip & URTWN_CHIP_88E) {
+		urtwn_write_4(sc, R88E_HISR, 0xffffffff);
+		urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
+		    R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT);
+		urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
+		    R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR);
+		urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
+		    urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
+		    R92C_USB_SPECIAL_OPTION_INT_BULK_SEL);
+	} else {
+		urtwn_write_4(sc, R92C_HISR, 0xffffffff);
+		urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
+	}
 
 	/* Set MAC address. */
 	urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp),
@@ -2875,10 +3339,12 @@ urtwn_init_locked(void *arg)
 	urtwn_edca_init(sc);
 
 	/* Setup rate fallback. */
-	urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
-	urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
-	urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
-	urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
+	if (!(sc->chip & URTWN_CHIP_88E)) {
+		urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
+		urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
+		urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
+		urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
+	}
 
 	urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
 	    urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) |
@@ -2897,23 +3363,28 @@ urtwn_init_locked(void *arg)
 	    urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
 	    R92C_USB_SPECIAL_OPTION_AGG_EN);
 	urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
-	urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
+	if (sc->chip & URTWN_CHIP_88E)
+		urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
+	else
+		urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
 	urtwn_write_1(sc, R92C_USB_AGG_TH, 8);
 	urtwn_write_1(sc, R92C_USB_AGG_TO, 6);
 
 	/* Initialize beacon parameters. */
+	urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010);
 	urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
 	urtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
 	urtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
 	urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
 
-	/* Setup AMPDU aggregation. */
-	urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631);	/* MCS7~0 */
-	urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
-	urtwn_write_2(sc, 0x4ca, 0x0708);
+	if (!(sc->chip & URTWN_CHIP_88E)) {
+		/* Setup AMPDU aggregation. */
+		urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631);	/* MCS7~0 */
+		urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
+		urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708);
 
-	urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
-	urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0);
+		urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
+	}
 
 	/* Load 8051 microcode. */
 	error = urtwn_load_firmware(sc);
@@ -2925,6 +3396,12 @@ urtwn_init_locked(void *arg)
 	urtwn_bb_init(sc);
 	urtwn_rf_init(sc);
 
+	if (sc->chip & URTWN_CHIP_88E) {
+		urtwn_write_2(sc, R92C_CR,
+		    urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN |
+		    R92C_CR_MACRXEN);
+	}
+
 	/* Turn CCK and OFDM blocks on. */
 	reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
 	reg |= R92C_RFMOD_CCK_EN;
@@ -2945,18 +3422,21 @@ urtwn_init_locked(void *arg)
 	urtwn_lc_calib(sc);
 
 	/* Fix USB interference issue. */
-	urtwn_write_1(sc, 0xfe40, 0xe0);
-	urtwn_write_1(sc, 0xfe41, 0x8d);
-	urtwn_write_1(sc, 0xfe42, 0x80);
+	if (!(sc->chip & URTWN_CHIP_88E)) {
+		urtwn_write_1(sc, 0xfe40, 0xe0);
+		urtwn_write_1(sc, 0xfe41, 0x8d);
+		urtwn_write_1(sc, 0xfe42, 0x80);
 
-	urtwn_pa_bias_init(sc);
+		urtwn_pa_bias_init(sc);
+	}
 
 	/* Initialize GPIO setting. */
 	urtwn_write_1(sc, R92C_GPIO_MUXCFG,
 	    urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
 
 	/* Fix for lower temperature. */
-	urtwn_write_1(sc, 0x15, 0xe9);
+	if (!(sc->chip & URTWN_CHIP_88E))
+		urtwn_write_1(sc, 0x15, 0xe9);
 
 	usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]);
 
@@ -3057,7 +3537,7 @@ static device_method_t urtwn_methods[] = {
 	DEVMETHOD(device_attach,	urtwn_attach),
 	DEVMETHOD(device_detach,	urtwn_detach),
 
-	{ 0, 0 }
+	DEVMETHOD_END
 };
 
 static driver_t urtwn_driver = {
diff --git a/sys/dev/usb/wlan/if_urtwnreg.h b/sys/dev/usb/wlan/if_urtwnreg.h
index c2d88b5a1262..4eef0293380c 100644
--- a/sys/dev/usb/wlan/if_urtwnreg.h
+++ b/sys/dev/usb/wlan/if_urtwnreg.h
@@ -33,6 +33,9 @@
 #define R92C_TXPKTBUF_COUNT	256
 #define R92C_TX_PAGE_COUNT	248
 #define R92C_TX_PAGE_BOUNDARY	(R92C_TX_PAGE_COUNT + 1)
+#define R88E_TXPKTBUF_COUNT	177
+#define R88E_TX_PAGE_COUNT	169
+#define R88E_TX_PAGE_BOUNDARY	(R88E_TX_PAGE_COUNT + 1)
 
 #define R92C_H2C_NBOX	4
 
@@ -78,6 +81,11 @@
 #define R92C_HSISR			0x05c
 #define R92C_MCUFWDL			0x080
 #define R92C_HMEBOX_EXT(idx)		(0x088 + (idx) * 2)
+#define R88E_HIMR			0x0b0
+#define R88E_HISR			0x0b4
+#define R88E_HIMRE			0x0b8
+#define R88E_HISRE			0x0bc
+#define R92C_EFUSE_ACCESS               0x0cf
 #define R92C_BIST_SCAN			0x0d0
 #define R92C_BIST_RPT			0x0d4
 #define R92C_BIST_ROM_RPT		0x0d8
@@ -118,6 +126,7 @@
 #define R92C_LLT_INIT			0x1e0
 #define R92C_BB_ACCESS_CTRL		0x1e8
 #define R92C_BB_ACCESS_DATA		0x1ec
+#define R88E_HMEBOX_EXT(idx)            (0x1f0 + (idx) * 4)
 /* Tx DMA Configuration. */
 #define R92C_RQPN			0x200
 #define R92C_FIFOPAGE			0x204
@@ -147,6 +156,7 @@
 #define R92C_RD_RESP_PKT_TH		0x463
 #define R92C_INIRTS_RATE_SEL		0x480
 #define R92C_INIDATA_RATE_SEL(macid)	(0x484 + (macid))
+#define R92C_MAX_AGGR_NUM		0x4ca
 /* EDCA Configuration. */
 #define R92C_EDCA_VO_PARAM		0x500
 #define R92C_EDCA_VI_PARAM		0x504
@@ -292,6 +302,10 @@
 /* Bits for R92C_LDOV12D_CTRL. */
 #define R92C_LDOV12D_CTRL_LDV12_EN	0x01
 
+/* Bits for R92C_AFE_XTAL_CTRL. */
+#define R92C_AFE_XTAL_CTRL_ADDR_M	0x007ff800
+#define R92C_AFE_XTAL_CTRL_ADDR_S	11
+
 /* Bits for R92C_EFUSE_CTRL. */
 #define R92C_EFUSE_CTRL_DATA_M	0x000000ff
 #define R92C_EFUSE_CTRL_DATA_S	0
@@ -313,10 +327,27 @@
 #define R92C_MCUFWDL_BBINI_RDY		0x00000010
 #define R92C_MCUFWDL_RFINI_RDY		0x00000020
 #define R92C_MCUFWDL_WINTINI_RDY	0x00000040
+#define R92C_MCUFWDL_RAM_DL_SEL		0x00000080
 #define R92C_MCUFWDL_PAGE_M		0x00070000
 #define R92C_MCUFWDL_PAGE_S		16
 #define R92C_MCUFWDL_CPRST		0x00800000
 
+/* Bits for R88E_HIMR. */
+#define R88E_HIMR_CPWM			0x00000100
+#define R88E_HIMR_CPWM2			0x00000200
+#define R88E_HIMR_TBDER			0x04000000
+#define R88E_HIMR_PSTIMEOUT		0x20000000
+
+/* Bits for R88E_HIMRE.*/
+#define R88E_HIMRE_RXFOVW		0x00000100
+#define R88E_HIMRE_TXFOVW		0x00000200
+#define R88E_HIMRE_RXERR		0x00000400
+#define R88E_HIMRE_TXERR		0x00000800
+
+/* Bits for R92C_EFUSE_ACCESS. */
+#define R92C_EFUSE_ACCESS_OFF		0x00
+#define R92C_EFUSE_ACCESS_ON		0x69
+
 /* Bits for R92C_HPON_FSM. */
 #define R92C_HPON_FSM_CHIP_BONDING_ID_S		22
 #define R92C_HPON_FSM_CHIP_BONDING_ID_M		0x00c00000
@@ -355,6 +386,7 @@
 #define R92C_CR_MACTXEN		0x00000040
 #define R92C_CR_MACRXEN		0x00000080
 #define R92C_CR_ENSEC		0x00000200
+#define R92C_CR_CALTMR_EN	0x00000400
 #define R92C_CR_NETTYPE_S	16
 #define R92C_CR_NETTYPE_M	0x00030000
 #define R92C_CR_NETTYPE_NOLINK	0
@@ -641,6 +673,8 @@
 #define R92C_LSSI_PARAM_DATA_S	0
 #define R92C_LSSI_PARAM_ADDR_M	0x03f00000
 #define R92C_LSSI_PARAM_ADDR_S	20
+#define R88E_LSSI_PARAM_ADDR_M	0x0ff00000
+#define R88E_LSSI_PARAM_ADDR_S	20
 
 /* Bits for R92C_FPGA0_ANAPARAM2. */
 #define R92C_FPGA0_ANAPARAM2_CBW20	0x00000400
@@ -673,7 +707,8 @@
 #define R92C_USB_STRING			0xfe80
 
 /* Bits for R92C_USB_SPECIAL_OPTION. */
-#define R92C_USB_SPECIAL_OPTION_AGG_EN	0x08
+#define R92C_USB_SPECIAL_OPTION_AGG_EN		0x08
+#define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL	0x10
 
 /* Bits for R92C_USB_EP. */
 #define R92C_USB_EP_HQ_M	0x000f
@@ -731,6 +766,7 @@
 #define R92C_RF_CHNLBW_CHNL_M	0x003ff
 #define R92C_RF_CHNLBW_CHNL_S	0
 #define R92C_RF_CHNLBW_BW20	0x00400
+#define R88E_RF_CHNLBW_BW20	0x00c00
 #define R92C_RF_CHNLBW_LCSTART	0x08000
 
 
@@ -941,6 +977,26 @@ struct r92c_rx_cck {
 	uint8_t		agc_rpt;
 } __packed;
 
+struct r88e_rx_cck {
+	uint8_t		path_agc[2];
+	uint8_t		sig_qual;
+	uint8_t		agc_rpt;
+	uint8_t		rpt_b;
+	uint8_t 	reserved1;
+	uint8_t		noise_power;
+	uint8_t		path_cfotail[2];        
+	uint8_t		pcts_mask[2];   
+	uint8_t		stream_rxevm[2];        
+	uint8_t		path_rxsnr[2];
+	uint8_t		noise_power_db_lsb;
+	uint8_t		reserved2[3];
+	uint8_t		stream_csi[2];
+	uint8_t		stream_target_csi[2];
+	uint8_t		sig_evm;
+	uint8_t		reserved3;
+	uint8_t		reserved4;
+} __packed;
+
 /* Tx MAC descriptor. */
 struct r92c_tx_desc {
 	uint32_t	txdw0;
@@ -956,6 +1012,8 @@ struct r92c_tx_desc {
 	uint32_t	txdw1;
 #define R92C_TXDW1_MACID_M	0x0000001f
 #define R92C_TXDW1_MACID_S	0
+#define R88E_TXDW1_MACID_M	0x0000003f
+#define R88E_TXDW1_MACID_S	0
 #define R92C_TXDW1_AGGEN	0x00000020
 #define R92C_TXDW1_AGGBK	0x00000040
 #define R92C_TXDW1_QSEL_M	0x00001f00
@@ -973,6 +1031,8 @@ struct r92c_tx_desc {
 #define R92C_TXDW1_PKTOFF_S	26
 
 	uint32_t	txdw2;
+#define R88E_TXDW2_AGGBK	0x00010000
+
 	uint16_t	txdw3;
 	uint16_t	txdseq;
 
@@ -1122,10 +1182,16 @@ struct urtwn_softc {
 #define URTWN_DETACHED		0x02
 
 	u_int				chip;
-#define URTWN_CHIP_92C		0x01
-#define URTWN_CHIP_92C_1T2R	0x02
-#define URTWN_CHIP_UMC		0x04
-#define URTWN_CHIP_UMC_A_CUT	0x08
+#define	URTWN_CHIP_92C		0x01
+#define	URTWN_CHIP_92C_1T2R	0x02
+#define	URTWN_CHIP_UMC		0x04
+#define	URTWN_CHIP_UMC_A_CUT	0x08
+#define	URTWN_CHIP_88E		0x10
+
+	void				(*sc_rf_write)(struct urtwn_softc *,
+					    int, uint8_t, uint32_t);
+	int				(*sc_power_on)(struct urtwn_softc *);
+	int				(*sc_dma_init)(struct urtwn_softc *);
 
 	uint8_t				board_type;
 	uint8_t				regulatory;
@@ -1153,6 +1219,11 @@ struct urtwn_softc {
 	void				*fw_virtaddr;
 
 	struct r92c_rom			rom;
+	uint8_t				r88e_rom[512];
+	uint8_t				cck_tx_pwr[6];
+	uint8_t				ht40_tx_pwr[5];
+	int8_t				bw20_tx_pwr_diff;
+	int8_t				ofdm_tx_pwr_diff;
 	uint8_t				sc_bssid[IEEE80211_ADDR_LEN];
 		
 	struct callout			sc_watchdog_ch;
@@ -1190,7 +1261,31 @@ struct urtwn_softc {
 static const struct {
 	uint16_t	reg;
 	uint8_t		val;
-} rtl8192cu_mac[] = {
+} rtl8188eu_mac[] = {
+	{ 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a },
+	{ 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 },
+	{ 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 },
+	{ 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 },
+	{ 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 },
+	{ 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 },
+	{ 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 },
+	{ 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 },
+	{ 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff },
+	{ 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 },
+	{ 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f },
+	{ 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e },
+	{ 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e },
+	{ 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 },
+	{ 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a },
+	{ 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 },
+	{ 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a },
+	{ 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff },
+	{ 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff },
+	{ 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e },
+	{ 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 },
+	{ 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 },
+	{ 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 }
+}, rtl8192cu_mac[] = {
 	{ 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
 	{ 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
 	{ 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
@@ -1525,6 +1620,115 @@ static const struct urtwn_bb_prog rtl8188cu_bb_prog = {
 	rtl8188ce_agc_vals
 };
 
+/*
+ * RTL8188EU.
+ */
+static const uint16_t rtl8188eu_bb_regs[] = {
+	0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c,
+	0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c,
+	0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c,
+	0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c,
+	0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c,
+	0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04,
+	0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24,
+	0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 0xb2c,
+	0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c,
+	0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c,
+	0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c,
+	0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c,
+	0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c,
+	0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc,
+	0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc,
+	0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c,
+	0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c,
+	0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c,
+	0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00,
+	0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30,
+	0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50,
+	0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74,
+	0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4,
+	0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14, 0xf4c, 0xf00
+};
+
+static const uint32_t rtl8188eu_bb_vals[] = {
+	0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331,
+	0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110,
+	0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000,
+	0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000,
+	0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050,
+	0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002,
+	0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f,
+	0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000,
+	0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
+	0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40,
+	0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100,
+	0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c,
+	0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420,
+	0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b,
+	0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f,
+	0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000,
+	0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000,
+	0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932,
+	0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740,
+	0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43,
+	0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000,
+	0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68,
+	0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220,
+	0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d,
+	0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f,
+	0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800,
+	0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102,
+	0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014,
+	0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014,
+	0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014,
+	0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003,
+	0x00000000, 0x00000300
+};
+
+static const uint32_t rtl8188eu_agc_vals[] = {
+	0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001,
+	0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001,
+	0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001,
+	0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001,
+	0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001,
+	0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001,
+	0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001,
+	0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001,
+	0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001,
+	0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001,
+	0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001,
+	0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001,
+	0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001,
+	0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001,
+	0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001,
+	0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001,
+	0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001,
+	0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001,
+	0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001,
+	0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001,
+	0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001,
+	0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001,
+	0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001,
+	0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001,
+	0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001,
+	0x407d0001, 0x407e0001, 0x407f0001
+};
+
+static const struct urtwn_bb_prog rtl8188eu_bb_prog = {
+	nitems(rtl8188eu_bb_regs),
+	rtl8188eu_bb_regs,
+	rtl8188eu_bb_vals,
+	nitems(rtl8188eu_agc_vals),
+	rtl8188eu_agc_vals
+};
+
 /*
  * RTL8188RU.
  */
@@ -1788,6 +1992,47 @@ static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = {
 	}
 };
 
+/*
+ * RTL8188EU.
+ */
+static const uint8_t rtl8188eu_rf_regs[] = {
+	0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57,
+	0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8,
+	0xb9, 0xba, 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
+	0xc8, 0xc9, 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56,
+	0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18, 0x5a,
+	0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34,
+	0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b,
+	0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b,
+	0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 0xfe,
+	0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00
+};
+
+static const uint32_t rtl8188eu_rf_vals[] = {
+	0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060,
+	0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc,
+	0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001,
+	0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999,
+	0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0,
+	0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186,
+	0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07,
+	0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7,
+	0x054ee, 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159,
+	0x68200, 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0,
+	0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780,
+	0x722b0, 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080,
+	0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003,
+	0x00000, 0x00000, 0x00001, 0x80000, 0x33e60
+};
+
+static const struct urtwn_rf_prog rtl8188eu_rf_prog[] = {
+	{
+		nitems(rtl8188eu_rf_regs),
+		rtl8188eu_rf_regs,
+		rtl8188eu_rf_vals
+	}
+};
+
 /*
  * RTL8188RU.
  */
@@ -1827,6 +2072,10 @@ struct urtwn_txpwr {
 	uint8_t	pwr[3][28];
 };
 
+struct urtwn_r88e_txpwr {
+	uint8_t	pwr[6][28];
+};
+
 /*
  * Per RF chain/group/rate Tx gain values.
  */
@@ -1895,3 +2144,44 @@ static const struct urtwn_txpwr rtl8188ru_txagc[] = {
 	}
 	} }
 };
+
+static const struct urtwn_r88e_txpwr rtl8188eu_txagc[] = {
+	{ {	/* Chain 0. */
+	{	/* Group 0. */
+	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
+	},
+	{	/* Group 1. */
+	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
+	},
+	{	/* Group 2. */
+	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
+	},
+	{	/* Group 3. */
+	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
+	},
+	{	/* Group 4. */
+	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
+	},
+	{	/* Group 5. */
+	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
+	}
+	} }
+};
diff --git a/sys/modules/usb/urtwnfw/Makefile b/sys/modules/usb/urtwnfw/Makefile
index c5ae0d511832..611b4115bb5a 100644
--- a/sys/modules/usb/urtwnfw/Makefile
+++ b/sys/modules/usb/urtwnfw/Makefile
@@ -1,5 +1,5 @@
 # $FreeBSD$
 
-SUBDIR=	urtwnrtl8192cT urtwnrtl8192cU
+SUBDIR=	urtwnrtl8188eu urtwnrtl8192cT urtwnrtl8192cU
 
 .include <bsd.subdir.mk>
diff --git a/sys/modules/usb/urtwnfw/urtwnrtl8188eu/Makefile b/sys/modules/usb/urtwnfw/urtwnrtl8188eu/Makefile
new file mode 100644
index 000000000000..d3c974e9c03a
--- /dev/null
+++ b/sys/modules/usb/urtwnfw/urtwnrtl8188eu/Makefile
@@ -0,0 +1,6 @@
+# $FreeBSD$
+
+KMOD=	urtwn-rtl8188eufw
+IMG=	urtwn-rtl8188eufw
+
+.include <bsd.kmod.mk>