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Fix build for o32 kernels.

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The emulation of 'ld' and 'sd' instructions only works for ABIs that support
64-bit registers and the instructions 'ldl' and 'ldr' that operate on those
registers.

Reviewed by:	jmallett
This commit is contained in:
Neel Natu 2010-07-29 05:14:59 +00:00
parent 864ec37f39
commit 2a3232d9d6
1 changed files with 4 additions and 0 deletions
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4
sys/mips/mips/trap.c
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@ -1497,6 +1497,7 @@ mips_unaligned_load_store(struct trapframe *frame, int mode, register_t addr, re
reg[MIPS_INST_RT(inst)] = value;
return (MIPS_LW_ACCESS);
#if defined(__mips_n32) || defined(__mips_n64)
case OP_LD:
KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
ldl_macro(value, addr);
@ -1504,6 +1505,7 @@ mips_unaligned_load_store(struct trapframe *frame, int mode, register_t addr, re
ldr_macro(value, addr);
reg[MIPS_INST_RT(inst)] = value;
return (MIPS_LD_ACCESS);
#endif
case OP_SH:
KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
@ -1522,6 +1524,7 @@ mips_unaligned_load_store(struct trapframe *frame, int mode, register_t addr, re
swr_macro(value, addr);
return (MIPS_SW_ACCESS);
#if defined(__mips_n32) || defined(__mips_n64)
case OP_SD:
KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
value = reg[MIPS_INST_RT(inst)];
@ -1529,6 +1532,7 @@ mips_unaligned_load_store(struct trapframe *frame, int mode, register_t addr, re
addr += 7;
sdr_macro(value, addr);
return (MIPS_SD_ACCESS);
#endif
}
panic("%s: should not be reached.", __func__);
}