Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features.
Note AMD dropped SSE5 extensions in order to avoid ISA overlap with Intel AVX instructions. The SSE5 bit was recycled as XOP extended instruction bit, CVT16 was deprecated in favor of F16C (half-precision float conversion instructions for AVX), and the remaining FMA4 (4-operand FMA instructions) gained a separate CPUID bit. Replace non-existent references with today's CPUID specifications.
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Jung-uk Kim
parent
179efac924
commit
2b052e43be
@ -216,6 +216,14 @@ printcpuinfo(void)
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printf(" Family = %x", CPUID_TO_FAMILY(cpu_id));
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printf(" Model = %x", CPUID_TO_MODEL(cpu_id));
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printf(" Stepping = %u", cpu_id & CPUID_STEPPING);
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/*
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* AMD CPUID Specification
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* http://support.amd.com/us/Embedded_TechDocs/25481.pdf
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*
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* Intel Processor Identification and CPUID Instruction
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* http://www.intel.com/assets/pdf/appnote/241618.pdf
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*/
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if (cpu_high > 0) {
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/*
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@ -277,38 +285,29 @@ printcpuinfo(void)
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"\012SSSE3" /* SSSE3 */
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"\013CNXT-ID" /* L1 context ID available */
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"\014<b11>"
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"\015<b12>"
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"\015FMA" /* Fused Multiply Add */
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"\016CX16" /* CMPXCHG16B Instruction */
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"\017xTPR" /* Send Task Priority Messages*/
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"\020PDCM" /* Perf/Debug Capability MSR */
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"\021<b16>"
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"\022PCID" /* Process-context Identifiers */
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"\022PCID" /* Process-context Identifiers*/
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"\023DCA" /* Direct Cache Access */
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"\024SSE4.1"
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"\025SSE4.2"
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"\024SSE4.1" /* SSE 4.1 */
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"\025SSE4.2" /* SSE 4.2 */
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"\026x2APIC" /* xAPIC Extensions */
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"\027MOVBE"
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"\030POPCNT"
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"\031<b24>"
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"\032AESNI" /* AES Crypto*/
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"\033XSAVE"
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"\034OSXSAVE"
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"\035<b28>"
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"\036<b29>"
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"\027MOVBE" /* MOVBE Instruction */
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"\030POPCNT" /* POPCNT Instruction */
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"\031TSCDLT" /* TSC-Deadline Timer */
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"\032AESNI" /* AES Crypto */
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"\033XSAVE" /* XSAVE/XRSTOR States */
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"\034OSXSAVE" /* OS-Enabled State Management*/
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"\035AVX" /* Advanced Vector Extensions */
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"\036F16C" /* Half-precision conversions */
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"\037<b30>"
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"\040HV" /* Hypervisor */
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);
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}
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/*
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* AMD64 Architecture Programmer's Manual Volume 3:
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* General-Purpose and System Instructions
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
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*
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* IA-32 Intel Architecture Software Developer's Manual,
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* Volume 2A: Instruction Set Reference, A-M
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* ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
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*/
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if (amd_feature != 0) {
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printf("\n AMD Features=0x%b", amd_feature,
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"\020" /* in hex */
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@ -361,18 +360,18 @@ printcpuinfo(void)
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"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
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"\012OSVW" /* OS visible workaround */
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"\013IBS" /* Instruction based sampling */
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"\014SSE5" /* SSE5 */
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"\014XOP" /* XOP extended instructions */
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"\015SKINIT" /* SKINIT/STGI */
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"\016WDT" /* Watchdog timer */
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"\017<b14>"
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"\020<b15>"
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"\021<b16>"
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"\020LWP" /* Lightweight Profiling */
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"\021FMA4" /* 4-operand FMA instructions */
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"\022<b17>"
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"\023<b18>"
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"\024<b19>"
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"\024NodeId" /* NodeId MSR support */
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"\025<b20>"
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"\026<b21>"
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"\027<b22>"
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"\026TBM" /* Trailing Bit Manipulation */
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"\027Topology" /* Topology Extensions */
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"\030<b23>"
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"\031<b24>"
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"\032<b25>"
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@ -123,6 +123,7 @@
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#define CPUID2_TM2 0x00000100
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#define CPUID2_SSSE3 0x00000200
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#define CPUID2_CNXTID 0x00000400
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#define CPUID2_FMA 0x00001000
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#define CPUID2_CX16 0x00002000
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#define CPUID2_XTPR 0x00004000
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#define CPUID2_PDCM 0x00008000
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@ -133,7 +134,12 @@
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#define CPUID2_X2APIC 0x00200000
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#define CPUID2_MOVBE 0x00400000
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#define CPUID2_POPCNT 0x00800000
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#define CPUID2_TSCDLT 0x01000000
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#define CPUID2_AESNI 0x02000000
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#define CPUID2_XSAVE 0x04000000
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#define CPUID2_OSXSAVE 0x08000000
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#define CPUID2_AVX 0x10000000
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#define CPUID2_F16C 0x20000000
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#define CPUID2_HV 0x80000000
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/*
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@ -170,9 +176,14 @@
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#define AMDID2_PREFETCH 0x00000100
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#define AMDID2_OSVW 0x00000200
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#define AMDID2_IBS 0x00000400
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#define AMDID2_SSE5 0x00000800
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#define AMDID2_XOP 0x00000800
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#define AMDID2_SKINIT 0x00001000
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#define AMDID2_WDT 0x00002000
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#define AMDID2_LWP 0x00008000
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#define AMDID2_FMA4 0x00010000
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#define AMDID2_NODE_ID 0x00080000
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#define AMDID2_TBM 0x00200000
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#define AMDID2_TOPOLOGY 0x00400000
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/*
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* CPUID instruction 1 eax info
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@ -693,6 +693,13 @@ printcpuinfo(void)
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printf(" Stepping = %u", cpu_id & CPUID_STEPPING);
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if (cpu_vendor_id == CPU_VENDOR_CYRIX)
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printf("\n DIR=0x%04x", cyrix_did);
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/*
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* AMD CPUID Specification
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* http://support.amd.com/us/Embedded_TechDocs/25481.pdf
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*
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* Intel Processor Identification and CPUID Instruction
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* http://www.intel.com/assets/pdf/appnote/241618.pdf
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*/
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if (cpu_high > 0) {
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/*
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@ -754,38 +761,29 @@ printcpuinfo(void)
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"\012SSSE3" /* SSSE3 */
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"\013CNXT-ID" /* L1 context ID available */
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"\014<b11>"
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"\015<b12>"
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"\015FMA" /* Fused Multiply Add */
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"\016CX16" /* CMPXCHG16B Instruction */
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"\017xTPR" /* Send Task Priority Messages*/
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"\020PDCM" /* Perf/Debug Capability MSR */
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"\021<b16>"
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"\022PCID" /* Process-context Identifiers */
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"\022PCID" /* Process-context Identifiers*/
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"\023DCA" /* Direct Cache Access */
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"\024SSE4.1"
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"\025SSE4.2"
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"\024SSE4.1" /* SSE 4.1 */
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"\025SSE4.2" /* SSE 4.2 */
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"\026x2APIC" /* xAPIC Extensions */
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"\027MOVBE"
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"\030POPCNT"
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"\031<b24>"
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"\032AESNI" /* AES Crypto*/
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"\033XSAVE"
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"\034OSXSAVE"
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"\035<b28>"
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"\036<b29>"
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"\027MOVBE" /* MOVBE Instruction */
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"\030POPCNT" /* POPCNT Instruction */
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"\031TSCDLT" /* TSC-Deadline Timer */
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"\032AESNI" /* AES Crypto */
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"\033XSAVE" /* XSAVE/XRSTOR States */
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"\034OSXSAVE" /* OS-Enabled State Management*/
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"\035AVX" /* Advanced Vector Extensions */
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"\036F16C" /* Half-precision conversions */
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"\037<b30>"
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"\040HV" /* Hypervisor */
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);
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}
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/*
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* AMD64 Architecture Programmer's Manual Volume 3:
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* General-Purpose and System Instructions
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
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*
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* IA-32 Intel Architecture Software Developer's Manual,
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* Volume 2A: Instruction Set Reference, A-M
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* ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
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*/
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if (amd_feature != 0) {
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printf("\n AMD Features=0x%b", amd_feature,
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"\020" /* in hex */
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@ -838,18 +836,18 @@ printcpuinfo(void)
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"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
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"\012OSVW" /* OS visible workaround */
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"\013IBS" /* Instruction based sampling */
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"\014SSE5" /* SSE5 */
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"\014XOP" /* XOP extended instructions */
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"\015SKINIT" /* SKINIT/STGI */
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"\016WDT" /* Watchdog timer */
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"\017<b14>"
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"\020<b15>"
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"\021<b16>"
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"\020LWP" /* Lightweight Profiling */
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"\021FMA4" /* 4-operand FMA instructions */
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"\022<b17>"
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"\023<b18>"
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"\024<b19>"
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"\024NodeId" /* NodeId MSR support */
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"\025<b20>"
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"\026<b21>"
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"\027<b22>"
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"\026TBM" /* Trailing Bit Manipulation */
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"\027Topology" /* Topology Extensions */
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"\030<b23>"
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"\031<b24>"
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"\032<b25>"
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@ -120,6 +120,7 @@
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#define CPUID2_TM2 0x00000100
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#define CPUID2_SSSE3 0x00000200
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#define CPUID2_CNXTID 0x00000400
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#define CPUID2_FMA 0x00001000
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#define CPUID2_CX16 0x00002000
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#define CPUID2_XTPR 0x00004000
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#define CPUID2_PDCM 0x00008000
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@ -130,7 +131,12 @@
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#define CPUID2_X2APIC 0x00200000
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#define CPUID2_MOVBE 0x00400000
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#define CPUID2_POPCNT 0x00800000
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#define CPUID2_TSCDLT 0x01000000
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#define CPUID2_AESNI 0x02000000
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#define CPUID2_XSAVE 0x04000000
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#define CPUID2_OSXSAVE 0x08000000
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#define CPUID2_AVX 0x10000000
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#define CPUID2_F16C 0x20000000
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#define CPUID2_HV 0x80000000
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/*
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@ -167,9 +173,14 @@
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#define AMDID2_PREFETCH 0x00000100
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#define AMDID2_OSVW 0x00000200
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#define AMDID2_IBS 0x00000400
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#define AMDID2_SSE5 0x00000800
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#define AMDID2_XOP 0x00000800
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#define AMDID2_SKINIT 0x00001000
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#define AMDID2_WDT 0x00002000
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#define AMDID2_LWP 0x00008000
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#define AMDID2_FMA4 0x00010000
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#define AMDID2_NODE_ID 0x00080000
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#define AMDID2_TBM 0x00200000
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#define AMDID2_TOPOLOGY 0x00400000
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/*
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* CPUID instruction 1 eax info
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