- Re-write OF_decode_addr() with a bus-neutral approach, adding support
for nodes hanging off of Central (untested), FireHose (untested) and PCI (tested) busses. - Add an additional parameter to OF_decode_addr() which specifies the index of the register bank to decode. These should allow to eventually add support for the Z8530 hanging off of FireHose to uart(4) and to write support for PCI-based graphics adapters. Suggested by: tmm (back in '03)
This commit is contained in:
Marius Strobl
parent
61e2f26526
commit
2b2250b149
@ -200,7 +200,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
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}
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if (input == -1)
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return (ENXIO);
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error = OF_decode_addr(input, &space, &addr);
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error = OF_decode_addr(input, 0, &space, &addr);
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if (error)
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return (error);
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@ -30,10 +30,9 @@
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#include <sys/bus.h>
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int OF_decode_addr(phandle_t, int *, bus_addr_t *);
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int OF_decode_addr(phandle_t, int, int *, bus_addr_t *);
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void OF_getetheraddr(device_t, u_char *);
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void cpu_shutdown(void *);
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void openfirmware_exit(void *);
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#endif /* _MACHINE_OFW_MACHDEP_H_ */
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@ -1,5 +1,6 @@
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/*-
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* Copyright (c) 2001 by Thomas Moestl <tmm@FreeBSD.org>.
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* Copyright (c) 2005 by Marius Strobl <marius@FreeBSD.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -36,17 +37,13 @@
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#include <net/ethernet.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/bus.h>
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#include <machine/idprom.h>
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#include <machine/ofw_bus.h>
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#include <machine/ofw_machdep.h>
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#include <machine/ofw_upa.h>
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#include <machine/resource.h>
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#include <sparc64/pci/ofw_pci.h>
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#include <sparc64/isa/ofw_isa.h>
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#include <sparc64/sbus/ofw_sbus.h>
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void
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OF_getetheraddr(device_t dev, u_char *addr)
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@ -71,105 +68,199 @@ OF_getetheraddr(device_t dev, u_char *addr)
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bcopy(&idp.id_ether, addr, ETHER_ADDR_LEN);
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}
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static __inline uint32_t
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phys_hi_mask_space(const char *bus, uint32_t phys_hi)
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{
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uint32_t space;
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space = phys_hi;
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if (strcmp(bus, "ebus") == 0 || strcmp(bus, "isa") == 0)
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space &= 0x1;
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else if (strcmp(bus, "pci") == 0)
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space &= OFW_PCI_PHYS_HI_SPACEMASK;
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/* The phys.hi cells of the other busses only contain space bits. */
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return (space);
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}
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/*
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* Return the physical address and the bus space to use for a node
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* referenced by its package handle and the index of the register bank
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* to decode. Intended to be used to together with sparc64_fake_bustag()
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* by console drivers in early boot only.
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* Works by mapping the address of the node's bank given in the address
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* space of its parent upward in the device tree at each bridge along the
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* path.
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* Currently only really deals with max. 64-bit addresses, i.e. addresses
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* consisting of max. 2 phys cells (phys.hi and phys.lo). If we encounter
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* a 3 phys cells address (as with PCI addresses) we assume phys.hi can
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* be ignored except for the space bits (generally contained in phys.hi)
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* and treat phys.mid as phys.hi.
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*/
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int
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OF_decode_addr(phandle_t node, int *space, bus_addr_t *addr)
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OF_decode_addr(phandle_t node, int bank, int *space, bus_addr_t *addr)
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{
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char name[32];
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union {
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struct isa_ranges isa[4];
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struct sbus_ranges sbus[8];
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struct upa_ranges upa[4];
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} range;
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union {
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struct isa_regs isa;
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struct sbus_regs sbus;
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} reg;
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phandle_t bus, pbus;
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u_long child, dummy, phys;
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int cs, i, rsz, type;
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uint64_t cend, cstart, end, phys, sz, start;
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pcell_t addrc, szc, paddrc;
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phandle_t bus, lbus, pbus;
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uint32_t banks[10 * 5]; /* 10 PCI banks */
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uint32_t cspace, spc;
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int i, j, nbank;
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/*
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* In general the addresses are contained in the "reg" property
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* of a node. The first address in the "reg" property of a PCI
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* node however is the address of its configuration registers in
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* the configuration space of the host bridge. Additional entries
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* denote the memory and I/O addresses. For relocatable addresses
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* the "reg" property contains the BAR, for non-relocatable
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* addresses it contains the absolute PCI address. The PCI-only
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* "assigned-addresses" property however always contains the
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* absolute PCI addresses.
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* The "assigned-addresses" and "reg" properties are arrays of
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* address structures consisting of #address-cells 32-bit phys
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* cells and #size-cells 32-bit size cells. If a parent lacks
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* the "#address-cells" or "#size-cells" property the default
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* for #address-cells to use is 2 and for #size-cells 1.
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*/
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bus = OF_parent(node);
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if (bus == 0)
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return (ENXIO);
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if (OF_getprop(bus, "name", name, sizeof(name)) == -1)
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return (ENXIO);
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name[sizeof(name) - 1] = '\0';
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if (strcmp(name, "ebus") == 0 || strcmp(name, "isa") == 0) {
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if (OF_getprop(node, "reg", ®.isa, sizeof(reg.isa)) == -1)
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if (OF_getprop(bus, "#address-cells", &addrc, sizeof(addrc)) == -1)
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addrc = 2;
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if (OF_getprop(bus, "#size-cells", &szc, sizeof(szc)) == -1)
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szc = 1;
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if (szc > 2)
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return (ENXIO);
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if (strcmp(name, "pci") == 0) {
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if (addrc > 3)
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return (ENXIO);
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rsz = OF_getprop(bus, "ranges", range.isa, sizeof(range.isa));
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if (rsz == -1)
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nbank = OF_getprop(node, "assigned-addresses", &banks,
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sizeof(banks));
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} else {
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if (addrc > 2)
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return (ENXIO);
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phys = ISA_REG_PHYS(®.isa);
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dummy = phys + 1;
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type = ofw_isa_range_map(range.isa, rsz / sizeof(*range.isa),
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&phys, &dummy, NULL);
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if (type == SYS_RES_MEMORY) {
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cs = PCI_CS_MEM32;
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*space = PCI_MEMORY_BUS_SPACE;
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} else {
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cs = PCI_CS_IO;
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*space = PCI_IO_BUS_SPACE;
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}
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nbank = OF_getprop(node, "reg", &banks, sizeof(banks));
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}
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if (nbank == -1)
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return (ENXIO);
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nbank /= sizeof(banks[0]) * (addrc + szc);
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if (bank < 0 || bank > nbank - 1)
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return (ENXIO);
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phys = 0;
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for (i = 0; i < MIN(2, addrc); i++)
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phys |= (uint64_t)banks[(addrc + szc) * bank + addrc - 2 + i] <<
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32 * (MIN(2, addrc) - i - 1);
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sz = 0;
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for (i = 0; i < szc; i++)
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sz |= (uint64_t)banks[(addrc + szc) * bank + addrc + i] <<
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32 * (szc - i - 1);
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start = phys;
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end = phys + sz - 1;
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spc = phys_hi_mask_space(name, banks[(addrc + szc) * bank]);
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/* Find the topmost PCI node (the host bridge) */
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while (1) {
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pbus = OF_parent(bus);
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if (pbus == 0)
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return (ENXIO);
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/*
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* Map upward in the device tree at every bridge we encounter
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* using their "ranges" properties.
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* The "ranges" property of a bridge is an array of a structure
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* consisting of that bridge's #address-cells 32-bit child-phys
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* cells, its parent bridge #address-cells 32-bit parent-phys
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* cells and that bridge's #size-cells 32-bit size cells.
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* If a bridge doesn't have a "ranges" property no mapping is
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* necessary at that bridge.
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*/
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cspace = 0;
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lbus = bus;
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while ((pbus = OF_parent(bus)) != 0) {
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if (OF_getprop(pbus, "#address-cells", &paddrc,
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sizeof(paddrc)) == -1)
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paddrc = 2;
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if (paddrc > 3)
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return (ENXIO);
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nbank = OF_getprop(bus, "ranges", &banks, sizeof(banks));
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if (nbank == -1) {
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if (OF_getprop(pbus, "name", name, sizeof(name)) == -1)
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return (ENXIO);
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name[sizeof(name) - 1] = '\0';
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if (strcmp(name, "pci") != 0)
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break;
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bus = pbus;
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goto skip;
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}
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/* There wasn't a PCI bridge. */
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if (bus == OF_parent(node))
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return (ENXIO);
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/* Make sure we reached the UPA/PCI node. */
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if (OF_getprop(pbus, "device_type", name, sizeof(name)) == -1)
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return (ENXIO);
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name[sizeof(name) - 1] = '\0';
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if (strcmp(name, "upa") != 0)
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return (ENXIO);
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rsz = OF_getprop(bus, "ranges", range.upa, sizeof(range.upa));
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if (rsz == -1)
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return (ENXIO);
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for (i = 0; i < (rsz / sizeof(range.upa[0])); i++) {
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child = UPA_RANGE_CHILD(&range.upa[i]);
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if (UPA_RANGE_CS(&range.upa[i]) == cs &&
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phys >= child &&
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phys - child < UPA_RANGE_SIZE(&range.upa[i])) {
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*addr = UPA_RANGE_PHYS(&range.upa[i]) + phys;
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return (0);
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}
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if (lbus != bus) {
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if (OF_getprop(bus, "#size-cells", &szc,
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sizeof(szc)) == -1)
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szc = 1;
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if (szc > 2)
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return (ENXIO);
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}
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} else if (strcmp(name, "sbus") == 0) {
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if (OF_getprop(node, "reg", ®.sbus, sizeof(reg.sbus)) == -1)
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return (ENXIO);
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rsz = OF_getprop(bus, "ranges", range.sbus,
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sizeof(range.sbus));
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if (rsz == -1)
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return (ENXIO);
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for (i = 0; i < (rsz / sizeof(range.sbus[0])); i++) {
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if (reg.sbus.sbr_slot != range.sbus[i].cspace)
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nbank /= sizeof(banks[0]) * (addrc + paddrc + szc);
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for (i = 0; i < nbank; i++) {
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cspace = phys_hi_mask_space(name,
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banks[(addrc + paddrc + szc) * i]);
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if (cspace != spc)
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continue;
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if (reg.sbus.sbr_offset < range.sbus[i].coffset ||
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reg.sbus.sbr_offset >= range.sbus[i].coffset +
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range.sbus[i].size)
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phys = 0;
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for (j = 0; j < MIN(2, addrc); j++)
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phys |= (uint64_t)banks[
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(addrc + paddrc + szc) * i +
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addrc - 2 + j] <<
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32 * (MIN(2, addrc) - j - 1);
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sz = 0;
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for (j = 0; j < szc; j++)
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sz |= (uint64_t)banks[
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(addrc + paddrc + szc) * i + addrc +
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paddrc + j] <<
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32 * (szc - j - 1);
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cstart = phys;
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cend = phys + sz - 1;
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if (start < cstart || start > cend)
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continue;
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/* Found it... */
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phys = range.sbus[i].poffset |
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((bus_addr_t)range.sbus[i].pspace << 32);
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phys += reg.sbus.sbr_offset - range.sbus[i].coffset;
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*addr = phys;
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*space = SBUS_BUS_SPACE;
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if (end < cstart || end > cend)
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return (ENXIO);
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phys = 0;
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for (j = 0; j < MIN(2, paddrc); j++)
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phys |= (uint64_t)banks[
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(addrc + paddrc + szc) * i + addrc +
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paddrc - 2 + j] <<
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32 * (MIN(2, paddrc) - j - 1);
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start += phys - cstart;
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end += phys - cstart;
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if (OF_getprop(pbus, "name", name, sizeof(name)) == -1)
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return (ENXIO);
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name[sizeof(name) - 1] = '\0';
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spc = phys_hi_mask_space(name,
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banks[(addrc + paddrc + szc) * i + addrc]);
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break;
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}
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if (i == nbank)
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return (ENXIO);
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skip:
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addrc = paddrc;
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lbus = bus;
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bus = pbus;
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}
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/* Done with mapping. Return the bus space as used by FreeBSD. */
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*addr = start;
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if (OF_getprop(lbus, "name", name, sizeof(name)) == -1)
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return (ENXIO);
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name[sizeof(name) - 1] = '\0';
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if (strcmp(name, "central") == 0) {
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*space = UPA_BUS_SPACE;
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return (0);
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} else if (strcmp(name, "pci") == 0) {
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switch (cspace) {
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case OFW_PCI_PHYS_HI_SPACE_IO:
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*space = PCI_IO_BUS_SPACE;
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return (0);
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case OFW_PCI_PHYS_HI_SPACE_MEM32:
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*space = PCI_MEMORY_BUS_SPACE;
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return (0);
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}
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} else if (strcmp(name, "sbus") == 0) {
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*space = SBUS_BUS_SPACE;
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return (0);
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}
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return (ENXIO);
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}
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