Fixed to probe extended memory for over 256M or under 64M.
Submitted by: chi@bd.mbn.or.jp (Chiharu Shibata)
This commit is contained in:
parent
49c57093b7
commit
2b60363d7f
@ -1400,21 +1400,22 @@ sdtossd(sd, ssd)
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* Total memory size may be set by the kernel environment variable
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* hw.physmem or the compile-time define MAXMEM.
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*/
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#ifdef PC98
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static void
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getmemsize_pc98(int first)
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getmemsize(int first)
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{
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u_int biosbasemem, biosextmem;
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u_int pagesinbase, pagesinext;
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int pa_indx;
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int pg_n;
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int speculative_mprobe;
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#if NNPX > 0
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int msize;
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#endif
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unsigned under16;
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vm_offset_t target_page;
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pc98_getmemsize();
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biosbasemem = 640; /* 640KB */
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biosextmem = (Maxmem * PAGE_SIZE - 0x100000)/1024; /* extent memory */
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pc98_getmemsize(&biosbasemem, &biosextmem, &under16);
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#ifdef SMP
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/* make hole for AP bootstrap code */
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@ -1422,9 +1423,10 @@ getmemsize_pc98(int first)
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#else
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pagesinbase = biosbasemem * 1024 / PAGE_SIZE;
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#endif
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pagesinext = biosextmem * 1024 / PAGE_SIZE;
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Maxmem_under16M = under16 * 1024 / PAGE_SIZE;
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/*
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* Maxmem isn't the "maximum memory", it's one larger than the
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* highest page of the physical address space. It should be
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@ -1440,14 +1442,7 @@ getmemsize_pc98(int first)
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* memory probe.
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*/
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if (Maxmem >= 0x4000)
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#ifdef PC98
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{
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Maxmem = 0x4000; /* XXX */
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speculative_mprobe = TRUE;
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}
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#else
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speculative_mprobe = TRUE;
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#endif
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else
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speculative_mprobe = FALSE;
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@ -1491,36 +1486,111 @@ getmemsize_pc98(int first)
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pa_indx++;
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}
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/* XXX - some of EPSON machines can't use PG_N */
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pg_n = PG_N;
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if (pc98_machine_type & M_EPSON_PC98) {
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switch (epson_machine_id) {
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#ifdef WB_CACHE
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default:
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#endif
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case 0x34: /* PC-486HX */
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case 0x35: /* PC-486HG */
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case 0x3B: /* PC-486HA */
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pg_n = 0;
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break;
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}
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}
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speculative_mprobe = FALSE;
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#ifdef notdef /* XXX - see below */
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/*
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* Certain 'CPU accelerator' supports over 16MB memory on the machines
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* whose BIOS doesn't store true size.
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* To support this, we don't trust BIOS values if Maxmem < 16MB (0x1000
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* pages) - which is the largest amount that the OLD PC-98 can report.
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*
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* OK: PC-9801NS/R(9.6M)
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* OK: PC-9801DA(5.6M)+EUD-H(32M)+Cyrix 5x86
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* OK: PC-9821Ap(14.6M)+EUA-T(8M)+Cyrix 5x86-100
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* NG: PC-9821Ap(14.6M)+EUA-T(8M)+AMD DX4-100 -> freeze
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*/
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if (Maxmem < 0x1000) {
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int tmp, page_bad;
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page_bad = FALSE;
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/*
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* For Max14.6MB machines, the 0x10f0 page is same as 0x00f0,
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* which is BIOS ROM, by overlapping.
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* So, we check that page's ability of writing.
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*/
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target_page = ptoa(0x10f0);
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/*
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* map page into kernel: valid, read/write, non-cacheable
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*/
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*(int *)CMAP1 = PG_V | PG_RW | pg_n | target_page;
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invltlb();
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tmp = *(int *)CADDR1;
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/*
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* Test for alternating 1's and 0's
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*/
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*(volatile int *)CADDR1 = 0xaaaaaaaa;
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if (*(volatile int *)CADDR1 != 0xaaaaaaaa)
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page_bad = TRUE;
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/*
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* Test for alternating 0's and 1's
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*/
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*(volatile int *)CADDR1 = 0x55555555;
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if (*(volatile int *)CADDR1 != 0x55555555)
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page_bad = TRUE;
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/*
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* Test for all 1's
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*/
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*(volatile int *)CADDR1 = 0xffffffff;
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if (*(volatile int *)CADDR1 != 0xffffffff)
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page_bad = TRUE;
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/*
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* Test for all 0's
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*/
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*(volatile int *)CADDR1 = 0x0;
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if (*(volatile int *)CADDR1 != 0x0) {
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/*
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* test of page failed
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*/
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page_bad = TRUE;
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}
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/*
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* Restore original value.
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*/
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*(int *)CADDR1 = tmp;
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/*
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* Adjust Maxmem if valid/good page.
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*/
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if (page_bad == FALSE) {
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/* '+ 2' is needed to make speculative_mprobe sure */
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Maxmem = 0x1000 + 2;
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speculative_mprobe = TRUE;
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}
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}
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#endif
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for (target_page = avail_start; target_page < ptoa(Maxmem); target_page += PAGE_SIZE) {
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int tmp, page_bad;
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page_bad = FALSE;
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/* skip system area */
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if (target_page>=ptoa(Maxmem_under16M) &&
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if (target_page >= ptoa(Maxmem_under16M) &&
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target_page < ptoa(4096))
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continue;
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/*
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* map page into kernel: valid, read/write, non-cacheable
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*/
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if (pc98_machine_type & M_EPSON_PC98) {
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switch (epson_machine_id) {
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case 0x34: /* PC-486HX */
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case 0x35: /* PC-486HG */
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case 0x3B: /* PC-486HA */
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*(int *)CMAP1 = PG_V | PG_RW | target_page;
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break;
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default:
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#ifdef WB_CACHE
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*(int *)CMAP1 = PG_V | PG_RW | target_page;
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#else
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*(int *)CMAP1 = PG_V | PG_RW | PG_N | target_page;
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#endif
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break;
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}
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} else {
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*(int *)CMAP1 = PG_V | PG_RW | PG_N | target_page;
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}
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*(int *)CMAP1 = PG_V | PG_RW | pg_n | target_page;
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invltlb();
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tmp = *(int *)CADDR1;
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@ -1578,7 +1648,7 @@ getmemsize_pc98(int first)
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if (phys_avail[pa_indx] == target_page) {
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phys_avail[pa_indx] += PAGE_SIZE;
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if (speculative_mprobe == TRUE &&
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phys_avail[pa_indx] >= (64*1024*1024))
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phys_avail[pa_indx] >= (16*1024*1024))
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Maxmem++;
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} else {
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pa_indx++;
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@ -1617,8 +1687,7 @@ getmemsize_pc98(int first)
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avail_end = phys_avail[pa_indx];
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}
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#ifndef PC98
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#else
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static void
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getmemsize(int first)
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{
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@ -2181,11 +2250,7 @@ init386(first)
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dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
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vm86_initialize();
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#ifdef PC98
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getmemsize_pc98(first);
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#else
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getmemsize(first);
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#endif
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/* now running on new page tables, configured,and u/iom is accessible */
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/* Map the message buffer. */
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@ -1400,21 +1400,22 @@ sdtossd(sd, ssd)
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* Total memory size may be set by the kernel environment variable
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* hw.physmem or the compile-time define MAXMEM.
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*/
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#ifdef PC98
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static void
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getmemsize_pc98(int first)
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getmemsize(int first)
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{
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u_int biosbasemem, biosextmem;
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u_int pagesinbase, pagesinext;
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int pa_indx;
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int pg_n;
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int speculative_mprobe;
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#if NNPX > 0
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int msize;
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#endif
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unsigned under16;
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vm_offset_t target_page;
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pc98_getmemsize();
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biosbasemem = 640; /* 640KB */
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biosextmem = (Maxmem * PAGE_SIZE - 0x100000)/1024; /* extent memory */
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pc98_getmemsize(&biosbasemem, &biosextmem, &under16);
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#ifdef SMP
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/* make hole for AP bootstrap code */
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@ -1422,9 +1423,10 @@ getmemsize_pc98(int first)
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#else
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pagesinbase = biosbasemem * 1024 / PAGE_SIZE;
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#endif
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pagesinext = biosextmem * 1024 / PAGE_SIZE;
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Maxmem_under16M = under16 * 1024 / PAGE_SIZE;
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/*
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* Maxmem isn't the "maximum memory", it's one larger than the
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* highest page of the physical address space. It should be
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@ -1440,14 +1442,7 @@ getmemsize_pc98(int first)
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* memory probe.
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*/
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if (Maxmem >= 0x4000)
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#ifdef PC98
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{
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Maxmem = 0x4000; /* XXX */
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speculative_mprobe = TRUE;
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}
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#else
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speculative_mprobe = TRUE;
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#endif
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else
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speculative_mprobe = FALSE;
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@ -1491,36 +1486,111 @@ getmemsize_pc98(int first)
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pa_indx++;
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}
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/* XXX - some of EPSON machines can't use PG_N */
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pg_n = PG_N;
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if (pc98_machine_type & M_EPSON_PC98) {
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switch (epson_machine_id) {
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#ifdef WB_CACHE
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default:
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#endif
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case 0x34: /* PC-486HX */
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case 0x35: /* PC-486HG */
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case 0x3B: /* PC-486HA */
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pg_n = 0;
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break;
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}
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}
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speculative_mprobe = FALSE;
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#ifdef notdef /* XXX - see below */
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/*
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* Certain 'CPU accelerator' supports over 16MB memory on the machines
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* whose BIOS doesn't store true size.
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* To support this, we don't trust BIOS values if Maxmem < 16MB (0x1000
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* pages) - which is the largest amount that the OLD PC-98 can report.
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*
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* OK: PC-9801NS/R(9.6M)
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* OK: PC-9801DA(5.6M)+EUD-H(32M)+Cyrix 5x86
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* OK: PC-9821Ap(14.6M)+EUA-T(8M)+Cyrix 5x86-100
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* NG: PC-9821Ap(14.6M)+EUA-T(8M)+AMD DX4-100 -> freeze
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*/
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if (Maxmem < 0x1000) {
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int tmp, page_bad;
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page_bad = FALSE;
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/*
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* For Max14.6MB machines, the 0x10f0 page is same as 0x00f0,
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* which is BIOS ROM, by overlapping.
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* So, we check that page's ability of writing.
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*/
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target_page = ptoa(0x10f0);
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/*
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* map page into kernel: valid, read/write, non-cacheable
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*/
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*(int *)CMAP1 = PG_V | PG_RW | pg_n | target_page;
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invltlb();
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tmp = *(int *)CADDR1;
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/*
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* Test for alternating 1's and 0's
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*/
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*(volatile int *)CADDR1 = 0xaaaaaaaa;
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if (*(volatile int *)CADDR1 != 0xaaaaaaaa)
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page_bad = TRUE;
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/*
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* Test for alternating 0's and 1's
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*/
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*(volatile int *)CADDR1 = 0x55555555;
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if (*(volatile int *)CADDR1 != 0x55555555)
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page_bad = TRUE;
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/*
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* Test for all 1's
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*/
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*(volatile int *)CADDR1 = 0xffffffff;
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if (*(volatile int *)CADDR1 != 0xffffffff)
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page_bad = TRUE;
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/*
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* Test for all 0's
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*/
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*(volatile int *)CADDR1 = 0x0;
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if (*(volatile int *)CADDR1 != 0x0) {
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/*
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* test of page failed
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*/
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page_bad = TRUE;
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}
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/*
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* Restore original value.
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*/
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*(int *)CADDR1 = tmp;
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/*
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* Adjust Maxmem if valid/good page.
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*/
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if (page_bad == FALSE) {
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/* '+ 2' is needed to make speculative_mprobe sure */
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Maxmem = 0x1000 + 2;
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speculative_mprobe = TRUE;
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}
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}
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#endif
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for (target_page = avail_start; target_page < ptoa(Maxmem); target_page += PAGE_SIZE) {
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int tmp, page_bad;
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page_bad = FALSE;
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/* skip system area */
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if (target_page>=ptoa(Maxmem_under16M) &&
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if (target_page >= ptoa(Maxmem_under16M) &&
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target_page < ptoa(4096))
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continue;
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/*
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* map page into kernel: valid, read/write, non-cacheable
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*/
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if (pc98_machine_type & M_EPSON_PC98) {
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switch (epson_machine_id) {
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case 0x34: /* PC-486HX */
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case 0x35: /* PC-486HG */
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case 0x3B: /* PC-486HA */
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*(int *)CMAP1 = PG_V | PG_RW | target_page;
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break;
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default:
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#ifdef WB_CACHE
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*(int *)CMAP1 = PG_V | PG_RW | target_page;
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#else
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*(int *)CMAP1 = PG_V | PG_RW | PG_N | target_page;
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#endif
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break;
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}
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} else {
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*(int *)CMAP1 = PG_V | PG_RW | PG_N | target_page;
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}
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*(int *)CMAP1 = PG_V | PG_RW | pg_n | target_page;
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invltlb();
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tmp = *(int *)CADDR1;
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@ -1578,7 +1648,7 @@ getmemsize_pc98(int first)
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if (phys_avail[pa_indx] == target_page) {
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phys_avail[pa_indx] += PAGE_SIZE;
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if (speculative_mprobe == TRUE &&
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phys_avail[pa_indx] >= (64*1024*1024))
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phys_avail[pa_indx] >= (16*1024*1024))
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Maxmem++;
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} else {
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pa_indx++;
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@ -1617,8 +1687,7 @@ getmemsize_pc98(int first)
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avail_end = phys_avail[pa_indx];
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}
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#ifndef PC98
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#else
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static void
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getmemsize(int first)
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{
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@ -2181,11 +2250,7 @@ init386(first)
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dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
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vm86_initialize();
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#ifdef PC98
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getmemsize_pc98(first);
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#else
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getmemsize(first);
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#endif
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/* now running on new page tables, configured,and u/iom is accessible */
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/* Map the message buffer. */
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@ -41,13 +41,6 @@
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#include <pc98/pc98/pc98_machdep.h>
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extern int Maxmem;
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extern int Maxmem_under16M;
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#ifdef notyet
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static void init_cpu_accel_mem __P((void));
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#endif
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/*
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* Initialize DMA controller
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*/
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@ -74,130 +67,50 @@ static void init_epson_memwin __P((void));
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static void
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init_epson_memwin(void)
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{
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/* Disable 15MB-16MB caching. */
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switch (epson_machine_id) {
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case 0x34: /* PC486HX */
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case 0x35: /* PC486HG */
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case 0x3B: /* PC486HA */
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/* Cache control start. */
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outb(0x43f, 0x42);
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outw(0xc40, 0x0033);
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if (pc98_machine_type & M_EPSON_PC98) {
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if (Maxmem > 3840) {
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if (Maxmem == Maxmem_under16M) {
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Maxmem = 3840;
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Maxmem_under16M = 3840;
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} else if (Maxmem_under16M > 3840) {
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Maxmem_under16M = 3840;
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}
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}
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/* Disable 0xF00000-0xFFFFFF. */
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outb(0xc48, 0x49);
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outb(0xc4c, 0x00);
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outb(0xc48, 0x48);
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outb(0xc4c, 0xf0);
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outb(0xc48, 0x4d);
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outb(0xc4c, 0x00);
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outb(0xc48, 0x4c);
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outb(0xc4c, 0xff);
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outb(0xc48, 0x4f);
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outb(0xc4c, 0x00);
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/* Disable 15MB-16MB caching. */
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switch (epson_machine_id) {
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case 0x34: /* PC486HX */
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case 0x35: /* PC486HG */
|
||||
case 0x3B: /* PC486HA */
|
||||
/* Cache control start. */
|
||||
outb(0x43f, 0x42);
|
||||
outw(0xc40, 0x0033);
|
||||
/* Cache control end. */
|
||||
outb(0x43f, 0x40);
|
||||
break;
|
||||
|
||||
/* Disable 0xF00000-0xFFFFFF. */
|
||||
outb(0xc48, 0x49);
|
||||
outb(0xc4c, 0x00);
|
||||
outb(0xc48, 0x48);
|
||||
outb(0xc4c, 0xf0);
|
||||
outb(0xc48, 0x4d);
|
||||
outb(0xc4c, 0x00);
|
||||
outb(0xc48, 0x4c);
|
||||
outb(0xc4c, 0xff);
|
||||
outb(0xc48, 0x4f);
|
||||
outb(0xc4c, 0x00);
|
||||
case 0x2B: /* PC486GR/GF */
|
||||
case 0x30: /* PC486P */
|
||||
case 0x31: /* PC486GRSuper */
|
||||
case 0x32: /* PC486GR+ */
|
||||
case 0x37: /* PC486SE */
|
||||
case 0x38: /* PC486SR */
|
||||
/* Disable 0xF00000-0xFFFFFF. */
|
||||
outb(0x43f, 0x42);
|
||||
outb(0x467, 0xe0);
|
||||
outb(0x567, 0xd8);
|
||||
|
||||
/* Cache control end. */
|
||||
outb(0x43f, 0x40);
|
||||
break;
|
||||
|
||||
case 0x2B: /* PC486GR/GF */
|
||||
case 0x30: /* PC486P */
|
||||
case 0x31: /* PC486GRSuper */
|
||||
case 0x32: /* PC486GR+ */
|
||||
case 0x37: /* PC486SE */
|
||||
case 0x38: /* PC486SR */
|
||||
/* Disable 0xF00000-0xFFFFFF. */
|
||||
outb(0x43f, 0x42);
|
||||
outb(0x467, 0xe0);
|
||||
outb(0x567, 0xd8);
|
||||
|
||||
outb(0x43f, 0x40);
|
||||
outb(0x467, 0xe0);
|
||||
outb(0x567, 0xe0);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Disable 15MB-16MB RAM and enable memory window. */
|
||||
outb(0x43b, inb(0x43b) & 0xfd); /* Clear bit1. */
|
||||
outb(0x43f, 0x40);
|
||||
outb(0x467, 0xe0);
|
||||
outb(0x567, 0xe0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef notyet
|
||||
static void init_cpu_accel_mem(void);
|
||||
|
||||
static void
|
||||
init_cpu_accel_mem(void)
|
||||
{
|
||||
u_int target_page;
|
||||
/*
|
||||
* Certain 'CPU accelerator' supports over 16MB memory on
|
||||
* the machines whose BIOS doesn't store true size.
|
||||
* To support this, we don't trust BIOS values if Maxmem < 4096.
|
||||
*/
|
||||
if (Maxmem < 4096) {
|
||||
for (target_page = ptoa(4096); /* 16MB */
|
||||
target_page < ptoa(32768); /* 128MB */
|
||||
target_page += 256 * PAGE_SIZE /* 1MB step */) {
|
||||
u_int tmp, page_bad = FALSE, OrigMaxmem = Maxmem;
|
||||
|
||||
*(int *)CMAP1 = PG_V | PG_RW | PG_N | target_page;
|
||||
invltlb();
|
||||
|
||||
tmp = *(u_int *)CADDR1;
|
||||
/*
|
||||
* Test for alternating 1's and 0's
|
||||
*/
|
||||
*(volatile u_int *)CADDR1 = 0xaaaaaaaa;
|
||||
if (*(volatile u_int *)CADDR1 != 0xaaaaaaaa) {
|
||||
page_bad = TRUE;
|
||||
}
|
||||
/*
|
||||
* Test for alternating 0's and 1's
|
||||
*/
|
||||
*(volatile u_int *)CADDR1 = 0x55555555;
|
||||
if (*(volatile u_int *)CADDR1 != 0x55555555) {
|
||||
page_bad = TRUE;
|
||||
}
|
||||
/*
|
||||
* Test for all 1's
|
||||
*/
|
||||
*(volatile u_int *)CADDR1 = 0xffffffff;
|
||||
if (*(volatile u_int *)CADDR1 != 0xffffffff) {
|
||||
page_bad = TRUE;
|
||||
}
|
||||
/*
|
||||
* Test for all 0's
|
||||
*/
|
||||
*(volatile u_int *)CADDR1 = 0x0;
|
||||
if (*(volatile u_int *)CADDR1 != 0x0) {
|
||||
/*
|
||||
* test of page failed
|
||||
*/
|
||||
page_bad = TRUE;
|
||||
}
|
||||
/*
|
||||
* Restore original value.
|
||||
*/
|
||||
*(u_int *)CADDR1 = tmp;
|
||||
if (page_bad == TRUE) {
|
||||
Maxmem = atop(target_page) + 256;
|
||||
} else
|
||||
break;
|
||||
}
|
||||
*(int *)CMAP1 = 0;
|
||||
invltlb();
|
||||
}
|
||||
/* Disable 15MB-16MB RAM and enable memory window. */
|
||||
outb(0x43b, inb(0x43b) & 0xfd); /* Clear bit1. */
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -205,22 +118,33 @@ init_cpu_accel_mem(void)
|
||||
* Get physical memory size
|
||||
*/
|
||||
void
|
||||
pc98_getmemsize(void)
|
||||
pc98_getmemsize(unsigned *base, unsigned *ext, unsigned *under16)
|
||||
{
|
||||
unsigned char under16, over16;
|
||||
unsigned int over16;
|
||||
|
||||
/* available protected memory size under 16MB / 128KB */
|
||||
under16 = PC98_SYSTEM_PARAMETER(0x401);
|
||||
/* available protected memory size over 16MB / 1MB */
|
||||
over16 = PC98_SYSTEM_PARAMETER(0x594);
|
||||
/* add conventional memory size (1024KB / 128KB = 8) */
|
||||
under16 += 8;
|
||||
/* available conventional memory size */
|
||||
*base = ((PC98_SYSTEM_PARAMETER(0x501) & 7) + 1) * 128;
|
||||
|
||||
Maxmem = Maxmem_under16M = under16 * 128 * 1024 / PAGE_SIZE;
|
||||
Maxmem += (over16 * 1024 * 1024 / PAGE_SIZE);
|
||||
/* available protected memory size under 16MB */
|
||||
*under16 = PC98_SYSTEM_PARAMETER(0x401) * 128 + 1024;
|
||||
#ifdef EPSON_MEMWIN
|
||||
init_epson_memwin();
|
||||
if (pc98_machine_type & M_EPSON_PC98) {
|
||||
if (*under16 > (15 * 1024)) {
|
||||
/* chop under16 memory to 15MB */
|
||||
*under16 = 15 * 1024;
|
||||
}
|
||||
init_epson_memwin();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* available protected memory size over 16MB / 1MB */
|
||||
over16 = PC98_SYSTEM_PARAMETER(0x594);
|
||||
over16 += PC98_SYSTEM_PARAMETER(0x595) * 256;
|
||||
|
||||
*ext = *under16;
|
||||
if (over16 > 0) {
|
||||
*ext = (16 + over16) * 1024;
|
||||
}
|
||||
}
|
||||
|
||||
#include "da.h"
|
||||
|
@ -31,7 +31,7 @@
|
||||
#define __PC98_PC98_PC98_MACHDEP_H__
|
||||
|
||||
void pc98_init_dmac __P((void));
|
||||
void pc98_getmemsize __P((void));
|
||||
void pc98_getmemsize __P((unsigned *, unsigned *, unsigned *));
|
||||
|
||||
struct ccb_calc_geometry;
|
||||
int scsi_da_bios_params __P((struct ccb_calc_geometry *));
|
||||
|
Loading…
Reference in New Issue
Block a user