Merge from NetBSD:
- Remove clause 3 and 4 from TNF licenses. - Fix memset usage. - Various cleanup. - Kill caddr_t.
This commit is contained in:
Marius Strobl
parent
e595c01fd8
commit
2b6ae84b63
@ -26,7 +26,7 @@
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*
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*/
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/* $NetBSD: esp_sbus.c,v 1.31 2005/02/27 00:27:48 perry Exp $ */
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/* $NetBSD: esp_sbus.c,v 1.51 2009/09/17 16:28:12 tsutsui Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -44,13 +44,6 @@
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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@ -158,12 +151,12 @@ MODULE_DEPEND(esp, sbus, 1, 1, 1);
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/*
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* Functions and the switch for the MI code
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*/
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static u_char esp_read_reg(struct ncr53c9x_softc *sc, int reg);
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static void esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v);
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static uint8_t esp_read_reg(struct ncr53c9x_softc *sc, int reg);
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static void esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v);
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static int esp_dma_isintr(struct ncr53c9x_softc *sc);
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static void esp_dma_reset(struct ncr53c9x_softc *sc);
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static int esp_dma_intr(struct ncr53c9x_softc *sc);
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static int esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr,
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static int esp_dma_setup(struct ncr53c9x_softc *sc, void **addr,
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size_t *len, int datain, size_t *dmasize);
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static void esp_dma_go(struct ncr53c9x_softc *sc);
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static void esp_dma_stop(struct ncr53c9x_softc *sc);
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@ -172,7 +165,7 @@ static int espattach(struct esp_softc *esc,
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const struct ncr53c9x_glue *gluep);
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static int espdetach(struct esp_softc *esc);
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static const struct ncr53c9x_glue esp_sbus_glue = {
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static const struct ncr53c9x_glue const esp_sbus_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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@ -718,9 +711,9 @@ espdetach(struct esp_softc *esc)
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static int esp_sbus_debug = 0;
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static const struct {
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char *r_name;
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int r_flag;
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} esp__read_regnames [] = {
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const char *r_name;
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int r_flag;
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} const esp__read_regnames [] = {
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{ "TCL", 0}, /* 0/00 */
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{ "TCM", 0}, /* 1/04 */
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{ "FIFO", 0}, /* 2/08 */
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@ -739,10 +732,10 @@ static const struct {
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{ "TCX", 1}, /* f/3c */
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};
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static const struct {
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char *r_name;
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int r_flag;
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} esp__write_regnames[] = {
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static const const struct {
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const char *r_name;
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int r_flag;
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} const esp__write_regnames[] = {
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{ "TCL", 1}, /* 0/00 */
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{ "TCM", 1}, /* 1/04 */
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{ "FIFO", 0}, /* 2/08 */
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@ -762,11 +755,11 @@ static const struct {
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};
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#endif
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static u_char
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static uint8_t
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esp_read_reg(struct ncr53c9x_softc *sc, int reg)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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u_char v;
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uint8_t v;
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v = bus_read_1(esc->sc_res, reg * 4);
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@ -780,7 +773,7 @@ esp_read_reg(struct ncr53c9x_softc *sc, int reg)
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}
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static void
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esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v)
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esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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@ -818,8 +811,8 @@ esp_dma_intr(struct ncr53c9x_softc *sc)
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}
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static int
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esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
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int datain, size_t *dmasize)
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esp_dma_setup(struct ncr53c9x_softc *sc, void **addr, size_t *len,
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int datain, size_t *dmasize)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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@ -26,7 +26,7 @@
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*
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*/
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/* $NetBSD: ncr53c9x.c,v 1.125 2007/01/09 12:53:12 itohy Exp $ */
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/* $NetBSD: ncr53c9x.c,v 1.143 2011/07/31 18:39:00 jakllsch Exp $ */
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/*-
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* Copyright (c) 1998, 2002 The NetBSD Foundation, Inc.
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@ -43,13 +43,6 @@
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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@ -133,7 +126,7 @@ __FBSDID("$FreeBSD$");
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MODULE_DEPEND(esp, cam, 1, 1, 1);
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#ifdef NCR53C9X_DEBUG
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static int ncr53c9x_debug =
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int ncr53c9x_debug =
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NCR_SHOWMISC /* | NCR_SHOWPHASE | NCR_SHOWTRAC | NCR_SHOWCMDS */;
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#endif
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@ -167,7 +160,7 @@ static void ncr53c9x_sched(struct ncr53c9x_softc *sc);
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static void ncr53c9x_select(struct ncr53c9x_softc *sc,
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struct ncr53c9x_ecb *ecb);
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static void ncr53c9x_watch(void *arg);
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static void ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p,
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static void ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, uint8_t *p,
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int len);
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static struct ncr53c9x_ecb *ncr53c9x_get_ecb(struct ncr53c9x_softc *sc);
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@ -187,13 +180,11 @@ static inline int ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc,
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NCR_WRITE_REG((sc), NCR_TCL, (size)); \
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NCR_WRITE_REG((sc), NCR_TCM, (size) >> 8); \
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if ((sc->sc_cfg2 & NCRCFG2_FE) || \
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(sc->sc_rev == NCR_VARIANT_FAS366)) { \
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(sc->sc_rev == NCR_VARIANT_FAS366)) \
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NCR_WRITE_REG((sc), NCR_TCH, (size) >> 16); \
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} \
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if (sc->sc_rev == NCR_VARIANT_FAS366) { \
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if (sc->sc_rev == NCR_VARIANT_FAS366) \
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NCR_WRITE_REG(sc, NCR_RCH, 0); \
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} \
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} while (0)
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} while (/* CONSTCOND */0)
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#ifndef mstohz
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#define mstohz(ms) \
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@ -551,11 +542,10 @@ ncr53c9x_reset(struct ncr53c9x_softc *sc)
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NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4);
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#if 0
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device_printf(sc->sc_dev, "ncr53c9x_reset: revision %d\n",
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sc->sc_rev);
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device_printf(sc->sc_dev, "ncr53c9x_reset: cfg1 0x%x, cfg2 0x%x, "
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"cfg3 0x%x, ccf 0x%x, timeout 0x%x\n",
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sc->sc_cfg1, sc->sc_cfg2, sc->sc_cfg3, sc->sc_ccf, sc->sc_timeout);
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device_printf(sc->sc_dev, "%s: revision %d\n", __func__, sc->sc_rev);
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device_printf(sc->sc_dev, "%s: cfg1 0x%x, cfg2 0x%x, cfg3 0x%x, ccf "
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"0x%x, timeout 0x%x\n", __func__, sc->sc_cfg1, sc->sc_cfg2,
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sc->sc_cfg3, sc->sc_ccf, sc->sc_timeout);
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#endif
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}
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@ -573,7 +563,8 @@ ncr53c9x_clear(struct ncr53c9x_softc *sc, cam_status result)
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/* Cancel any active commands. */
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sc->sc_state = NCR_CLEANING;
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sc->sc_msgify = 0;
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if ((ecb = sc->sc_nexus) != NULL) {
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ecb = sc->sc_nexus;
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if (ecb != NULL) {
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ecb->ccb->ccb_h.status = result;
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ncr53c9x_done(sc, ecb);
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}
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@ -597,7 +588,8 @@ ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target,
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/* Cancel outstanding disconnected commands on each LUN. */
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LIST_FOREACH(li, &sc->sc_tinfo[target].luns, link) {
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if ((ecb = li->untagged) != NULL) {
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ecb = li->untagged;
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if (ecb != NULL) {
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li->untagged = NULL;
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/*
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* XXX should we terminate a command
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@ -607,12 +599,14 @@ ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target,
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ecb->ccb->ccb_h.status = result;
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ncr53c9x_done(sc, ecb);
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}
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for (i = 0; i < NCR_TAG_DEPTH; i++)
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if ((ecb = li->queued[i])) {
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for (i = 0; i < NCR_TAG_DEPTH; i++) {
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ecb = li->queued[i];
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if (ecb != NULL) {
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li->queued[i] = NULL;
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ecb->ccb->ccb_h.status = result;
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ncr53c9x_done(sc, ecb);
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}
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}
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li->used = 0;
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}
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}
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@ -635,7 +629,7 @@ ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset)
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TAILQ_INIT(&sc->ready_list);
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sc->sc_nexus = NULL;
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memset(sc->sc_tinfo, 0, sizeof(sc->sc_tinfo));
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memset(sc->sc_tinfo, 0, sizeof(*sc->sc_tinfo));
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for (r = 0; r < sc->sc_ntarg; r++) {
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LIST_INIT(&sc->sc_tinfo[r].luns);
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}
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@ -751,7 +745,7 @@ ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc, int period)
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static inline void
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ncr53c9x_setsync(struct ncr53c9x_softc *sc, struct ncr53c9x_tinfo *ti)
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{
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u_char cfg3, syncoff, synctp;
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uint8_t cfg3, syncoff, synctp;
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NCR_LOCK_ASSERT(sc, MA_OWNED);
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@ -810,7 +804,7 @@ static void
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ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
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{
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struct ncr53c9x_tinfo *ti;
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u_char *cmd;
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uint8_t *cmd;
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size_t dmasize;
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int clen, selatn3, selatns;
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int lun = ecb->ccb->ccb_h.target_lun;
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@ -818,8 +812,8 @@ ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
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NCR_LOCK_ASSERT(sc, MA_OWNED);
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NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x,tag:%x,%x)] ",
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target, lun, ecb->cmd.cmd.opcode, ecb->tag[0], ecb->tag[1]));
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NCR_TRACE(("[%s(t%d,l%d,cmd:%x,tag:%x,%x)] ", __func__, target, lun,
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ecb->cmd.cmd.opcode, ecb->tag[0], ecb->tag[1]));
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ti = &sc->sc_tinfo[target];
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sc->sc_state = NCR_SELECTING;
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@ -838,9 +832,8 @@ ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
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NCRCMD(sc, NCRCMD_FLUSH);
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NCR_WRITE_REG(sc, NCR_SELID, target | NCR_BUSID_HMEXC32 |
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NCR_BUSID_HMEENCID);
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} else {
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} else
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NCR_WRITE_REG(sc, NCR_SELID, target);
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}
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/*
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* If we are requesting sense, force a renegotiation if we are
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@ -873,7 +866,7 @@ ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
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selatns = 1;
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}
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cmd = (u_char *)&ecb->cmd.cmd;
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cmd = (uint8_t *)&ecb->cmd.cmd;
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if (selatn3) {
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/* We'll use tags with SELATN3. */
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@ -954,7 +947,7 @@ ncr53c9x_get_ecb(struct ncr53c9x_softc *sc)
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ecb = TAILQ_FIRST(&sc->free_list);
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if (ecb) {
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if (ecb->flags != 0)
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panic("ecb flags not cleared\n");
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panic("%s: ecb flags not cleared", __func__);
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TAILQ_REMOVE(&sc->free_list, ecb, free_links);
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ecb->flags = ECB_ALLOC;
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bzero(&ecb->ccb, sizeof(struct ncr53c9x_ecb) -
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@ -990,7 +983,7 @@ ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
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NCR_LOCK_ASSERT(sc, MA_OWNED);
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NCR_TRACE(("[ncr53c9x_action %d]", ccb->ccb_h.func_code));
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NCR_TRACE(("[%s %d]", __func__, ccb->ccb_h.func_code));
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switch (ccb->ccb_h.func_code) {
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case XPT_RESET_BUS:
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@ -1196,7 +1189,7 @@ ncr53c9x_poll(struct cam_sim *sim)
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NCR_LOCK_ASSERT(sc, MA_OWNED);
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NCR_TRACE(("[ncr53c9x_poll] "));
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NCR_TRACE(("[%s] ", __func__));
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if (NCRDMA_ISINTR(sc))
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ncr53c9x_intr1(sc);
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@ -1260,10 +1253,10 @@ ncr53c9x_sched(struct ncr53c9x_softc *sc)
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NCR_LOCK_ASSERT(sc, MA_OWNED);
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NCR_TRACE(("[ncr53c9x_sched] "));
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NCR_TRACE(("[%s] ", __func__));
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if (sc->sc_state != NCR_IDLE)
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panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state);
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panic("%s: not IDLE (state=%d)", __func__, sc->sc_state);
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/*
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* Find first ecb in ready queue that is for a target/lunit
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@ -1288,10 +1281,9 @@ ncr53c9x_sched(struct ncr53c9x_softc *sc)
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li = TINFO_LUN(ti, lun);
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if (li == NULL) {
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/* Initialize LUN info and add to list. */
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if ((li = malloc(sizeof(*li),
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M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
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li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT | M_ZERO);
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if (li == NULL)
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continue;
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}
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li->lun = lun;
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LIST_INSERT_HEAD(&ti->luns, li, link);
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@ -1338,7 +1330,7 @@ ncr53c9x_sched(struct ncr53c9x_softc *sc)
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ncr53c9x_select(sc, ecb);
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break;
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} else {
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NCR_TRACE(("%d:%d busy\n",
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NCR_TRACE(("[%s %d:%d busy] \n", __func__,
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ecb->ccb->ccb_h.target_id,
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ecb->ccb->ccb_h.target_lun));
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}
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@ -1356,7 +1348,7 @@ ncr53c9x_sense(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
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NCR_LOCK_ASSERT(sc, MA_OWNED);
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NCR_TRACE(("requesting sense "));
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NCR_TRACE(("[%s] ", __func__));
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lun = ccb->ccb_h.target_lun;
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ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
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@ -1368,7 +1360,7 @@ ncr53c9x_sense(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
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ss->length = sizeof(struct scsi_sense_data);
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ecb->clen = sizeof(*ss);
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memset(&ccb->csio.sense_data, 0, sizeof(ccb->csio.sense_data));
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ecb->daddr = (char *)&ccb->csio.sense_data;
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ecb->daddr = (uint8_t *)&ccb->csio.sense_data;
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ecb->dleft = sizeof(struct scsi_sense_data);
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ecb->flags |= ECB_SENSE;
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ecb->timeout = NCR_SENSE_TIMEOUT;
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@ -1379,9 +1371,9 @@ ncr53c9x_sense(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
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ncr53c9x_dequeue(sc, ecb);
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li->untagged = ecb; /* Must be executed first to fix C/A. */
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li->busy = 2;
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if (ecb == sc->sc_nexus) {
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if (ecb == sc->sc_nexus)
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ncr53c9x_select(sc, ecb);
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} else {
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else {
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TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain);
|
||||
ecb->flags |= ECB_READY;
|
||||
if (sc->sc_state == NCR_IDLE)
|
||||
@ -1402,7 +1394,7 @@ ncr53c9x_done(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
|
||||
|
||||
NCR_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
NCR_TRACE(("[ncr53c9x_done(status:%x)] ", ccb->ccb_h.status));
|
||||
NCR_TRACE(("[%s(status:%x)] ", __func__, ccb->ccb_h.status));
|
||||
|
||||
ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
|
||||
lun = ccb->ccb_h.target_lun;
|
||||
@ -1457,7 +1449,7 @@ ncr53c9x_done(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
|
||||
}
|
||||
|
||||
#ifdef NCR53C9X_DEBUG
|
||||
if (ncr53c9x_debug & NCR_SHOWTRAC) {
|
||||
if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) {
|
||||
if (ccb->csio.resid != 0)
|
||||
printf("resid=%d ", ccb->csio.resid);
|
||||
if ((ccb->ccb_h.status & CAM_AUTOSNS_VALID) != 0)
|
||||
@ -1510,7 +1502,7 @@ ncr53c9x_dequeue(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
|
||||
li = TINFO_LUN(ti, lun);
|
||||
#ifdef DIAGNOSTIC
|
||||
if (li == NULL || li->lun != lun)
|
||||
panic("ncr53c9x_dequeue: lun %qx for ecb %p does not exist",
|
||||
panic("%s: lun %qx for ecb %p does not exist", __func__,
|
||||
(long long)lun, ecb);
|
||||
#endif
|
||||
if (li->untagged == ecb) {
|
||||
@ -1521,9 +1513,9 @@ ncr53c9x_dequeue(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
|
||||
#ifdef DIAGNOSTIC
|
||||
if (li->queued[ecb->tag[1]] != NULL &&
|
||||
(li->queued[ecb->tag[1]] != ecb))
|
||||
panic("ncr53c9x_dequeue: slot %d for lun %qx has %p "
|
||||
"instead of ecb %p\n", ecb->tag[1],
|
||||
(long long)lun, li->queued[ecb->tag[1]], ecb);
|
||||
panic("%s: slot %d for lun %qx has %p instead of ecb "
|
||||
"%p", __func__, ecb->tag[1], (long long)lun,
|
||||
li->queued[ecb->tag[1]], ecb);
|
||||
#endif
|
||||
li->queued[ecb->tag[1]] = NULL;
|
||||
li->used--;
|
||||
@ -1550,7 +1542,7 @@ ncr53c9x_dequeue(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
|
||||
NCRCMD(sc, NCRCMD_SETATN); \
|
||||
sc->sc_flags |= NCR_ATN; \
|
||||
sc->sc_msgpriq |= (m); \
|
||||
} while (0)
|
||||
} while (/* CONSTCOND */0)
|
||||
|
||||
static void
|
||||
ncr53c9x_flushfifo(struct ncr53c9x_softc *sc)
|
||||
@ -1558,7 +1550,7 @@ ncr53c9x_flushfifo(struct ncr53c9x_softc *sc)
|
||||
|
||||
NCR_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
NCR_TRACE(("[flushfifo] "));
|
||||
NCR_TRACE(("[%s] ", __func__));
|
||||
|
||||
NCRCMD(sc, NCRCMD_FLUSH);
|
||||
|
||||
@ -1570,8 +1562,8 @@ ncr53c9x_flushfifo(struct ncr53c9x_softc *sc)
|
||||
static int
|
||||
ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how)
|
||||
{
|
||||
u_char *ibuf;
|
||||
int i, n;
|
||||
uint8_t *ibuf;
|
||||
|
||||
NCR_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
@ -1586,7 +1578,7 @@ ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how)
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("ncr53c9x_rdfifo: bad flag");
|
||||
panic("%s: bad flag", __func__);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
@ -1611,10 +1603,9 @@ ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how)
|
||||
|
||||
ncr53c9x_flushfifo(sc);
|
||||
}
|
||||
} else {
|
||||
} else
|
||||
for (i = 0; i < n; i++)
|
||||
ibuf[i] = NCR_READ_REG(sc, NCR_FIFO);
|
||||
}
|
||||
|
||||
sc->sc_imlen += i;
|
||||
|
||||
@ -1622,7 +1613,7 @@ ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how)
|
||||
#ifdef NCR53C9X_DEBUG
|
||||
NCR_TRACE(("\n[rdfifo %s (%d):",
|
||||
(how == NCR_RDFIFO_START) ? "start" : "cont", (int)sc->sc_imlen));
|
||||
if (ncr53c9x_debug & NCR_SHOWTRAC) {
|
||||
if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) {
|
||||
for (i = 0; i < sc->sc_imlen; i++)
|
||||
printf(" %02x", sc->sc_imess[i]);
|
||||
printf("]\n");
|
||||
@ -1633,7 +1624,7 @@ ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how)
|
||||
}
|
||||
|
||||
static void
|
||||
ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p, int len)
|
||||
ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, uint8_t *p, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
@ -1641,7 +1632,7 @@ ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p, int len)
|
||||
|
||||
#ifdef NCR53C9X_DEBUG
|
||||
NCR_MSGS(("[wrfifo(%d):", len));
|
||||
if (ncr53c9x_debug & NCR_SHOWMSGS) {
|
||||
if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) {
|
||||
for (i = 0; i < len; i++)
|
||||
printf(" %02x", p[i]);
|
||||
printf("]\n");
|
||||
@ -1663,13 +1654,13 @@ ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, int tagtype,
|
||||
struct ncr53c9x_ecb *ecb = NULL;
|
||||
struct ncr53c9x_linfo *li;
|
||||
struct ncr53c9x_tinfo *ti;
|
||||
u_char lun, selid, target;
|
||||
uint8_t lun, selid, target;
|
||||
|
||||
NCR_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
if (sc->sc_rev == NCR_VARIANT_FAS366) {
|
||||
if (sc->sc_rev == NCR_VARIANT_FAS366)
|
||||
target = sc->sc_selid;
|
||||
} else {
|
||||
else {
|
||||
/*
|
||||
* The SCSI chip made a snapshot of the data bus
|
||||
* while the reselection was being negotiated.
|
||||
@ -1751,7 +1742,7 @@ ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, int tagtype,
|
||||
#define MSG_IS2BYTE(m) (((m) & 0xf0) == 0x20)
|
||||
|
||||
static inline int
|
||||
__verify_msg_format(u_char *p, int len)
|
||||
__verify_msg_format(uint8_t *p, int len)
|
||||
{
|
||||
|
||||
if (len == 1 && MSG_IS1BYTE(p[0]))
|
||||
@ -1777,12 +1768,12 @@ ncr53c9x_msgin(struct ncr53c9x_softc *sc)
|
||||
struct ncr53c9x_ecb *ecb;
|
||||
struct ncr53c9x_linfo *li;
|
||||
struct ncr53c9x_tinfo *ti;
|
||||
u_char *pb;
|
||||
uint8_t *pb;
|
||||
int lun, plen;
|
||||
|
||||
NCR_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen));
|
||||
NCR_TRACE(("[%s(curmsglen:%ld)] ", __func__, (long)sc->sc_imlen));
|
||||
|
||||
if (sc->sc_imlen == 0) {
|
||||
device_printf(sc->sc_dev, "msgin: no msg byte available\n");
|
||||
@ -2068,19 +2059,19 @@ ncr53c9x_msgin(struct ncr53c9x_softc *sc)
|
||||
sc->sc_imess[0]);
|
||||
goto reset;
|
||||
}
|
||||
(void) ncr53c9x_reselect(sc, sc->sc_msgify,
|
||||
(void)ncr53c9x_reselect(sc, sc->sc_msgify,
|
||||
sc->sc_imess[0], sc->sc_imess[1]);
|
||||
break;
|
||||
|
||||
case NCR_RESELECTED:
|
||||
if (MSG_ISIDENTIFY(sc->sc_imess[1])) {
|
||||
if (MSG_ISIDENTIFY(sc->sc_imess[1]))
|
||||
sc->sc_msgify = sc->sc_imess[1];
|
||||
} else {
|
||||
else {
|
||||
device_printf(sc->sc_dev, "reselect without IDENTIFY;"
|
||||
" MSG %x; sending DEVICE RESET\n", sc->sc_imess[1]);
|
||||
goto reset;
|
||||
}
|
||||
(void) ncr53c9x_reselect(sc, sc->sc_msgify, 0, 0);
|
||||
(void)ncr53c9x_reselect(sc, sc->sc_msgify, 0, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -2124,8 +2115,8 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
|
||||
|
||||
NCR_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]",
|
||||
sc->sc_msgpriq, sc->sc_prevphase));
|
||||
NCR_TRACE(("[%s(priq:%x, prevphase:%x)]", __func__, sc->sc_msgpriq,
|
||||
sc->sc_prevphase));
|
||||
|
||||
/*
|
||||
* XXX - the NCR_ATN flag is not in sync with the actual ATN
|
||||
@ -2138,7 +2129,9 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
|
||||
if (sc->sc_prevphase != MESSAGE_OUT_PHASE) {
|
||||
new:
|
||||
NCRCMD(sc, NCRCMD_FLUSH);
|
||||
/* DELAY(1); */
|
||||
#if 0
|
||||
DELAY(1);
|
||||
#endif
|
||||
sc->sc_msgoutq = 0;
|
||||
sc->sc_omlen = 0;
|
||||
}
|
||||
@ -2146,10 +2139,9 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
|
||||
if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
|
||||
ncr53c9x_sched_msgout(sc->sc_msgoutq);
|
||||
goto new;
|
||||
} else {
|
||||
} else
|
||||
device_printf(sc->sc_dev, "at line %d: unexpected "
|
||||
"MESSAGE OUT phase\n", __LINE__);
|
||||
}
|
||||
}
|
||||
|
||||
if (sc->sc_omlen == 0) {
|
||||
@ -2181,20 +2173,18 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
|
||||
break;
|
||||
|
||||
case SEND_IDENTIFY:
|
||||
if (sc->sc_state != NCR_CONNECTED) {
|
||||
if (sc->sc_state != NCR_CONNECTED)
|
||||
device_printf(sc->sc_dev, "at line %d: no "
|
||||
"nexus\n", __LINE__);
|
||||
}
|
||||
ecb = sc->sc_nexus;
|
||||
sc->sc_omess[0] =
|
||||
MSG_IDENTIFY(ecb->ccb->ccb_h.target_lun, 0);
|
||||
break;
|
||||
|
||||
case SEND_TAG:
|
||||
if (sc->sc_state != NCR_CONNECTED) {
|
||||
if (sc->sc_state != NCR_CONNECTED)
|
||||
device_printf(sc->sc_dev, "at line %d: no "
|
||||
"nexus\n", __LINE__);
|
||||
}
|
||||
ecb = sc->sc_nexus;
|
||||
sc->sc_omess[0] = ecb->tag[0];
|
||||
sc->sc_omess[1] = ecb->tag[1];
|
||||
@ -2249,7 +2239,7 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
|
||||
}
|
||||
|
||||
#ifdef NCR53C9X_DEBUG
|
||||
if (ncr53c9x_debug & NCR_SHOWMSGS) {
|
||||
if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) {
|
||||
NCR_MSGS(("<msgout:"));
|
||||
for (i = 0; i < sc->sc_omlen; i++)
|
||||
NCR_MSGS((" %02x", sc->sc_omess[i]));
|
||||
@ -2310,7 +2300,7 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
struct timeval cur, wait;
|
||||
size_t size;
|
||||
int i, nfifo;
|
||||
u_char msg;
|
||||
uint8_t msg;
|
||||
|
||||
NCR_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
@ -2385,7 +2375,7 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
* while we were trying to select
|
||||
* another target.
|
||||
*/
|
||||
#ifdef DEBUG
|
||||
#ifdef NCR53C9X_DEBUG
|
||||
device_printf(sc->sc_dev, "ESP100 work-around "
|
||||
"activated\n");
|
||||
#endif
|
||||
@ -2492,7 +2482,9 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
sc->sc_espintr,sc->sc_espstat,sc->sc_espstep));
|
||||
if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
|
||||
NCRCMD(sc, NCRCMD_FLUSH);
|
||||
/* DELAY(1); */
|
||||
#if 0
|
||||
DELAY(1);
|
||||
#endif
|
||||
}
|
||||
/*
|
||||
* This command must (apparently) be issued within
|
||||
@ -2734,7 +2726,7 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
if (sc->sc_state == NCR_IDLE &&
|
||||
sc->sc_espstep == 0)
|
||||
return;
|
||||
panic("ncr53c9x: no nexus");
|
||||
panic("%s: no nexus", __func__);
|
||||
}
|
||||
|
||||
ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
|
||||
@ -2812,8 +2804,8 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
if (sc->sc_cmdlen == 0)
|
||||
/* Hope for the best... */
|
||||
break;
|
||||
} else if ((NCR_READ_REG(sc, NCR_FFLAG)
|
||||
& NCRFIFO_FF) == 0) {
|
||||
} else if ((NCR_READ_REG(sc, NCR_FFLAG) &
|
||||
NCRFIFO_FF) == 0) {
|
||||
/* Hope for the best... */
|
||||
break;
|
||||
}
|
||||
@ -2872,7 +2864,7 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
/* "Initiate Command Complete Steps" in progress */
|
||||
sc->sc_flags &= ~NCR_ICCS;
|
||||
|
||||
if (!(sc->sc_espintr & NCRINTR_DONE)) {
|
||||
if ((sc->sc_espintr & NCRINTR_DONE) == 0) {
|
||||
device_printf(sc->sc_dev, "ICCS: "
|
||||
": [intr %x, stat %x, step %x]\n",
|
||||
sc->sc_espintr, sc->sc_espstat,
|
||||
@ -2912,9 +2904,8 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
* Driver is now in state NCR_CONNECTED, i.e. we
|
||||
* have a current command working the SCSI bus.
|
||||
*/
|
||||
if (sc->sc_state != NCR_CONNECTED || ecb == NULL) {
|
||||
panic("ncr53c9x: no nexus");
|
||||
}
|
||||
if (sc->sc_state != NCR_CONNECTED || ecb == NULL)
|
||||
panic("%s: no nexus", __func__);
|
||||
|
||||
switch (sc->sc_phase) {
|
||||
case MESSAGE_OUT_PHASE:
|
||||
@ -2928,7 +2919,7 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
NCR_PHASE(("MESSAGE_IN_PHASE "));
|
||||
if ((sc->sc_espintr & NCRINTR_BS) != 0) {
|
||||
if ((sc->sc_rev != NCR_VARIANT_FAS366) ||
|
||||
!(sc->sc_espstat2 & NCRFAS_STAT2_EMPTY)) {
|
||||
(sc->sc_espstat2 & NCRFAS_STAT2_EMPTY) == 0) {
|
||||
NCRCMD(sc, NCRCMD_FLUSH);
|
||||
}
|
||||
sc->sc_flags |= NCR_WAITI;
|
||||
@ -2945,11 +2936,10 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
(sc->sc_prevphase == sc->sc_phase) ?
|
||||
NCR_RDFIFO_CONTINUE : NCR_RDFIFO_START);
|
||||
ncr53c9x_msgin(sc);
|
||||
} else {
|
||||
} else
|
||||
device_printf(sc->sc_dev, "MSGIN: weird bits: "
|
||||
"[intr %x, stat %x, step %x]\n",
|
||||
sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
|
||||
}
|
||||
sc->sc_prevphase = MESSAGE_IN_PHASE;
|
||||
goto shortcut; /* i.e. expect data to be ready */
|
||||
|
||||
@ -2966,7 +2956,9 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
ecb->cmd.cmd.opcode, ecb->clen));
|
||||
if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) {
|
||||
NCRCMD(sc, NCRCMD_FLUSH);
|
||||
/* DELAY(1);*/
|
||||
#if 0
|
||||
DELAY(1);
|
||||
#endif
|
||||
}
|
||||
/*
|
||||
* If we have more messages to send, e.g. WDTR or SDTR
|
||||
@ -2981,7 +2973,7 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
/* Setup DMA transfer for command. */
|
||||
size = ecb->clen;
|
||||
sc->sc_cmdlen = size;
|
||||
sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd;
|
||||
sc->sc_cmdp = (void *)&ecb->cmd.cmd;
|
||||
NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen,
|
||||
0, &size);
|
||||
/* Program the SCSI counter. */
|
||||
@ -2994,7 +2986,8 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
||||
NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA);
|
||||
NCRDMA_GO(sc);
|
||||
} else {
|
||||
ncr53c9x_wrfifo(sc, (u_char *)&ecb->cmd.cmd, ecb->clen);
|
||||
ncr53c9x_wrfifo(sc, (uint8_t *)&ecb->cmd.cmd,
|
||||
ecb->clen);
|
||||
NCRCMD(sc, NCRCMD_TRANS);
|
||||
}
|
||||
sc->sc_prevphase = COMMAND_PHASE;
|
||||
@ -3175,7 +3168,7 @@ ncr53c9x_callout(void *arg)
|
||||
static void
|
||||
ncr53c9x_watch(void *arg)
|
||||
{
|
||||
struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg;
|
||||
struct ncr53c9x_softc *sc = arg;
|
||||
struct ncr53c9x_linfo *li;
|
||||
struct ncr53c9x_tinfo *ti;
|
||||
time_t old;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: ncr53c9xreg.h,v 1.14 2005/02/27 00:27:02 perry Exp $ */
|
||||
/* $NetBSD: ncr53c9xreg.h,v 1.16 2009/09/07 13:31:44 tsutsui Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1994 Peter Galbavy. All rights reserved.
|
||||
@ -43,84 +43,84 @@
|
||||
#define NCR_FIFO 0x02 /* RW - FIFO data */
|
||||
|
||||
#define NCR_CMD 0x03 /* RW - Command (2 deep) */
|
||||
#define NCRCMD_DMA 0x80 /* DMA Bit */
|
||||
#define NCRCMD_NOP 0x00 /* No Operation */
|
||||
#define NCRCMD_FLUSH 0x01 /* Flush FIFO */
|
||||
#define NCRCMD_RSTCHIP 0x02 /* Reset Chip */
|
||||
#define NCRCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
|
||||
#define NCRCMD_RESEL 0x40 /* Reselect Sequence */
|
||||
#define NCRCMD_SELNATN 0x41 /* Select without ATN */
|
||||
#define NCRCMD_SELATN 0x42 /* Select with ATN */
|
||||
#define NCRCMD_SELATNS 0x43 /* Select with ATN & Stop */
|
||||
#define NCRCMD_ENSEL 0x44 /* Enable (Re)Selection */
|
||||
#define NCRCMD_DISSEL 0x45 /* Disable (Re)Selection */
|
||||
#define NCRCMD_SELATN3 0x46 /* Select with ATN3 */
|
||||
#define NCRCMD_RESEL3 0x47 /* Reselect3 Sequence */
|
||||
#define NCRCMD_SNDMSG 0x20 /* Send Message */
|
||||
#define NCRCMD_SNDSTAT 0x21 /* Send Status */
|
||||
#define NCRCMD_SNDDATA 0x22 /* Send Data */
|
||||
#define NCRCMD_DISCSEQ 0x23 /* Disconnect Sequence */
|
||||
#define NCRCMD_TERMSEQ 0x24 /* Terminate Sequence */
|
||||
#define NCRCMD_TCCS 0x25 /* Target Command Comp Seq */
|
||||
#define NCRCMD_DISC 0x27 /* Disconnect */
|
||||
#define NCRCMD_RECMSG 0x28 /* Receive Message */
|
||||
#define NCRCMD_RECCMD 0x29 /* Receive Command */
|
||||
#define NCRCMD_RECDATA 0x2a /* Receive Data */
|
||||
#define NCRCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
|
||||
#define NCRCMD_ABORT 0x04 /* Target Abort DMA */
|
||||
#define NCRCMD_TRANS 0x10 /* Transfer Information */
|
||||
#define NCRCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
|
||||
#define NCRCMD_MSGOK 0x12 /* Message Accepted */
|
||||
#define NCRCMD_TRPAD 0x18 /* Transfer Pad */
|
||||
#define NCRCMD_SETATN 0x1a /* Set ATN */
|
||||
#define NCRCMD_RSTATN 0x1b /* Reset ATN */
|
||||
#define NCRCMD_DMA 0x80 /* DMA Bit */
|
||||
#define NCRCMD_NOP 0x00 /* No Operation */
|
||||
#define NCRCMD_FLUSH 0x01 /* Flush FIFO */
|
||||
#define NCRCMD_RSTCHIP 0x02 /* Reset Chip */
|
||||
#define NCRCMD_RSTSCSI 0x03 /* Reset SCSI Bus */
|
||||
#define NCRCMD_RESEL 0x40 /* Reselect Sequence */
|
||||
#define NCRCMD_SELNATN 0x41 /* Select without ATN */
|
||||
#define NCRCMD_SELATN 0x42 /* Select with ATN */
|
||||
#define NCRCMD_SELATNS 0x43 /* Select with ATN & Stop */
|
||||
#define NCRCMD_ENSEL 0x44 /* Enable (Re)Selection */
|
||||
#define NCRCMD_DISSEL 0x45 /* Disable (Re)Selection */
|
||||
#define NCRCMD_SELATN3 0x46 /* Select with ATN3 */
|
||||
#define NCRCMD_RESEL3 0x47 /* Reselect3 Sequence */
|
||||
#define NCRCMD_SNDMSG 0x20 /* Send Message */
|
||||
#define NCRCMD_SNDSTAT 0x21 /* Send Status */
|
||||
#define NCRCMD_SNDDATA 0x22 /* Send Data */
|
||||
#define NCRCMD_DISCSEQ 0x23 /* Disconnect Sequence */
|
||||
#define NCRCMD_TERMSEQ 0x24 /* Terminate Sequence */
|
||||
#define NCRCMD_TCCS 0x25 /* Target Command Comp Seq */
|
||||
#define NCRCMD_DISC 0x27 /* Disconnect */
|
||||
#define NCRCMD_RECMSG 0x28 /* Receive Message */
|
||||
#define NCRCMD_RECCMD 0x29 /* Receive Command */
|
||||
#define NCRCMD_RECDATA 0x2a /* Receive Data */
|
||||
#define NCRCMD_RECCSEQ 0x2b /* Receive Command Sequence*/
|
||||
#define NCRCMD_ABORT 0x04 /* Target Abort DMA */
|
||||
#define NCRCMD_TRANS 0x10 /* Transfer Information */
|
||||
#define NCRCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
|
||||
#define NCRCMD_MSGOK 0x12 /* Message Accepted */
|
||||
#define NCRCMD_TRPAD 0x18 /* Transfer Pad */
|
||||
#define NCRCMD_SETATN 0x1a /* Set ATN */
|
||||
#define NCRCMD_RSTATN 0x1b /* Reset ATN */
|
||||
|
||||
#define NCR_STAT 0x04 /* RO - Status */
|
||||
#define NCRSTAT_INT 0x80 /* Interrupt */
|
||||
#define NCRSTAT_GE 0x40 /* Gross Error */
|
||||
#define NCRSTAT_PE 0x20 /* Parity Error */
|
||||
#define NCRSTAT_TC 0x10 /* Terminal Count */
|
||||
#define NCRSTAT_VGC 0x08 /* Valid Group Code */
|
||||
#define NCRSTAT_PHASE 0x07 /* Phase bits */
|
||||
#define NCRSTAT_INT 0x80 /* Interrupt */
|
||||
#define NCRSTAT_GE 0x40 /* Gross Error */
|
||||
#define NCRSTAT_PE 0x20 /* Parity Error */
|
||||
#define NCRSTAT_TC 0x10 /* Terminal Count */
|
||||
#define NCRSTAT_VGC 0x08 /* Valid Group Code */
|
||||
#define NCRSTAT_PHASE 0x07 /* Phase bits */
|
||||
|
||||
#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */
|
||||
#define NCR_BUSID_HMEXC32 0x40 /* HME xfer counter is 32bit */
|
||||
#define NCR_BUSID_HMEENCID 0x10 /* HME encode reselection ID */
|
||||
#define NCR_BUSID_HMEXC32 0x40 /* HME xfer counter is 32bit */
|
||||
#define NCR_BUSID_HMEENCID 0x10 /* HME encode reselection ID */
|
||||
|
||||
#define NCR_INTR 0x05 /* RO - Interrupt */
|
||||
#define NCRINTR_SBR 0x80 /* SCSI Bus Reset */
|
||||
#define NCRINTR_ILL 0x40 /* Illegal Command */
|
||||
#define NCRINTR_DIS 0x20 /* Disconnect */
|
||||
#define NCRINTR_BS 0x10 /* Bus Service */
|
||||
#define NCRINTR_FC 0x08 /* Function Complete */
|
||||
#define NCRINTR_RESEL 0x04 /* Reselected */
|
||||
#define NCRINTR_SELATN 0x02 /* Select with ATN */
|
||||
#define NCRINTR_SEL 0x01 /* Selected */
|
||||
#define NCRINTR_SBR 0x80 /* SCSI Bus Reset */
|
||||
#define NCRINTR_ILL 0x40 /* Illegal Command */
|
||||
#define NCRINTR_DIS 0x20 /* Disconnect */
|
||||
#define NCRINTR_BS 0x10 /* Bus Service */
|
||||
#define NCRINTR_FC 0x08 /* Function Complete */
|
||||
#define NCRINTR_RESEL 0x04 /* Reselected */
|
||||
#define NCRINTR_SELATN 0x02 /* Select with ATN */
|
||||
#define NCRINTR_SEL 0x01 /* Selected */
|
||||
|
||||
#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
|
||||
|
||||
#define NCR_STEP 0x06 /* RO - Sequence Step */
|
||||
#define NCRSTEP_MASK 0x07 /* the last 3 bits */
|
||||
#define NCRSTEP_DONE 0x04 /* command went out */
|
||||
#define NCRSTEP_MASK 0x07 /* the last 3 bits */
|
||||
#define NCRSTEP_DONE 0x04 /* command went out */
|
||||
|
||||
#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */
|
||||
/* Default 5 (53C9X) */
|
||||
|
||||
#define NCR_FFLAG 0x07 /* RO - FIFO Flags */
|
||||
#define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */
|
||||
#define NCRFIFO_FF 0x1f /* Bytes in FIFO */
|
||||
#define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */
|
||||
#define NCRFIFO_FF 0x1f /* Bytes in FIFO */
|
||||
|
||||
#define NCR_SYNCOFF 0x07 /* WO - Synch Offset */
|
||||
/* 0 = ASYNC */
|
||||
/* 1 - 15 = SYNC bytes */
|
||||
|
||||
#define NCR_CFG1 0x08 /* RW - Configuration #1 */
|
||||
#define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */
|
||||
#define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
|
||||
#define NCRCFG1_PTEST 0x20 /* Parity Test Mod */
|
||||
#define NCRCFG1_PARENB 0x10 /* Enable Parity Check */
|
||||
#define NCRCFG1_CTEST 0x08 /* Enable Chip Test */
|
||||
#define NCRCFG1_BUSID 0x07 /* Bus ID */
|
||||
#define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */
|
||||
#define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
|
||||
#define NCRCFG1_PTEST 0x20 /* Parity Test Mod */
|
||||
#define NCRCFG1_PARENB 0x10 /* Enable Parity Check */
|
||||
#define NCRCFG1_CTEST 0x08 /* Enable Chip Test */
|
||||
#define NCRCFG1_BUSID 0x07 /* Bus ID */
|
||||
|
||||
#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */
|
||||
/* 0 = 35.01 - 40MHz */
|
||||
@ -136,24 +136,24 @@
|
||||
|
||||
#define NCR_CFG2 0x0b /* RW - Configuration #2 */
|
||||
#define NCRCFG2_RSVD 0xa0 /* reserved */
|
||||
#define NCRCFG2_FE 0x40 /* Features Enable */
|
||||
#define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */
|
||||
#define NCRCFG2_SCSI2 0x08 /* SCSI-2 Enable */
|
||||
#define NCRCFG2_BPA 0x04 /* Target Bad Parity Abort */
|
||||
#define NCRCFG2_RPE 0x02 /* Register Parity Error */
|
||||
#define NCRCFG2_DPE 0x01 /* DMA Parity Error */
|
||||
#define NCRCFG2_FE 0x40 /* Features Enable */
|
||||
#define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */
|
||||
#define NCRCFG2_SCSI2 0x08 /* SCSI-2 Enable */
|
||||
#define NCRCFG2_BPA 0x04 /* Target Bad Parity Abort */
|
||||
#define NCRCFG2_RPE 0x02 /* Register Parity Error */
|
||||
#define NCRCFG2_DPE 0x01 /* DMA Parity Error */
|
||||
|
||||
#define NCRCFG2_HMEFE 0x10 /* HME feature enable */
|
||||
#define NCRCFG2_HMEFE 0x10 /* HME feature enable */
|
||||
#define NCRCFG2_HME32 0x80 /* HME 32 extended */
|
||||
|
||||
/* Config #3 only on 53C9X */
|
||||
#define NCR_CFG3 0x0c /* RW - Configuration #3 */
|
||||
#define NCRCFG3_RSVD 0xe0 /* reserved */
|
||||
#define NCRCFG3_IDM 0x10 /* ID Message Res Check */
|
||||
#define NCRCFG3_QTE 0x08 /* Queue Tag Enable */
|
||||
#define NCRCFG3_CDB 0x04 /* CDB 10-bytes OK */
|
||||
#define NCRCFG3_FSCSI 0x02 /* Fast SCSI */
|
||||
#define NCRCFG3_FCLK 0x01 /* Fast Clock (>25MHz) */
|
||||
#define NCRCFG3_IDM 0x10 /* ID Message Res Check */
|
||||
#define NCRCFG3_QTE 0x08 /* Queue Tag Enable */
|
||||
#define NCRCFG3_CDB 0x04 /* CDB 10-bytes OK */
|
||||
#define NCRCFG3_FSCSI 0x02 /* Fast SCSI */
|
||||
#define NCRCFG3_FCLK 0x01 /* Fast Clock (>25MHz) */
|
||||
|
||||
/*
|
||||
* For some unknown reason, the ESP406/FAS408 looks like every
|
||||
@ -164,35 +164,35 @@
|
||||
|
||||
/* Config #3 different on ESP406/FAS408 */
|
||||
#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */
|
||||
#define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */
|
||||
#define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */
|
||||
#define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */
|
||||
#define NCRESPCFG3_FSCSI 0x10 /* Fast SCSI */
|
||||
#define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */
|
||||
#define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */
|
||||
#define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */
|
||||
#define NCRESPCFG3_FSCSI 0x10 /* Fast SCSI */
|
||||
#define NCRESPCFG3_SRESB 0x08 /* Save Residual Byte */
|
||||
#define NCRESPCFG3_FCLK 0x04 /* Fast Clock (>25MHz) */
|
||||
#define NCRESPCFG3_FCLK 0x04 /* Fast Clock (>25MHz) */
|
||||
#define NCRESPCFG3_ADMA 0x02 /* Alternate DMA Mode */
|
||||
#define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */
|
||||
|
||||
/* Config #3 also different on NCR53CF9x/FAS100A/FAS216/FAS236 */
|
||||
#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */
|
||||
#define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */
|
||||
#define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */
|
||||
#define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */
|
||||
#define NCRF9XCFG3_FSCSI 0x10 /* Fast SCSI */
|
||||
#define NCRF9XCFG3_FCLK 0x08 /* Fast Clock (>25MHz) */
|
||||
#define NCRF9XCFG3_SRESB 0x04 /* Save Residual Byte */
|
||||
#define NCRF9XCFG3_ADMA 0x02 /* Alternate DMA Mode */
|
||||
#define NCRF9XCFG3_T8M 0x01 /* Threshold 8 Mode */
|
||||
#define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */
|
||||
#define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */
|
||||
#define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */
|
||||
#define NCRF9XCFG3_FSCSI 0x10 /* Fast SCSI */
|
||||
#define NCRF9XCFG3_FCLK 0x08 /* Fast Clock (>25MHz) */
|
||||
#define NCRF9XCFG3_SRESB 0x04 /* Save Residual Byte */
|
||||
#define NCRF9XCFG3_ADMA 0x02 /* Alternate DMA Mode */
|
||||
#define NCRF9XCFG3_T8M 0x01 /* Threshold 8 Mode */
|
||||
|
||||
/* Config #3 on FAS366 */
|
||||
#define NCRFASCFG3_OBAUTO 0x80 /* auto push odd-byte to DMA */
|
||||
#define NCRFASCFG3_EWIDE 0x40 /* Enable Wide-SCSI */
|
||||
#define NCRFASCFG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID */
|
||||
#define NCRFASCFG3_IDRESCHK 0x10 /* ID message checking */
|
||||
#define NCRFASCFG3_QUENB 0x08 /* 3-byte msg support */
|
||||
#define NCRFASCFG3_CDB10 0x04 /* group 2 scsi-2 support */
|
||||
#define NCRFASCFG3_FASTSCSI 0x02 /* 10 MB/S fast scsi mode */
|
||||
#define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */
|
||||
#define NCRFASCFG3_OBAUTO 0x80 /* auto push odd-byte to DMA */
|
||||
#define NCRFASCFG3_EWIDE 0x40 /* Enable Wide-SCSI */
|
||||
#define NCRFASCFG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID */
|
||||
#define NCRFASCFG3_IDRESCHK 0x10 /* ID message checking */
|
||||
#define NCRFASCFG3_QUENB 0x08 /* 3-byte msg support */
|
||||
#define NCRFASCFG3_CDB10 0x04 /* group 2 scsi-2 support */
|
||||
#define NCRFASCFG3_FASTSCSI 0x02 /* 10 MB/S fast scsi mode */
|
||||
#define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */
|
||||
|
||||
/* Config #4 only on ESP406/FAS408 */
|
||||
#define NCR_CFG4 0x0d /* RW - Configuration #4 */
|
||||
@ -208,8 +208,8 @@
|
||||
*/
|
||||
|
||||
#define NCR_JMP 0x00 /* RO - Jumper Sense Register */
|
||||
#define NCRJMP_RSVD 0xc0 /* reserved */
|
||||
#define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */
|
||||
#define NCRJMP_RSVD 0xc0 /* reserved */
|
||||
#define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */
|
||||
#define NCRJMP_J4 0x10 /* Jumper #4 */
|
||||
#define NCRJMP_J3 0x08 /* Jumper #3 */
|
||||
#define NCRJMP_J2 0x04 /* Jumper #2 */
|
||||
@ -218,17 +218,17 @@
|
||||
|
||||
#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */
|
||||
|
||||
#define NCR_PSTAT 0x08 /* RW - PIO Status Register */
|
||||
#define NCRPSTAT_PERR 0x80 /* PIO Error */
|
||||
#define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */
|
||||
#define NCRPSTAT_ATAI 0x20 /* ATA IRQ */
|
||||
#define NCRPSTAT_FEMPT 0x10 /* PIO FIFO Empty */
|
||||
#define NCRPSTAT_F13 0x08 /* PIO FIFO 1/3 */
|
||||
#define NCRPSTAT_F23 0x04 /* PIO FIFO 2/3 */
|
||||
#define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */
|
||||
#define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */
|
||||
#define NCR_PSTAT 0x08 /* RW - PIO Status Register */
|
||||
#define NCRPSTAT_PERR 0x80 /* PIO Error */
|
||||
#define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */
|
||||
#define NCRPSTAT_ATAI 0x20 /* ATA IRQ */
|
||||
#define NCRPSTAT_FEMPT 0x10 /* PIO FIFO Empty */
|
||||
#define NCRPSTAT_F13 0x08 /* PIO FIFO 1/3 */
|
||||
#define NCRPSTAT_F23 0x04 /* PIO FIFO 2/3 */
|
||||
#define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */
|
||||
#define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */
|
||||
|
||||
#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
|
||||
#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
|
||||
#define NCRPIOI_RSVD 0xe0 /* reserved */
|
||||
#define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */
|
||||
#define NCRPIOI_13 0x08 /* IRQ When 1/3 */
|
||||
@ -239,12 +239,12 @@
|
||||
#define NCR_CFG5 0x0d /* RW - Configuration #5 */
|
||||
#define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */
|
||||
#define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */
|
||||
#define NCRCFG5_AADDR 0x20 /* Auto Address */
|
||||
#define NCRCFG5_PTRINC 0x10 /* Pointer Increment */
|
||||
#define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */
|
||||
#define NCRCFG5_SINT 0x04 /* SCSI Interrupt Enable */
|
||||
#define NCRCFG5_INTP 0x02 /* INT Polarity */
|
||||
#define NCRCFG5_AINT 0x01 /* ATA Interrupt Enable */
|
||||
#define NCRCFG5_AADDR 0x20 /* Auto Address */
|
||||
#define NCRCFG5_PTRINC 0x10 /* Pointer Increment */
|
||||
#define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */
|
||||
#define NCRCFG5_SINT 0x04 /* SCSI Interrupt Enable */
|
||||
#define NCRCFG5_INTP 0x02 /* INT Polarity */
|
||||
#define NCRCFG5_AINT 0x01 /* ATA Interrupt Enable */
|
||||
|
||||
#define NCR_SIGNTR 0x0e /* RO - Signature */
|
||||
|
||||
@ -272,13 +272,13 @@
|
||||
/*
|
||||
* FAS366
|
||||
*/
|
||||
#define NCR_RCL NCR_TCH /* Recommand counter low */
|
||||
#define NCR_RCH 0xf /* Recommand counter high */
|
||||
#define NCR_UID NCR_RCL /* fas366 part-uniq id */
|
||||
#define NCR_RCL NCR_TCH /* Recommand counter low */
|
||||
#define NCR_RCH 0xf /* Recommand counter high */
|
||||
#define NCR_UID NCR_RCL /* fas366 part-uniq id */
|
||||
|
||||
|
||||
/* status register #2 definitions (read only) */
|
||||
#define NCR_STAT2 NCR_CCF
|
||||
#define NCR_STAT2 NCR_CCF
|
||||
#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */
|
||||
#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */
|
||||
#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: ncr53c9xvar.h,v 1.46 2005/02/04 02:10:36 perry Exp $ */
|
||||
/* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 The NetBSD Foundation, Inc.
|
||||
@ -133,27 +133,27 @@ struct ncr53c9x_ecb {
|
||||
struct callout ch;
|
||||
|
||||
struct {
|
||||
u_char msg[3]; /* Selection Id msg and tags */
|
||||
uint8_t msg[3]; /* Selection Id msg and tags */
|
||||
struct scsi_generic cmd; /* SCSI command block */
|
||||
} cmd;
|
||||
char *daddr; /* Saved data pointer */
|
||||
uint8_t *daddr; /* Saved data pointer */
|
||||
int clen; /* Size of command in cmd.cmd */
|
||||
int dleft; /* Residue */
|
||||
u_char stat; /* SCSI status byte */
|
||||
u_char tag[2]; /* TAG bytes */
|
||||
u_char pad[1];
|
||||
uint8_t stat; /* SCSI status byte */
|
||||
uint8_t tag[2]; /* TAG bytes */
|
||||
uint8_t pad[1];
|
||||
|
||||
#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
|
||||
char trace[1000];
|
||||
#endif
|
||||
};
|
||||
#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
|
||||
#define ECB_TRACE(ecb, msg, a, b) do { \
|
||||
const char *f = "[" msg "]"; \
|
||||
int n = strlen((ecb)->trace); \
|
||||
if (n < (sizeof((ecb)->trace)-100)) \
|
||||
sprintf((ecb)->trace + n, f, a, b); \
|
||||
} while(0)
|
||||
#define ECB_TRACE(ecb, msg, a, b) do { \
|
||||
const char *f = "[" msg "]"; \
|
||||
int n = strlen((ecb)->trace); \
|
||||
if (n < (sizeof((ecb)->trace)-100)) \
|
||||
sprintf((ecb)->trace + n, f, a, b); \
|
||||
} while (/* CONSTCOND */0)
|
||||
#else
|
||||
#define ECB_TRACE(ecb, msg, a, b)
|
||||
#endif
|
||||
@ -174,17 +174,17 @@ struct ncr53c9x_linfo {
|
||||
int64_t lun;
|
||||
LIST_ENTRY(ncr53c9x_linfo) link;
|
||||
time_t last_used;
|
||||
u_char used; /* # slots in use */
|
||||
u_char avail; /* where to start scanning */
|
||||
u_char busy;
|
||||
uint8_t used; /* # slots in use */
|
||||
uint8_t avail; /* where to start scanning */
|
||||
uint8_t busy;
|
||||
struct ncr53c9x_ecb *untagged;
|
||||
struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
|
||||
};
|
||||
|
||||
struct ncr53c9x_xinfo {
|
||||
u_char period;
|
||||
u_char offset;
|
||||
u_char width;
|
||||
uint8_t period;
|
||||
uint8_t offset;
|
||||
uint8_t width;
|
||||
};
|
||||
|
||||
struct ncr53c9x_tinfo {
|
||||
@ -193,7 +193,7 @@ struct ncr53c9x_tinfo {
|
||||
int touts; /* # of timeouts */
|
||||
int perrs; /* # of parity errors */
|
||||
int senses; /* # of request sense commands sent */
|
||||
u_char flags;
|
||||
uint8_t flags;
|
||||
#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */
|
||||
#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */
|
||||
#define T_TAG 0x04 /* Turn on TAG QUEUEs */
|
||||
@ -206,13 +206,13 @@ struct ncr53c9x_tinfo {
|
||||
};
|
||||
|
||||
/* Look up a lun in a tinfo */
|
||||
#define TINFO_LUN(t, l) ( \
|
||||
(((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
|
||||
? ((t)->lun[(l)]) \
|
||||
: ncr53c9x_lunsearch((t), (int64_t)(l)) \
|
||||
#define TINFO_LUN(t, l) ( \
|
||||
(((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
|
||||
? ((t)->lun[(l)]) \
|
||||
: ncr53c9x_lunsearch((t), (int64_t)(l)) \
|
||||
)
|
||||
|
||||
/* Register a linenumber (for debugging) */
|
||||
/* Register a linenumber (for debugging). */
|
||||
#define LOGLINE(p)
|
||||
|
||||
#define NCR_SHOWECBS 0x01
|
||||
@ -228,24 +228,51 @@ struct ncr53c9x_tinfo {
|
||||
|
||||
#ifdef NCR53C9X_DEBUG
|
||||
extern int ncr53c9x_debug;
|
||||
#define NCR_ECBS(str) \
|
||||
do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
|
||||
#define NCR_MISC(str) \
|
||||
do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
|
||||
#define NCR_INTS(str) \
|
||||
do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
|
||||
#define NCR_TRACE(str) \
|
||||
do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
|
||||
#define NCR_CMDS(str) \
|
||||
do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
|
||||
#define NCR_START(str) \
|
||||
do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
|
||||
#define NCR_PHASE(str) \
|
||||
do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
|
||||
#define NCR_DMA(str) \
|
||||
do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
|
||||
#define NCR_MSGS(str) \
|
||||
do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
|
||||
#define NCR_ECBS(str) \
|
||||
do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWECBS) != 0) \
|
||||
printf str; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#define NCR_MISC(str) \
|
||||
do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWMISC) != 0) \
|
||||
printf str; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#define NCR_INTS(str) \
|
||||
do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWINTS) != 0) \
|
||||
printf str; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#define NCR_TRACE(str) \
|
||||
do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) \
|
||||
printf str; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#define NCR_CMDS(str) \
|
||||
do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWCMDS) != 0) \
|
||||
printf str; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#define NCR_START(str) \
|
||||
do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWSTART) != 0) \
|
||||
printf str; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#define NCR_PHASE(str) \
|
||||
do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWPHASE) != 0) \
|
||||
printf str; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#define NCR_DMA(str) \
|
||||
do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWDMA) != 0) \
|
||||
printf str; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#define NCR_MSGS(str) \
|
||||
do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) \
|
||||
printf str; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#else
|
||||
#define NCR_ECBS(str)
|
||||
#define NCR_MISC(str)
|
||||
@ -267,13 +294,13 @@ struct ncr53c9x_softc;
|
||||
*/
|
||||
struct ncr53c9x_glue {
|
||||
/* Mandatory entry points. */
|
||||
u_char (*gl_read_reg)(struct ncr53c9x_softc *, int);
|
||||
void (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char);
|
||||
uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int);
|
||||
void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t);
|
||||
int (*gl_dma_isintr)(struct ncr53c9x_softc *);
|
||||
void (*gl_dma_reset)(struct ncr53c9x_softc *);
|
||||
int (*gl_dma_intr)(struct ncr53c9x_softc *);
|
||||
int (*gl_dma_setup)(struct ncr53c9x_softc *,
|
||||
caddr_t *, size_t *, int, size_t *);
|
||||
int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *,
|
||||
int, size_t *);
|
||||
void (*gl_dma_go)(struct ncr53c9x_softc *);
|
||||
void (*gl_dma_stop)(struct ncr53c9x_softc *);
|
||||
int (*gl_dma_isactive)(struct ncr53c9x_softc *);
|
||||
@ -294,21 +321,21 @@ struct ncr53c9x_softc {
|
||||
int sc_cfflags; /* Copy of config flags */
|
||||
|
||||
/* register defaults */
|
||||
u_char sc_cfg1; /* Config 1 */
|
||||
u_char sc_cfg2; /* Config 2, not ESP100 */
|
||||
u_char sc_cfg3; /* Config 3, ESP200,FAS */
|
||||
u_char sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
|
||||
u_char sc_cfg4; /* Config 4, only ESP200 */
|
||||
u_char sc_cfg5; /* Config 5, only ESP200 */
|
||||
u_char sc_ccf; /* Clock Conversion */
|
||||
u_char sc_timeout;
|
||||
uint8_t sc_cfg1; /* Config 1 */
|
||||
uint8_t sc_cfg2; /* Config 2, not ESP100 */
|
||||
uint8_t sc_cfg3; /* Config 3, ESP200,FAS */
|
||||
uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
|
||||
uint8_t sc_cfg4; /* Config 4, only ESP200 */
|
||||
uint8_t sc_cfg5; /* Config 5, only ESP200 */
|
||||
uint8_t sc_ccf; /* Clock Conversion */
|
||||
uint8_t sc_timeout;
|
||||
|
||||
/* register copies, see espreadregs() */
|
||||
u_char sc_espintr;
|
||||
u_char sc_espstat;
|
||||
u_char sc_espstep;
|
||||
u_char sc_espstat2;
|
||||
u_char sc_espfflags;
|
||||
uint8_t sc_espintr;
|
||||
uint8_t sc_espstat;
|
||||
uint8_t sc_espstep;
|
||||
uint8_t sc_espstat2;
|
||||
uint8_t sc_espfflags;
|
||||
|
||||
/* Lists of command blocks */
|
||||
TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
|
||||
@ -318,33 +345,33 @@ struct ncr53c9x_softc {
|
||||
struct ncr53c9x_tinfo *sc_tinfo;
|
||||
|
||||
/* Data about the current nexus (updated for every cmd switch) */
|
||||
caddr_t sc_dp; /* Current data pointer */
|
||||
void *sc_dp; /* Current data pointer */
|
||||
ssize_t sc_dleft; /* Data left to transfer */
|
||||
|
||||
/* Adapter state */
|
||||
int sc_phase; /* Copy of what bus phase we are in */
|
||||
int sc_prevphase; /* Copy of what bus phase we were in */
|
||||
u_char sc_state; /* State applicable to the adapter */
|
||||
u_char sc_flags; /* See below */
|
||||
u_char sc_selid;
|
||||
u_char sc_lastcmd;
|
||||
uint8_t sc_state; /* State applicable to the adapter */
|
||||
uint8_t sc_flags; /* See below */
|
||||
uint8_t sc_selid;
|
||||
uint8_t sc_lastcmd;
|
||||
|
||||
/* Message stuff */
|
||||
u_short sc_msgify; /* IDENTIFY message associated with nexus */
|
||||
u_short sc_msgout; /* What message is on its way out? */
|
||||
u_short sc_msgpriq; /* One or more messages to send (encoded) */
|
||||
u_short sc_msgoutq; /* What messages have been sent so far? */
|
||||
uint16_t sc_msgify; /* IDENTIFY message associated with nexus */
|
||||
uint16_t sc_msgout; /* What message is on its way out? */
|
||||
uint16_t sc_msgpriq; /* One or more messages to send (encoded) */
|
||||
uint16_t sc_msgoutq; /* What messages have been sent so far? */
|
||||
|
||||
u_char *sc_omess; /* MSGOUT buffer */
|
||||
uint8_t *sc_omess; /* MSGOUT buffer */
|
||||
int sc_omess_self; /* MSGOUT buffer is self-allocated */
|
||||
caddr_t sc_omp; /* Message pointer (for multibyte messages) */
|
||||
void *sc_omp; /* Message pointer (for multibyte messages) */
|
||||
size_t sc_omlen;
|
||||
u_char *sc_imess; /* MSGIN buffer */
|
||||
uint8_t *sc_imess; /* MSGIN buffer */
|
||||
int sc_imess_self; /* MSGIN buffer is self-allocated */
|
||||
caddr_t sc_imp; /* Message pointer (for multibyte messages) */
|
||||
void *sc_imp; /* Message pointer (for multibyte messages) */
|
||||
size_t sc_imlen;
|
||||
|
||||
caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */
|
||||
void *sc_cmdp; /* Command pointer (for DMAed commands) */
|
||||
size_t sc_cmdlen; /* Size of command in transit */
|
||||
|
||||
/* Hardware attributes */
|
||||
@ -434,10 +461,10 @@ struct ncr53c9x_softc {
|
||||
#ifdef NCR53C9X_DEBUG
|
||||
#define NCRCMD(sc, cmd) do { \
|
||||
if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
|
||||
printf("<CMD:0x%x %d>", (unsigned)cmd, __LINE__); \
|
||||
printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__); \
|
||||
sc->sc_lastcmd = cmd; \
|
||||
NCR_WRITE_REG(sc, NCR_CMD, cmd); \
|
||||
} while (0)
|
||||
} while (/* CONSTCOND */ 0)
|
||||
#else
|
||||
#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
|
||||
#endif
|
||||
|
||||
@ -85,7 +85,11 @@ __FBSDID("$FreeBSD$");
|
||||
#define LDB_PP 4
|
||||
#define LDB_ANY 0xff
|
||||
int lsi64854debug = 0;
|
||||
#define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0)
|
||||
#define DPRINTF(a,x) \
|
||||
do { \
|
||||
if ((lsi64854debug & (a)) != 0) \
|
||||
printf x; \
|
||||
} while (/* CONSTCOND */0)
|
||||
#else
|
||||
#define DPRINTF(a,x)
|
||||
#endif
|
||||
@ -94,12 +98,12 @@ int lsi64854debug = 0;
|
||||
|
||||
static void lsi64854_reset(struct lsi64854_softc *);
|
||||
static void lsi64854_map_scsi(void *, bus_dma_segment_t *, int, int);
|
||||
static int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *,
|
||||
static int lsi64854_setup(struct lsi64854_softc *, void **, size_t *,
|
||||
int, size_t *);
|
||||
static int lsi64854_scsi_intr(void *);
|
||||
static int lsi64854_enet_intr(void *);
|
||||
static int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *,
|
||||
int, size_t *);
|
||||
static int lsi64854_setup_pp(struct lsi64854_softc *, void **,
|
||||
size_t *, int, size_t *);
|
||||
static int lsi64854_pp_intr(void *);
|
||||
|
||||
/*
|
||||
@ -235,7 +239,7 @@ lsi64854_detach(struct lsi64854_softc *sc)
|
||||
else \
|
||||
panic(MSG); \
|
||||
} \
|
||||
} while (0)
|
||||
} while (/* CONSTCOND */0)
|
||||
|
||||
#define DMA_DRAIN(sc, dontpanic) do { \
|
||||
uint32_t csr; \
|
||||
@ -264,7 +268,7 @@ lsi64854_detach(struct lsi64854_softc *sc)
|
||||
* rev0 & rev1 call this PACKCNT \
|
||||
*/ \
|
||||
DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
|
||||
} while(0)
|
||||
} while (/* CONSTCOND */0)
|
||||
|
||||
#define DMA_FLUSH(sc, dontpanic) do { \
|
||||
uint32_t csr; \
|
||||
@ -279,7 +283,7 @@ lsi64854_detach(struct lsi64854_softc *sc)
|
||||
csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
|
||||
csr |= L64854_INVALIDATE; /* XXX FAS ? */ \
|
||||
L64854_SCSR(sc,csr); \
|
||||
} while(0)
|
||||
} while (/* CONSTCOND */0)
|
||||
|
||||
static void
|
||||
lsi64854_reset(struct lsi64854_softc *sc)
|
||||
@ -373,7 +377,7 @@ lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error)
|
||||
* setup a DMA transfer
|
||||
*/
|
||||
static int
|
||||
lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
|
||||
lsi64854_setup(struct lsi64854_softc *sc, void **addr, size_t *len,
|
||||
int datain, size_t *dmasize)
|
||||
{
|
||||
long bcnt;
|
||||
@ -547,7 +551,7 @@ lsi64854_scsi_intr(void *arg)
|
||||
}
|
||||
|
||||
*sc->sc_dmalen -= trans;
|
||||
*sc->sc_dmaaddr += trans;
|
||||
*sc->sc_dmaaddr = (char *)*sc->sc_dmaaddr + trans;
|
||||
|
||||
#if 0 /* this is not normal operation just yet */
|
||||
if (*sc->sc_dmalen == 0 || nsc->sc_phase != nsc->sc_prevphase)
|
||||
@ -620,7 +624,7 @@ lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
|
||||
* setup a DMA transfer
|
||||
*/
|
||||
static int
|
||||
lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
|
||||
lsi64854_setup_pp(struct lsi64854_softc *sc, void **addr, size_t *len,
|
||||
int datain, size_t *dmasize)
|
||||
{
|
||||
uint32_t csr;
|
||||
@ -714,7 +718,7 @@ lsi64854_pp_intr(void *arg)
|
||||
if (trans < 0) /* transferred < 0? */
|
||||
trans = sc->sc_dmasize;
|
||||
*sc->sc_dmalen -= trans;
|
||||
*sc->sc_dmaaddr += trans;
|
||||
*sc->sc_dmaaddr = (char *)*sc->sc_dmaaddr + trans;
|
||||
|
||||
if (sc->sc_dmasize != 0) {
|
||||
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
|
||||
|
||||
@ -51,12 +51,12 @@ struct lsi64854_softc {
|
||||
bus_dma_tag_t sc_buffer_dmat;
|
||||
int sc_datain;
|
||||
size_t sc_dmasize;
|
||||
caddr_t *sc_dmaaddr;
|
||||
void **sc_dmaaddr;
|
||||
size_t *sc_dmalen;
|
||||
|
||||
void (*reset)(struct lsi64854_softc *);/* reset routine */
|
||||
int (*setup)(struct lsi64854_softc *, caddr_t *, size_t *,
|
||||
int, size_t *); /* DMA setup */
|
||||
int (*setup)(struct lsi64854_softc *, void **, size_t *,
|
||||
int, size_t *); /* DMA setup */
|
||||
int (*intr)(void *); /* interrupt handler */
|
||||
|
||||
u_int sc_dmactl;
|
||||
@ -78,7 +78,7 @@ struct lsi64854_softc {
|
||||
uint32_t csr = L64854_GCSR(sc); \
|
||||
csr |= L64854_INT_EN; \
|
||||
L64854_SCSR(sc, csr); \
|
||||
} while (0)
|
||||
} while (/* CONSTCOND */0)
|
||||
|
||||
#define DMA_ISINTR(sc) (L64854_GCSR(sc) & (D_INT_PEND|D_ERR_PEND))
|
||||
|
||||
@ -87,7 +87,7 @@ struct lsi64854_softc {
|
||||
csr |= D_EN_DMA; \
|
||||
L64854_SCSR(sc, csr); \
|
||||
sc->sc_active = 1; \
|
||||
} while (0)
|
||||
} while (/* CONSTCOND */0)
|
||||
|
||||
int lsi64854_attach(struct lsi64854_softc *);
|
||||
int lsi64854_detach(struct lsi64854_softc *);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user