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Use the new(-ish) CP15_SCTLR macro to generate system control reg accesses

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where possible.  In the places that doesn't work (multi-line inline asm,
and places where the old armv4 cpufuncs mechanism is used), annotate the
accesses with a comment that includes SCTLR.  Now a grep -i sctlr can find
all the system control register manipulations.

No functional changes.
This commit is contained in:
Ian Lepore 2016-05-23 20:07:17 +00:00
parent 3f54ec85e8
commit 2c96ac7a39
10 changed files with 41 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sys/arm/arm/cpufunc.c
View File

@ -886,7 +886,7 @@ arm9_setup(void)
/* Clear out the cache */
cpu_idcache_wbinv_all();
/* Set the control register */
/* Set the control register (SCTLR) */
cpu_control(cpuctrlmask, cpuctrl);
}

13
sys/arm/arm/cpufunc_asm.S
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@ -68,7 +68,7 @@ ENTRY(cpu_ident)
END(cpu_ident)
ENTRY(cpu_get_control)
mrc p15, 0, r0, c1, c0, 0
mrc CP15_SCTLR(r0)
RET
END(cpu_get_control)
@ -98,13 +98,6 @@ END(cpu_faultaddress)
* All other registers are CPU architecture specific
*/
#if 0 /* See below. */
ENTRY(cpufunc_control)
mcr p15, 0, r0, c1, c0, 0
RET
END(cpufunc_control)
#endif
ENTRY(cpu_domains)
mcr p15, 0, r0, c3, c0, 0
RET
@ -121,13 +114,13 @@ END(cpu_domains)
*/
ENTRY(cpufunc_control)
mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
mrc CP15_SCTLR(r3) /* Read the control register */
bic r2, r3, r0 /* Clear bits */
eor r2, r2, r1 /* XOR bits */
teq r2, r3 /* Only write if there is a change */
mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
mcrne CP15_SCTLR(r2) /* Write new control register */
mov r0, r3 /* Return old value */
RET

4
sys/arm/arm/cpufunc_asm_xscale.S
View File

@ -111,13 +111,13 @@ END(xscale_cpwait)
* changes in the control register.
*/
ENTRY(xscale_control)
mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
mrc CP15_SCTLR(r3) /* Read the control register */
bic r2, r3, r0 /* Clear bits */
eor r2, r2, r1 /* XOR bits */
teq r2, r3 /* Only write if there was a change */
mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
mcrne CP15_SCTLR(r3) /* Write new control register */
mov r0, r3 /* Return old value */
CPWAIT_AND_RETURN(r1)

16
sys/arm/arm/elf_trampoline.c
View File

@ -227,14 +227,14 @@ _startC(void)
"bic %0, %0, #0xff000000\n"
"and %1, %1, #0xff000000\n"
"orr %0, %0, %1\n"
"mrc p15, 0, %1, c1, c0, 0\n"
"mrc p15, 0, %1, c1, c0, 0\n" /* CP15_SCTLR(%1)*/
"bic %1, %1, #1\n" /* Disable MMU */
"orr %1, %1, #(4 | 8)\n" /* Add DC enable,
WBUF enable */
"orr %1, %1, #0x1000\n" /* Add IC enable */
"orr %1, %1, #(0x800)\n" /* BPRD enable */
"mcr p15, 0, %1, c1, c0, 0\n"
"mcr p15, 0, %1, c1, c0, 0\n" /* CP15_SCTLR(%1)*/
"nop\n"
"nop\n"
"nop\n"
@ -599,9 +599,9 @@ load_kernel(unsigned int kstart, unsigned int curaddr,unsigned int func_end,
__asm __volatile("mcr p15, 0, %0, c7, c5, 0\n"
"mcr p15, 0, %0, c7, c10, 4\n"
: : "r" (curaddr));
__asm __volatile("mrc p15, 0, %0, c1, c0, 0\n"
__asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/
"bic %0, %0, #1\n" /* MMU_ENABLE */
"mcr p15, 0, %0, c1, c0, 0\n"
"mcr p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/
: "=r" (ssym));
/* Jump to the entry point. */
((void(*)(void))(entry_point - KERNVIRTADDR + curaddr))();
@ -643,9 +643,9 @@ setup_pagetables(unsigned int pt_addr, vm_paddr_t physstart, vm_paddr_t physend,
__asm __volatile("mcr p15, 0, %1, c2, c0, 0\n" /* set TTB */
"mcr p15, 0, %1, c8, c7, 0\n" /* Flush TTB */
"mcr p15, 0, %2, c3, c0, 0\n" /* Set DAR */
"mrc p15, 0, %0, c1, c0, 0\n"
"mrc p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/
"orr %0, %0, #1\n" /* MMU_ENABLE */
"mcr p15, 0, %0, c1, c0, 0\n"
"mcr p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/
"mrc p15, 0, %0, c2, c0, 0\n" /* CPWAIT */
"mov r0, r0\n"
"sub pc, pc, #4\n" :
@ -700,9 +700,9 @@ __start(void)
*/
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
__asm __volatile("mrc p15, 0, %0, c1, c0, 0\n"
__asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/
"bic %0, %0, #1\n" /* MMU_DISABLE */
"mcr p15, 0, %0, c1, c0, 0\n"
"mcr p15, 0, %0, c1, c0, 0\n" /* CP15_SCTLR(%0)*/
:"=r" (pt_addr));
} else
#endif

12
sys/arm/arm/locore-v4.S
View File

@ -114,7 +114,7 @@ ASENTRY_NP(_start)
* If we're running with MMU disabled, test against the
* physical address instead.
*/
mrc p15, 0, r2, c1, c0, 0
mrc CP15_SCTLR(r2)
ands r2, r2, #CPU_CONTROL_MMU_ENABLE
ldreq r6, =PHYSADDR
ldrne r6, =LOADERRAMADDR
@ -146,12 +146,12 @@ from_ram:
disable_mmu:
/* Disable MMU for a while */
mrc p15, 0, r2, c1, c0, 0
mrc CP15_SCTLR(r2)
bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
CPU_CONTROL_WBUF_ENABLE)
bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
mcr p15, 0, r2, c1, c0, 0
mcr CP15_SCTLR(r2)
nop
nop
@ -213,9 +213,9 @@ Lunmapped:
/*
* Enable MMU.
*/
mrc p15, 0, r0, c1, c0, 0
mrc CP15_SCTLR(r0)
orr r0, r0, #(CPU_CONTROL_MMU_ENABLE)
mcr p15, 0, r0, c1, c0, 0
mcr CP15_SCTLR(r0)
nop
nop
nop
@ -398,7 +398,7 @@ ENTRY_NP(cpu_halt)
* Hurl ourselves into the ROM
*/
mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
mcr p15, 0, r0, c1, c0, 0
mcr CP15_SCTLR(r0)
mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
mov pc, r4

13
sys/arm/arm/machdep.c
View File

@ -416,20 +416,15 @@ arm_vector_init(vm_offset_t va, int which)
if (va == ARM_VECTORS_HIGH) {
/*
* Assume the MD caller knows what it's doing here, and
* really does want the vector page relocated.
* Enable high vectors in the system control reg (SCTLR).
*
* Assume the MD caller knows what it's doing here, and really
* does want the vector page relocated.
*
* Note: This has to be done here (and not just in
* cpu_setup()) because the vector page needs to be
* accessible *before* cpu_startup() is called.
* Think ddb(9) ...
*
* NOTE: If the CPU control register is not readable,
* this will totally fail! We'll just assume that
* any system that has high vector support has a
* readable CPU control register, for now. If we
* ever encounter one that does not, we'll have to
* rethink this.
*/
cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC);
}

7
sys/arm/at91/at91_machdep.c
View File

@ -584,6 +584,10 @@ initarm(struct arm_boot_params *abp)
memsize = 16 * 1024 * 1024;
}
/* Enable MMU (set SCTLR), and do other cpu-specific setup. */
cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
cpu_setup();
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
@ -592,9 +596,6 @@ initarm(struct arm_boot_params *abp)
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
cpu_setup();
set_stackptrs(0);
/*

5
sys/arm/cavium/cns11xx/econa_machdep.c
View File

@ -272,6 +272,9 @@ initarm(struct arm_boot_params *abp)
mem_info = ((*ddr) >> 4) & 0x3;
memsize = (8<<mem_info)*1024*1024;
/* Enable MMU in system control register (SCTLR). */
cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
@ -280,8 +283,6 @@ initarm(struct arm_boot_params *abp)
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
set_stackptrs(0);
/*

1
sys/arm/include/cpu-v4.h
View File

@ -105,6 +105,7 @@ _RF0(cp15_midr_get, CP15_MIDR(%0))
_RF0(cp15_ctr_get, CP15_CTR(%0))
_RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
_RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
_RF0(cp15_sctlr_get, CP15_SCTLR(%0))
#undef _FX
#undef _RF0

11
sys/arm/mv/mv_machdep.c
View File

@ -50,11 +50,18 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/acle-compat.h>
#include <machine/bus.h>
#include <machine/fdt.h>
#include <machine/machdep.h>
#include <machine/platform.h>
#if __ARM_ARCH < 6
#include <machine/cpu-v4.h>
#else
#include <machine/cpu-v6.h>
#endif
#include <arm/mv/mvreg.h> /* XXX */
#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */
#include <arm/mv/mvwin.h>
@ -453,9 +460,9 @@ DB_SHOW_COMMAND(cp15, db_show_cp15)
__asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg));
db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
__asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg));
reg = cp15_sctlr_get();
db_printf("Ctrl: 0x%08x\n",reg);
__asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg));
reg = cp15_actlr_get();
db_printf("Aux Ctrl: 0x%08x\n",reg);
__asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg));