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Merge commit e578d0fd2 from llvm git (by Simon Atanasyan):

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[mips] Fix `__mips_isa_rev` macros value for Octeon CPU

This is one of the upstream changes needed for adding support for the
OCTEON+ CPU type, so that we can test Clang builds using the most
commonly available FreeBSD/mips64 reference platform, the Edge Router
Lite.

Requested by:	kevans
MFC after:	1 month
X-MFC-With:	r353358
This commit is contained in:
Dimitry Andric 2019-11-21 20:32:34 +00:00
parent 44344578f8
commit 2e197b24c5
1 changed files with 1 additions and 1 deletions
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2
contrib/llvm/tools/clang/lib/Basic/Targets/Mips.cpp
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@ -62,7 +62,7 @@ void MipsTargetInfo::fillValidCPUList(
unsigned MipsTargetInfo::getISARev() const {
return llvm::StringSwitch<unsigned>(getCPU())
.Cases("mips32", "mips64", 1)
.Cases("mips32r2", "mips64r2", 2)
.Cases("mips32r2", "mips64r2", "octeon", 2)
.Cases("mips32r3", "mips64r3", 3)
.Cases("mips32r5", "mips64r5", 5)
.Cases("mips32r6", "mips64r6", 6)