- MFi386: sys/i386/i386/intr_machdep.c rev. 1.11
Don't use atomic ops to increment interrupt stats. On sparc64 this reduces delay until tick interrupts are service by 1/10th on average. In turn this reduces the clock drift caused by these delays so there's less drift which has to be compensated in tick_hardclock(). This includes switching from atomically incrementing the global cnt.v_intr to the asm equivalent of PCPU_LAZY_INC(cnt.v_intr) in exception.S - Correct some comments to match the registers actually used. - Correct some format specifiers, interrupt levels passed in are u_int. - Use FBSDID. Ok'ed by: jhb
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@ -2320,14 +2320,16 @@ ENTRY(tl0_intr)
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lduh [%l0 + %l1], %l0
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sllx %l0, 3, %l0
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add %l0, %l2, %l0
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ATOMIC_INC_ULONG(%l0, %l1, %l2)
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ldx [%l0], %l1
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inc %l1
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stx %l1, [%l0]
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call critical_enter
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nop
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SET(cnt+V_INTR, %l1, %l0)
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ATOMIC_INC_INT(%l0, %l1, %l2)
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lduw [PCPU(CNT) + V_INTR], %l0
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inc %l0
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stw %l0, [PCPU(CNT) + V_INTR]
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SET(intr_handlers, %l1, %l0)
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sllx %l3, IH_SHIFT, %l1
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@ -2779,7 +2781,7 @@ ENTRY(tl1_intr)
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#if KTR_COMPILE & KTR_INTR
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CATR(KTR_INTR,
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"tl1_intr: td=%p level=%#lx pil=%#lx pc=%#lx sp=%#lx"
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"tl1_intr: td=%p level=%#x pil=%#lx pc=%#lx sp=%#lx"
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, %g1, %g2, %g3, 7, 8, 9)
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ldx [PCPU(CURTHREAD)], %g2
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stx %g2, [%g1 + KTR_PARM1]
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@ -2827,7 +2829,7 @@ ENTRY(tl1_intr)
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mov %l5, PCPU_REG
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wrpr %g0, PSTATE_KERNEL, %pstate
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/* %l3 contains PIL */
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/* %l7 contains PIL */
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SET(intrcnt, %l5, %l4)
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prefetcha [%l4] ASI_N, 1
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SET(pil_countp, %l5, %l6)
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@ -2835,14 +2837,16 @@ ENTRY(tl1_intr)
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lduh [%l5 + %l6], %l5
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sllx %l5, 3, %l5
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add %l5, %l4, %l4
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ATOMIC_INC_ULONG(%l4, %l5, %l6)
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ldx [%l4], %l5
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inc %l5
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stx %l5, [%l4]
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call critical_enter
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nop
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SET(cnt+V_INTR, %l5, %l4)
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ATOMIC_INC_INT(%l4, %l5, %l6)
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lduw [PCPU(CNT) + V_INTR], %l4
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inc %l4
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stw %l4, [PCPU(CNT) + V_INTR]
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SET(intr_handlers, %l5, %l4)
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sllx %l7, IH_SHIFT, %l5
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@ -2880,7 +2884,7 @@ ENTRY(tl1_intr)
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wrpr %g3, 0, %tnpc
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#if KTR_COMPILE & KTR_INTR
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CATR(KTR_INTR, "tl1_intr: td=%#lx pil=%#lx ts=%#lx pc=%#lx sp=%#lx"
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CATR(KTR_INTR, "tl1_intr: td=%#x pil=%#lx ts=%#lx pc=%#lx sp=%#lx"
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, %g2, %g3, %g4, 7, 8, 9)
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ldx [PCPU(CURTHREAD)], %g3
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stx %g3, [%g2 + KTR_PARM1]
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@ -24,9 +24,11 @@
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* SUCH DAMAGE.
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*
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* from: @(#)genassym.c 5.11 (Berkeley) 5/10/91
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_kstack_pages.h"
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#include <sys/param.h>
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@ -197,6 +199,7 @@ ASSYM(PC_TLB_CTX, offsetof(struct pcpu, pc_tlb_ctx));
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ASSYM(PC_TLB_CTX_MAX, offsetof(struct pcpu, pc_tlb_ctx_max));
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ASSYM(PC_TLB_CTX_MIN, offsetof(struct pcpu, pc_tlb_ctx_min));
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ASSYM(PC_PMAP, offsetof(struct pcpu, pc_pmap));
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ASSYM(PC_CNT, offsetof(struct pcpu, pc_cnt));
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ASSYM(PC_SIZEOF, sizeof(struct pcpu));
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ASSYM(IH_SHIFT, IH_SHIFT);
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@ -171,16 +171,17 @@ ENTRY(intr_fast)
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ldx [%l0 + IR_ARG], %o1
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lduw [%l0 + IR_VEC], %o2
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/* load intrcnt[intr_countp[%o2]] into %l4 */
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SET(intrcnt, %l7, %l2) /* %l5 = intrcnt */
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/* intrcnt[intr_countp[%o2]]++ */
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SET(intrcnt, %l7, %l2) /* %l2 = intrcnt */
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prefetcha [%l2] ASI_N, 1
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SET(intr_countp, %l7, %l3) /* %l6 = intr_countp */
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SET(intr_countp, %l7, %l3) /* %l3 = intr_countp */
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sllx %o2, 1, %l4 /* %l4 = vec << 1 */
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lduh [%l4 + %l3], %l5 /* %l6 = intr_countp[%o2] */
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lduh [%l4 + %l3], %l5 /* %l5 = intr_countp[%o2] */
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sllx %l5, 3, %l6 /* %l6 = intr_countp[%o2] << 3 */
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add %l6, %l2, %l7 /* %l4 = intrcnt[intr_countp[%o2]] */
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ATOMIC_INC_ULONG(%l7, %l5, %l2)
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add %l6, %l2, %l7 /* %l7 = intrcnt[intr_countp[%o2]] */
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ldx [%l7], %l2
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inc %l2
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stx %l2, [%l7]
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ldx [PCPU(IRFREE)], %l1
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stx %l1, [%l0 + IR_NEXT]
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@ -199,7 +199,7 @@ intr_stray_vector(void *cookie)
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iv = cookie;
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if (intr_stray_count[iv->iv_vec] < MAX_STRAY_LOG) {
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printf("stray vector interrupt %d\n", iv->iv_vec);
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atomic_add_long(&intr_stray_count[iv->iv_vec], 1);
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intr_stray_count[iv->iv_vec]++;
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if (intr_stray_count[iv->iv_vec] >= MAX_STRAY_LOG)
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printf("got %d stray interrupt %d's: not logging "
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"anymore\n", MAX_STRAY_LOG, iv->iv_vec);
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